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| www..com User's Manual 78K0/KF2 8-Bit Single-Chip Microcontrollers PD78F0544 PD78F0545 PD78F0546 PD78F0547 PD78F0547D PD78F0544(A) PD78F0545(A) PD78F0546(A) PD78F0547(A) The PD78F0547D has an on-chip debug function. Do not use this product for mass production because its reliability cannot be guaranteed after the on-chip debug function has been used, due to issues with respect to the number of times the flash memory can be rewritten. NEC Electronics does not accept complaints concerning this product. Document No. U17397EJ4V0UD00 (4th edition) Date Published May 2006 NS CP(K) 2005 Printed in Japan www..com [MEMO] 2 User's Manual U17397EJ4V0UD www..com NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. User's Manual U17397EJ4V0UD 3 www..com EEPROM is a trademark of NEC Electronics Corporation. Windows and Windows NT are registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. 4 User's Manual U17397EJ4V0UD www..com Caution: This product uses SuperFlash(R) technology licensed from Silicon Storage Technology, Inc. * The information in this document is current as of May, 2006. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1 User's Manual U17397EJ4V0UD 5 www..com [MEMO] 6 User's Manual U17397EJ4V0UD www..com INTRODUCTION Readers This manual is intended for user engineers who wish to understand the functions of the 78K0/KF2 and design and develop application systems and programs for these devices. The target products are as follows. 78K0/KF2: PD78F0544, 78F0545, 78F0546, 78F0547, 78F0547D, 78F0544(A), 78F0545(A), 78F0546(A), 78F0547(A) This manual is intended to give users an understanding of the functions described in the Organization below. Organization The 78K0/KF2 manual is separated into two parts: this manual and the instructions edition (common to the 78K/0 Series). 78K0/KF2 User's Manual (This Manual) 78K/0 Series User's Manual Instructions * Pin functions * Internal block functions * Interrupts * Other on-chip peripheral functions * Electrical specifications How to Read This Manual * CPU functions * Instruction set * Explanation of each instruction It is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. * When using this manual as the manual for (A) grade products : Only the quality grade differs between standard products and (A) grade products. Read the part number as follows. * PD78F0544 PD78F0544(A) * PD78F0545 PD78F0545(A) * PD78F0546 PD78F0546(A) * PD78F0547 PD78F0547(A) * To gain a general understanding of functions: Read this manual in the order of the CONTENTS. The mark " User's Manual U17397EJ4V0UD 7 www..com * To know details of the 78K/0 Series instructions: Refer to the separate document 78K/0 Series Instructions User's Manual (U12326E). Conventions Data significance: Note: Caution: Remark: Higher digits on the left and lower digits on the right Footnote for item marked with Note in the text Information requiring particular attention Supplementary information ... xxxx or xxxxB Decimal Hexadecimal Related Documents ... xxxx ... xxxxH Active low representations: xxx (overscore over pin and signal name) Numerical representations: Binary The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name 78K0/KF2 User's Manual 78K/0 Series Instructions User's Manual 78K0/Kx2 Flash Memory Programming (Programmer) Application Note 78K0/Kx2 Flash Memory Self Programming User's Manual Note Document No. This manual U12326E U17739E U17516E Note This document is under engineering management. For details, consult an NEC Electronics sales representative. Documents Related to Development Tools (Software) (User's Manuals) Document Name RA78K0 Ver. 3.80 Assembler Package Operation Language Structured Assembly Language CC78K0 Ver. 3.70 C Compiler Operation Language SM+ System Simulator Operation User Open Interface ID78K0-QB Ver. 2.90 Integrated Debugger PM+ Ver. 5.20 Operation Document No. U17199E U17198E U17197E U17201E U17200E U17246E U17247E U17437E U16934E Documents Related to Development Tools (Hardware) (User's Manuals) Document Name QB-78K0KX2 In-Circuit Emulator QB-78K0MINI On-Chip Debug Emulator Document No. U17341E U17029E Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing. 8 User's Manual U17397EJ4V0UD www..com Documents Related to Flash Memory Programming Document Name PG-FP4 Flash Memory Programmer User's Manual PG-FP3 Flash Memory Programmer User's Manual Document No. U15260E U17454E Other Documents Document Name SEMICONDUCTOR SELECTION GUIDE - Products and Packages - Semiconductor Device Mount Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Document No. X13769X Note C11531E C10983E C11892E Note See the "Semiconductor Device Mount Manual" website (http://www.necel.com/pkg/en/mount/index.html). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing. User's Manual U17397EJ4V0UD 9 www..com CONTENTS CHAPTER 1 OUTLINE ............................................................................................................................ 19 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Features .................................................................................................................................... 19 Applications.............................................................................................................................. 20 Ordering Information ............................................................................................................... 21 Pin Configuration (Top View).................................................................................................. 22 78K0/Kx2 Series Lineup .......................................................................................................... 24 Block Diagram .......................................................................................................................... 27 Outline of Functions ................................................................................................................ 28 CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 30 2.1 2.2 Pin Function List ...................................................................................................................... 30 Description of Pin Functions .................................................................................................. 34 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 2.2.8 2.2.9 2.2.10 2.2.11 2.2.12 2.2.13 2.2.14 2.2.15 2.2.16 2.2.17 2.2.18 P00 to P06 (port 0) .................................................................................................................... 34 P10 to P17 (port 1) .................................................................................................................... 35 P20 to P27 (port 2) .................................................................................................................... 36 P30 to P33 (port 3) .................................................................................................................... 36 P40 to P47 (port 4) .................................................................................................................... 37 P50 to P57 (port 5) .................................................................................................................... 37 P60 to P67 (port 6) .................................................................................................................... 37 P70 to P77 (port 7) .................................................................................................................... 38 P120 to P124 (port 12) .............................................................................................................. 38 P130 (port 13) ........................................................................................................................... 39 P140 to P145 (port 14) .............................................................................................................. 39 AVREF......................................................................................................................................... 40 AVSS .......................................................................................................................................... 40 RESET ...................................................................................................................................... 40 REGC........................................................................................................................................ 40 VDD and EVDD ............................................................................................................................ 41 VSS and EVSS............................................................................................................................. 41 FLMD0 ...................................................................................................................................... 41 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins....................................... 42 CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 46 3.1 Memory Space .......................................................................................................................... 46 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 Internal program memory space................................................................................................ 54 Memory bank (PD78F0546, 78F0547, and 78F0547D only)................................................... 55 Internal data memory space...................................................................................................... 56 Special function register (SFR) area ......................................................................................... 56 Data memory addressing .......................................................................................................... 57 Control registers ........................................................................................................................ 61 General-purpose registers......................................................................................................... 65 Special function registers (SFRs) .............................................................................................. 66 User's Manual U17397EJ4V0UD 3.2 Processor Registers ................................................................................................................ 61 3.2.1 3.2.2 3.2.3 10 www..com 3.3 Instruction Address Addressing ............................................................................................ 71 3.3.1 3.3.2 3.3.3 3.3.4 Relative addressing....................................................................................................................71 Immediate addressing................................................................................................................72 Table indirect addressing ...........................................................................................................73 Register addressing ...................................................................................................................73 Implied addressing .....................................................................................................................74 Register addressing ...................................................................................................................75 Direct addressing .......................................................................................................................76 Short direct addressing ..............................................................................................................77 Special function register (SFR) addressing................................................................................78 Register indirect addressing.......................................................................................................79 Based addressing ......................................................................................................................80 Based indexed addressing.........................................................................................................81 Stack addressing .......................................................................................................................82 3.4 Operand Address Addressing ................................................................................................ 74 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 3.4.9 CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F0546, 78F0547, AND 78F0547D ONLY)......................................................... 83 4.1 4.2 4.3 4.4 Memory Bank ........................................................................................................................... 83 Difference in Representation of Memory Space ................................................................... 84 Memory Bank Select Register (BANK) .................................................................................. 85 Selecting Memory Bank .......................................................................................................... 86 4.4.1 4.4.2 4.4.3 4.4.4 Referencing values between memory banks .............................................................................86 Branching instruction between memory banks...........................................................................88 Subroutine call between memory banks ....................................................................................90 Instruction branch to bank area by interrupt...............................................................................92 CHAPTER 5 PORT FUNCTIONS........................................................................................................... 94 5.1 5.2 Port Functions.......................................................................................................................... 94 Port Configuration ................................................................................................................... 96 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 5.2.9 5.2.10 5.2.11 Port 0 .........................................................................................................................................97 Port 1 .......................................................................................................................................101 Port 2 .......................................................................................................................................106 Port 3 .......................................................................................................................................107 Port 4 .......................................................................................................................................110 Port 5 .......................................................................................................................................111 Port 6 .......................................................................................................................................112 Port 7 .......................................................................................................................................115 Port 12 .....................................................................................................................................116 Port 13 .....................................................................................................................................119 Port 14 .....................................................................................................................................120 5.3 Registers Controlling Port Function ........................................................................................ 124 5.4 Port Function Operations.......................................................................................................... 129 5.4.1 5.4.2 5.4.3 Writing to I/O port .....................................................................................................................129 Reading from I/O port...............................................................................................................129 Operations on I/O port..............................................................................................................129 5.5 Settings of Port Mode Register and Output Latch When Using Alternate Function........... 129 5.6 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn).................................... 132 User's Manual U17397EJ4V0UD 11 www..com CHAPTER 6 CLOCK GENERATOR .................................................................................................... 133 6.1 6.2 6.3 6.4 Functions of Clock Generator............................................................................................... 133 Configuration of Clock Generator ........................................................................................ 134 Registers Controlling Clock Generator ............................................................................... 136 System Clock Oscillator ........................................................................................................ 145 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 X1 oscillator..............................................................................................................................145 XT1 oscillator ...........................................................................................................................145 When subsystem clock is not used ..........................................................................................148 Internal high-speed oscillator ...................................................................................................148 Internal low-speed oscillator.....................................................................................................148 Prescaler ..................................................................................................................................148 6.5 6.6 Clock Generator Operation ................................................................................................... 149 Controlling Clock ................................................................................................................... 153 6.6.1 6.6.2 6.6.3 6.6.4 6.6.5 6.6.6 6.6.7 6.6.8 6.6.9 6.6.10 Controlling high-speed system clock ........................................................................................153 Example of controlling internal high-speed oscillation clock.....................................................156 Example of controlling subsystem clock...................................................................................158 Example of controlling internal low-speed oscillation clock ......................................................160 Clocks supplied to CPU and peripheral hardware ....................................................................160 CPU clock status transition diagram.........................................................................................161 Condition before changing CPU clock and processing after changing CPU clock ...................166 Time required for switchover of CPU clock and main system clock .........................................167 Conditions before clock oscillation is stopped ..........................................................................168 Peripheral hardware and source clocks ...................................................................................169 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01......................................................... 170 7.1 7.2 7.3 7.4 Functions of 16-Bit Timer/Event Counters 00 and 01......................................................... 170 Configuration of 16-Bit Timer/Event Counters 00 and 01 .................................................. 171 Registers Controlling 16-Bit Timer/Event Counters 00 and 01 ......................................... 177 Operation of 16-Bit Timer/Event Counters 00 and 01......................................................... 189 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 7.4.8 Interval timer operation.............................................................................................................189 Square-wave output operation .................................................................................................192 External event counter operation..............................................................................................195 Operation in clear & start mode entered by TI00n pin valid edge input ....................................199 Free-running timer operation ....................................................................................................212 PPG output operation...............................................................................................................221 One-shot pulse output operation ..............................................................................................224 Pulse width measurement operation ........................................................................................229 Rewriting CR01n during TM0n operation .................................................................................237 Setting LVS0n and LVR0n .......................................................................................................237 7.5 Special Use of TM0n .............................................................................................................. 237 7.5.1 7.5.2 7.6 Cautions for 16-Bit Timer/Event Counters 00 and 01 ......................................................... 239 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51........................................................... 243 8.1 8.2 8.3 8.4 12 Functions of 8-Bit Timer/Event Counters 50 and 51........................................................... 243 Configuration of 8-Bit Timer/Event Counters 50 and 51 .................................................... 243 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 ........................................... 246 Operations of 8-Bit Timer/Event Counters 50 and 51......................................................... 251 User's Manual U17397EJ4V0UD www..com 8.4.1 8.4.2 8.4.3 8.4.4 Operation as interval timer .......................................................................................................251 Operation as external event counter ........................................................................................253 Square-wave output operation .................................................................................................254 PWM output operation .............................................................................................................255 8.5 Cautions for 8-Bit Timer/Event Counters 50 and 51........................................................... 259 CHAPTER 9 8-BIT TIMERS H0 AND H1 .......................................................................................... 260 9.1 9.2 9.3 9.4 Functions of 8-Bit Timers H0 and H1................................................................................... 260 Configuration of 8-Bit Timers H0 and H1 ............................................................................ 260 Registers Controlling 8-Bit Timers H0 and H1.................................................................... 264 Operation of 8-Bit Timers H0 and H1 ................................................................................... 269 9.4.1 9.4.2 9.4.3 Operation as interval timer/square-wave output.......................................................................269 Operation as PWM output........................................................................................................272 Carrier generator operation (8-bit timer H1 only) .....................................................................278 CHAPTER 10 WATCH TIMER ............................................................................................................. 285 10.1 10.2 10.3 10.4 Functions of Watch Timer..................................................................................................... 285 Configuration of Watch Timer .............................................................................................. 286 Register Controlling Watch Timer........................................................................................ 287 Watch Timer Operations ....................................................................................................... 289 10.4.1 10.4.2 Watch timer operation ..............................................................................................................289 Interval timer operation ............................................................................................................289 10.5 Cautions for Watch Timer ..................................................................................................... 290 CHAPTER 11 WATCHDOG TIMER ..................................................................................................... 291 11.1 11.2 11.3 11.4 Functions of Watchdog Timer .............................................................................................. 291 Configuration of Watchdog Timer........................................................................................ 292 Register Controlling Watchdog Timer ................................................................................. 293 Operation of Watchdog Timer .............................................................................................. 294 11.4.1 11.4.2 11.4.3 Controlling operation of watchdog timer...................................................................................294 Setting overflow time of watchdog timer...................................................................................295 Setting window open period of watchdog timer........................................................................296 CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER............................................... 298 12.1 12.2 12.3 12.4 Functions of Clock Output/Buzzer Output Controller........................................................ 298 Configuration of Clock Output/Buzzer Output Controller ................................................. 299 Registers Controlling Clock Output/Buzzer Output Controller......................................... 299 Operations of Clock Output/Buzzer Output Controller...................................................... 301 12.4.1 12.4.2 Operation as clock output ........................................................................................................301 Operation as buzzer output......................................................................................................301 CHAPTER 13 A/D CONVERTER ......................................................................................................... 302 13.1 13.2 13.3 13.4 Function of A/D Converter .................................................................................................... 302 Configuration of A/D Converter............................................................................................ 303 Registers Used in A/D Converter ......................................................................................... 305 A/D Converter Operations..................................................................................................... 313 User's Manual U17397EJ4V0UD 13 www..com 13.4.1 13.4.2 13.4.3 Basic operations of A/D converter ............................................................................................313 Input voltage and conversion results ........................................................................................315 A/D converter operation mode .................................................................................................316 13.5 13.6 How to Read A/D Converter Characteristics Table............................................................. 318 Cautions for A/D Converter................................................................................................... 320 CHAPTER 14 SERIAL INTERFACE UART0 ...................................................................................... 324 14.1 14.2 14.3 14.4 Functions of Serial Interface UART0.................................................................................... 324 Configuration of Serial Interface UART0 ............................................................................. 325 Registers Controlling Serial Interface UART0..................................................................... 328 Operation of Serial Interface UART0.................................................................................... 333 14.4.1 14.4.2 14.4.3 14.4.4 Operation stop mode................................................................................................................333 Asynchronous serial interface (UART) mode ...........................................................................334 Dedicated baud rate generator.................................................................................................340 Calculation of baud rate ...........................................................................................................341 CHAPTER 15 SERIAL INTERFACE UART6 ...................................................................................... 345 15.1 15.2 15.3 15.4 Functions of Serial Interface UART6.................................................................................... 345 Configuration of Serial Interface UART6 ............................................................................. 349 Registers Controlling Serial Interface UART6..................................................................... 352 Operation of Serial Interface UART6.................................................................................... 361 15.4.1 15.4.2 15.4.3 15.4.4 Operation stop mode................................................................................................................361 Asynchronous serial interface (UART) mode ...........................................................................362 Dedicated baud rate generator.................................................................................................375 Calculation of baud rate ...........................................................................................................377 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 ................................................................ 382 16.1 16.2 16.3 16.4 Functions of Serial Interfaces CSI10 and CSI11 ................................................................. 382 Configuration of Serial Interfaces CSI10 and CSI11........................................................... 383 Registers Controlling Serial Interfaces CSI10 and CSI11 .................................................. 385 Operation of Serial Interfaces CSI10 and CSI11 ................................................................. 390 16.4.1 16.4.2 Operation stop mode................................................................................................................390 3-wire serial I/O mode ..............................................................................................................391 CHAPTER 17 SERIAL INTERFACE CSIA0........................................................................................ 403 17.1 17.2 17.3 17.4 Functions of Serial Interface CSIA0 ..................................................................................... 403 Configuration of Serial Interface CSIA0............................................................................... 404 Registers Controlling Serial Interface CSIA0 ...................................................................... 406 Operation of Serial Interface CSIA0 ..................................................................................... 415 17.4.1 17.4.2 17.4.3 Operation stop mode................................................................................................................415 3-wire serial I/O mode ..............................................................................................................416 3-wire serial I/O mode with automatic transmit/receive function...............................................421 CHAPTER 18 SERIAL INTERFACE IIC0............................................................................................ 441 18.1 18.2 14 Functions of Serial Interface IIC0 ......................................................................................... 441 Configuration of Serial Interface IIC0................................................................................... 444 User's Manual U17397EJ4V0UD www..com 18.3 18.4 18.5 Registers to Control Serial Interface IIC0............................................................................ 447 I2C Bus Mode Functions ........................................................................................................ 460 18.4.1 18.5.1 18.5.2 18.5.3 18.5.4 18.5.5 18.5.6 18.5.7 18.5.8 18.5.9 18.5.10 18.5.11 18.5.12 18.5.13 18.5.14 18.5.15 18.5.16 18.5.17 Pin configuration ......................................................................................................................460 Start conditions ........................................................................................................................461 Addresses ................................................................................................................................462 Transfer direction specification ................................................................................................462 Acknowledge (ACK) .................................................................................................................463 Stop condition ..........................................................................................................................464 Wait..........................................................................................................................................465 Canceling wait..........................................................................................................................467 Interrupt request (INTIIC0) generation timing and wait control.................................................467 Address match detection method.............................................................................................468 Error detection .........................................................................................................................468 Extension code ........................................................................................................................469 Arbitration.................................................................................................................................470 Wakeup function ......................................................................................................................471 Communication reservation .....................................................................................................472 Cautions...................................................................................................................................475 Communication operations ......................................................................................................476 Timing of I2C interrupt request (INTIIC0) occurrence ...............................................................484 I2C Bus Definitions and Control Methods............................................................................ 461 18.6 Timing Charts......................................................................................................................... 505 CHAPTER 19 MULTIPLIER/DIVIDER................................................................................................... 512 19.1 19.2 19.3 19.4 Functions of Multiplier/Divider ............................................................................................. 512 Configuration of Multiplier/Divider....................................................................................... 512 Register Controlling Multiplier/Divider ................................................................................ 516 Operations of Multiplier/Divider ........................................................................................... 517 19.4.1 19.4.2 Multiplication operation ............................................................................................................517 Division operation ....................................................................................................................519 CHAPTER 20 INTERRUPT FUNCTIONS ............................................................................................ 521 20.1 20.2 20.3 20.4 Interrupt Function Types....................................................................................................... 521 Interrupt Sources and Configuration................................................................................... 521 Registers Controlling Interrupt Functions .......................................................................... 526 Interrupt Servicing Operations ............................................................................................. 534 20.4.1 20.4.2 20.4.3 20.4.4 Maskable interrupt acknowledgment........................................................................................534 Software interrupt request acknowledgment ............................................................................536 Multiple interrupt servicing .......................................................................................................537 Interrupt request hold ...............................................................................................................540 CHAPTER 21 KEY INTERRUPT FUNCTION ..................................................................................... 541 21.1 21.2 21.3 Functions of Key Interrupt .................................................................................................... 541 Configuration of Key Interrupt ............................................................................................. 541 Register Controlling Key Interrupt....................................................................................... 542 CHAPTER 22 STANDBY FUNCTION.................................................................................................. 543 User's Manual U17397EJ4V0UD 15 www..com 22.1 Standby Function and Configuration................................................................................... 543 22.1.1 22.1.2 Standby function.......................................................................................................................543 Registers controlling standby function......................................................................................543 HALT mode ..............................................................................................................................546 STOP mode .............................................................................................................................551 22.2 Standby Function Operation................................................................................................. 546 22.2.1 22.2.2 CHAPTER 23 RESET FUNCTION........................................................................................................ 557 23.1 Register for Confirming Reset Source................................................................................. 565 CHAPTER 24 POWER-ON-CLEAR CIRCUIT...................................................................................... 566 24.1 24.2 24.3 24.4 Functions of Power-on-Clear Circuit ................................................................................... 566 Configuration of Power-on-Clear Circuit ............................................................................. 567 Operation of Power-on-Clear Circuit.................................................................................... 567 Cautions for Power-on-Clear Circuit .................................................................................... 570 CHAPTER 25 LOW-VOLTAGE DETECTOR ....................................................................................... 572 25.1 25.2 25.3 25.4 Functions of Low-Voltage Detector...................................................................................... 572 Configuration of Low-Voltage Detector ............................................................................... 573 Registers Controlling Low-Voltage Detector ...................................................................... 573 Operation of Low-Voltage Detector...................................................................................... 576 25.4.1 25.4.2 When used as reset .................................................................................................................577 When used as interrupt ............................................................................................................582 25.5 Cautions for Low-Voltage Detector ...................................................................................... 587 CHAPTER 26 OPTION BYTE............................................................................................................... 590 26.1 26.2 Functions of Option Bytes .................................................................................................... 590 Format of Option Byte ........................................................................................................... 592 CHAPTER 27 FLASH MEMORY .......................................................................................................... 595 27.1 27.2 27.3 27.4 27.5 27.6 Internal Memory Size Switching Register............................................................................ 595 Internal Expansion RAM Size Switching Register .............................................................. 596 Writing with Flash memory programmer............................................................................. 597 Programming Environment................................................................................................... 600 Communication Mode............................................................................................................ 600 Connection of Pins on Board................................................................................................ 602 27.6.1 27.6.2 27.6.3 27.6.4 27.6.5 27.6.6 27.6.7 FLMD0 pin................................................................................................................................602 Serial interface pins..................................................................................................................602 RESET pin ...............................................................................................................................604 Port pins ...................................................................................................................................604 REGC pin .................................................................................................................................604 Other signal pins ......................................................................................................................605 Power supply............................................................................................................................605 Controlling flash memory..........................................................................................................606 Flash memory programming mode...........................................................................................606 User's Manual U17397EJ4V0UD 27.7 Programming Method ............................................................................................................ 606 27.7.1 27.7.2 16 www..com 27.7.3 27.7.4 Selecting communication mode ...............................................................................................607 Communication commands......................................................................................................608 27.8 Security Settings.................................................................................................................... 609 27.9 Processing Time for Each Command When PG-FP4 Is Used (Reference) ...................... 611 27.10 Flash Memory Programming by Self-Programming........................................................... 612 27.10.1 Boot swap function...................................................................................................................618 CHAPTER 28 ON-CHIP DEBUG FUNCTION (PD78F0547D ONLY) ............................................ 620 28.1 28.2 Connecting QB-78K0MINI to PD78F0547D........................................................................ 620 On-Chip Debug Security ID................................................................................................... 622 CHAPTER 29 INSTRUCTION SET ...................................................................................................... 623 29.1 Conventions Used in Operation List.................................................................................... 623 29.1.1 29.1.2 29.1.3 Operand identifiers and specification methods ........................................................................623 Description of operation column...............................................................................................624 Description of flag operation column ........................................................................................624 29.2 29.3 Operation List......................................................................................................................... 625 Instructions Listed by Addressing Type ............................................................................. 633 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)................................... 636 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS, TARGET) ................... 658 CHAPTER 32 PACKAGE DRAWINGS................................................................................................ 679 CHAPTER 33 RECOMMENDED SOLDERING CONDITIONS........................................................... 683 CHAPTER 34 CAUTIONS FOR WAIT ................................................................................................ 684 34.1 34.2 Cautions for Wait ................................................................................................................... 684 Peripheral Hardware That Generates Wait .......................................................................... 685 APPENDIX A DEVELOPMENT TOOLS .............................................................................................. 687 A.1 A.2 A.3 A.4 Software Package .................................................................................................................. 691 Language Processing Software ........................................................................................... 691 Control Software .................................................................................................................... 692 Flash Memory Programming Tools...................................................................................... 693 A.4.1 A.4.2 When using flash memory programmer FG-FP4, FL-PR4, PG-FPL3, and FP-LITE3 ..............693 When using on-chip debug emulator with programming function QB-MINI2............................693 When using in-circuit emulator QB-78K0KX2 ..........................................................................694 When using on-chip debug emulator QB-78K0MINI ................................................................694 When using on-chip debug emulator with programming function QB-MINI2............................695 A.5 Debugging Tools (Hardware)................................................................................................ 694 A.5.1 A.5.2 A.5.3 A.6 Debugging Tools (Software) ................................................................................................. 695 APPENDIX B NOTES ON TARGET SYSTEM DESIGN................................................................... 696 User's Manual U17397EJ4V0UD 17 www..com APPENDIX C REGISTER INDEX ......................................................................................................... 698 C.1 C.2 Register Index (In Alphabetical Order with Respect to Register Names) ........................ 698 Register Index (In Alphabetical Order with Respect to Register Symbol) ....................... 702 APPENDIX D LIST OF CAUTIONS ..................................................................................................... 706 APPENDIX E REVISION HISTORY...................................................................................................... 733 E.1 E.2 Major Revisions in This Edition............................................................................................ 733 Revision History of Preceding Editions............................................................................... 735 18 User's Manual U17397EJ4V0UD www..com CHAPTER 1 OUTLINE 1.1 Features Minimum instruction execution time can be changed from high speed (0.1 s: @ 20 MHz operation with highspeed system clock) to ultra low-speed (122 s: @ 32.768 kHz operation with subsystem clock) General-purpose register: 8 bits x 32 registers (8 bits x 8 registers x 4 banks) ROM, RAM capacities Item Part Number Program Memory (ROM) Flash memory Note Data Memory Internal High-Speed RAM 1 KB Note Internal Expansion RAM 1 KB 2 KB 4 KB 6 KB Note PD78F0544 PD78F0545 PD78F0546 PD78F0547, 78F0547D 48 KB 60 KB 96 KB 128 KB Note The internal flash memory, internal high-speed RAM capacities, and internal expansion RAM capacities can be changed using the internal memory size switching register (IMS) and the internal expansion RAM size switching register (IXS). For IMS and IXS, see 27.1 Memory Size Switching Register and 27.2 Internal Expansion RAM Size Switching Register. Buffer RAM: 32 bytes (can be used for transfer in CSI with automatic transmit/receive function) On-chip single-power-supply flash memory Self-programming (with boot swap function) On-chip debug function (PD78F0547D only)Note On-chip power-on-clear (POC) circuit and low-voltage detector (LVI) On-chip watchdog timer (operable with the on-chip internal low-speed oscillation clock) On-chip multiplier/divider (16 bits x 16 bits, 32 bits/16 bits) On-chip key interrupt function On-chip clock output/buzzer output controller I/O ports: 71 (N-ch open drain: 4) Timer: 8 channels * 16-bit timer/event counter: 2 channels * 8-bit timer/event counter: * 8-bit timer: * Watch timer: * Watchdog timer: 2 channels 2 channels 1 channel 1 channel Note The PD78F0547D has an on-chip debug function. Do not use this product for mass production because its reliability cannot be guaranteed after the on-chip debug function has been used, from the viewpoint of the restriction on the number of times the flash memory can be rewritten. NEC Electronics does not accept any complaint about this product. User's Manual U17397EJ4V0UD 19 CHAPTER 1 OUTLINE www..com Serial interface: 5 channels * UART (LIN (Local Interconnect Network)-bus supported: 1 channel * CSI/UARTNote: * CSI: * CSI with automatic transmit/receive function: * I2C: Power supply voltage: VDD = 1.8 to 5.5 V Operating ambient temperature: TA = -40 to +85C Note Select either of the functions of these alternate-function pins. 1 channel 1 channel 1 channel 1 channel 10-bit resolution A/D converter (AVREF = 2.3 to 5.5 V): 8 channels 1.2 Applications Automotive equipment ((A), (A1), (A2) grade products, under development) * System control for body electricals (power windows, keyless entry reception, etc.) * Sub-microcontrollers for control Car audio AV equipment, home audio PC peripheral equipment (keyboards, etc.) Household electrical appliances * Air conditioners * Microwave ovens, electric rice cookers Industrial equipment * Pumps * Vending machines * FA (Factory Automation) 20 User's Manual U17397EJ4V0UD CHAPTER 1 OUTLINE www..com 1.3 Ordering Information * Flash memory version Part Number Package 80-pin plastic LQFP (14 x 14) 80-pin plastic LQFP (fine pitch) (12 x 12) 80-pin plastic LQFP (14 x 14) 80-pin plastic LQFP (fine pitch) (12 x 12) 80-pin plastic LQFP (14 x 14) 80-pin plastic LQFP (fine pitch) (12 x 12) 80-pin plastic LQFP (14 x 14) 80-pin plastic LQFP (fine pitch) (12 x 12) 80-pin plastic LQFP (14 x 14) 80-pin plastic LQFP (fine pitch) (12 x 12) 80-pin plastic LQFP (14 x 14) 80-pin plastic LQFP (fine pitch) (12 x 12) 80-pin plastic LQFP (14 x 14) 80-pin plastic LQFP (fine pitch) (12 x 12) 80-pin plastic LQFP (14 x 14) 80-pin plastic LQFP (fine pitch) (12 x 12) 80-pin plastic LQFP (14 x 14) 80-pin plastic LQFP (fine pitch) (12 x 12) Quality Grade Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Special Special Special Special Special Special Special Special PD78F0544GC-UBT-A PD78F0544GK-8EU-A PD78F0545GC-UBT-A PD78F0545GK-8EU-A PD78F0546GC-UBT-A PD78F0546GK-8EU-A PD78F0547GC-UBT-A PD78F0547GK-8EU-A PD78F0547DGC-UBT-ANote1 PD78F0547DGK-8EU-ANote1 PD78F0544GC(A)-GAD-AX Note2 PD78F0544GK(A)-GAK-AX Note2 PD78F0545GC(A)-GAD-AX Note2 PD78F0545GK(A)-GAK-AX Note2 PD78F0546GC(A)-GAD-AX Note2 PD78F0546GK(A)-GAK-AX Note2 PD78F0547GC(A)-GAD-AX Note2 PD78F0547GK(A)-GAK-AX Note2 Notes 1. The PD78F0547D has an on-chip debug function. Do not use this product for mass production, because its reliability cannot be guaranteed after the on-chip debug function has been used, with respect to the number of times the flash memory can be rewritten. NEC Electronics does not accept complaints about this product. 2. Under development Remark Products with -A and -AX at the end of the part number are lead-free products. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. User's Manual U17397EJ4V0UD 21 CHAPTER 1 OUTLINE www..com 1.4 Pin Configuration (Top View) * 80-pin plastic LQFP (14 x 14) * 80-pin plastic LQFP (fine pitch) (12 x 12) P140/PCL/INTP6 P141/BUZ/BUSY0/INTP7 P142/SCKA0 P143/SIA0 P144/SOA0 P145/STB0 P00/TI000 P01/TI010/TO00 P02/SO11 P03/SI11 P04/SCK11 P130 ANI0/P20 ANI1/P21 ANI2/P22 ANI3/P23 ANI4/P24 ANI5/P25 ANI6/P26 ANI7/P27 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P120/INTP0/EXLVI P47 P46 P45 P44 P43 P42 P41 P40 RESET P124/XT2/EXCLKS P123/XT1 FLMD0 P122/X2/EXCLK/OCD0BNote P121/X1/OCD0ANote REGC VSS EVSS VDD EVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 AVSS AVREF P57 P56 P55 P54 P10/SCK10/TxD0 P11/SI10/RxD0 P12/SO10 P13/TxD6 P14/RxD6 P15/TOH0 P16/TOH1/INTP5 P17/TI50/TO50 P30/INTP1 P53 P52 P51 P50 P31/INTP2/OCD1ANote Note PD78F0547D (product with on-chip debug function) only Cautions 1. Make AVSS and EVSS the same potential as VSS. 2. Make EVDD the same potential as VDD. 3. Connect the REGC pin to VSS via a capacitor (0.47 to 1 F: recommended). 4. ANI0/P20 to ANI7/P27 are set in the analog input mode after release of reset. 22 P60/SCL0 P61/SDA0 P62/EXSCL0 P63 P33/TI51/TO51/INTP4 P64 P65 P66 P67 P77/KR7 P76/KR6 P75/KR5 P74/KR4 P73/KR3 P72/KR2 P71/KR1 P70/KR0 P06/TI011/TO01 P05/TI001/SSI11 P32/INTP3/OCD1BNote User's Manual U17397EJ4V0UD CHAPTER 1 OUTLINE www..com Pin Identification ANI0 to ANI7: AVREF: AVSS: BUSY0: BUZ: EVDD: EVSS: EXCLK: EXCLKS: EXLVI: EXSCL0: FLMD0: INTP0 to INTP7: KR0 to KR7: OCD0A, OCD0B, OCD1A, OCD1B: On chip debug input/output P00 to P06: P10 to P17: P20 to P27: P30 to P33: P40 to P47: P50 to P57: P60 to P67: P70 to P77: Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Analog input Analog reference voltage Analog ground Serial busy input Buzzer output Power supply for port Ground for port External clock input (main system clock) External clock input (subsystem clock) External potential input for low-voltage detector External serial clock input Flash programming mode External interrupt input Key return P120 to P124: P130: P140 to P145: PCL: REGC RESET: RxD0, RxD6: SCL0: SDA0: SI10, SI11, SIA0: SO10, SO11, SOA0: SSI11: STB0: TI000, TI010, TI001, TI011, TI50, TI51: TO00, TO01, TO50, TO51, TOH0, TOH1: TxD0, TxD6: VDD: VSS: X1, X2: XT1, XT2: Timer output Transmit data Power supply Ground Crystal oscillator (main system clock) Crystal oscillator (subsystem clock) Timer input Port 12 Port 13 Port 14 Programmable clock output Regulator capacitance Reset Receive data Serial clock input/output Serial data input/output Serial data input Serial data output Serial interface chip select input Serial strobe SCK10, SCK11, SCKA0: Serial clock input/output User's Manual U17397EJ4V0UD 23 CHAPTER 1 OUTLINE www..com 1.5 78K0/Kx2 Series Lineup ROM RAM 78K0/KB2 30 Pins 128 KB 7 KB - 44 Pins - 78K0/KC2 48 Pins - 78K0/KD2 52 Pins 78K0/KE2 64 Pins Note 78K0/KF2 80 Pins Note PD78F0527D PD78F0537D PD78F0547DNote PD78F0547 PD78F0546 PD78F0545 PD78F0544 - PD78F0527 96 KB 60 KB 5 KB 3 KB - - - - - PD78F0537 PD78F0536 PD78F0535 PD78F0534 PD78F0533 PD78F0532 PD78F0531 - PD78F0526 Note PD78F0515D PD78F0525 PD78F0524 PD78F0523 PD78F0522 PD78F0521 - PD78F0515 48 KB 32 KB 2 KB 1 KB - - Note PD78F0514 Note PD78F0503D PD78F0513D PD78F0513 PD78F0503 24 KB 1 KB PD78F0513 PD78F0512 PD78F0511 - - - - PD78F0502 PD78F0501 PD78F0500 16 KB 768 B 8 KB 512 B Note Product with on-chip debug function 24 User's Manual U17397EJ4V0UD CHAPTER 1 OUTLINE www..com The list of functions in the 78K0/Kx2 Series is shown below. (1/2) Part Number Item Flash memory (KB) RAM (KB) Bank (flash memory) Power supply voltage Regulator Minimum instruction execution time Main High-speed system Internal high-speed oscillation - 8 0.5 78K0/KB2 30/36 Pins 16 0.75 24 1 32 1 16 0.75 44 Pins 24 1 - VDD = 1.8 to 5.5 V Provided 0.1 s (20 MHz: VDD = 4.0 to 5.5 V)/0.2 s (10 MHz: VDD = 2.7 to 5.5 V)/ 0.4 s (5 MHz: VDD = 1.8 to 5.5 V) 20 MHz: VDD = 4.0 to 5.5 V/10 MHz: VDD = 2.7 to 5.5 V/5 MHz: VDD = 1.8 to 5.5 V 8 MHz (TYP.): VDD = 1.8 to 5.5 V 32.768 kHz (TYP.): VDD = 1.8 to 5.5 V 240 kHz (TYP.): VDD = 1.8 to 5.5 V 23 2 37 4 1 ch 2 ch 2 ch - 1 ch - - 1 ch 1 ch 1 ch 4 ch 6 14 - Provided 1.59 V 0.15 V (rise time to 1.8 V: 3.6 ms (MIN.)) The detection level of the supply voltage is selectable in 16 steps. Provided - - Clock output only Provided 7 16 4 ch 8 ch 8 1 ch 41 4 32 1 16 0.75 24 1 78K0/KC2 48 Pins 32 1 48 2 60 3 Clock Port Timer Serial interface Subsystem Internal low-speed oscillation Total N-ch O.D. (6 V tolerance) 16 bits (TM0) 8 bits (TM5) 8 bits (TMH) Watch WDT 3-wire CSI Automatic transmit/ receive 3-wire CSI UART/3-wire CSI Note UART supporting LINbus I C bus 2 10-bit A/D Interrupt Reset External Internal Key interrupt RESET pin POC LVI WDT Clock output/buzzer output Multiplier/divider On-chip debug function Operating ambient temperature PD78F0503D only PD78F0513D only -40 to +85C PD78F0515D only Note Select either of the functions of these alternate-function pins. User's Manual U17397EJ4V0UD 25 CHAPTER 1 OUTLINE www..com (2/2) Part Number Item Flash memory (KB) RAM (KB) Bank (flash memory) Power supply voltage Regulator Minimum instruction execution time Main High-speed system Internal high-speed oscillation 16 0.75 24 1 32 1 - 78K0/KD2 52 Pins 48 2 60 3 96 5 4 128 7 6 16 0.75 24 1 32 1 - VDD = 1.8 to 5.5 V Provided 0.1 s (20 MHz: VDD = 4.0 to 5.5 V)/0.2 s (10 MHz: VDD = 2.7 to 5.5 V)/ 0.4 s (5 MHz: VDD = 1.8 to 5.5 V) 20 MHz: VDD = 4.0 to 5.5 V/10 MHz: VDD = 2.7 to 5.5 V/5 MHz: VDD = 1.8 to 5.5 V 8 MHz (TYP.): VDD = 1.8 to 5.5 V 32.768 kHz (TYP.): VDD = 1.8 to 5.5 V 240 kHz (TYP.): VDD = 1.8 to 5.5 V 45 4 1 ch 2 ch 2 ch 1 ch 1 ch - - 1 ch 1 ch 1 ch 8 ch 8 16 8 ch Provided 1.59 V 0.15 V (rise time to 1.8 V: 3.6 ms (MIN.)) The detection level of the supply voltage is selectable in 16 steps. Provided Clock output only - Provided - Provided Provided 19 9 20 1 ch 1 ch 55 4 2 ch 71 4 78K0/KE2 64 Pins 48 2 60 3 96 5 4 128 7 6 48 2 - 78K0/KF2 80 Pins 60 3 96 5 4 128 7 6 Clock Port Timer Serial interface Subsystem Internal low-speed oscillation Total N-ch O.D. (6 V tolerance) 16 bits (TM0) 8 bits (TM5) 8 bits (TMH) Watch WDT 3-wire CSI Automatic transmit/ receive 3-wire CSI UART/3-wire CSI Note UART supporting LINbus I C bus 2 10-bit A/D Interrupt Reset External Internal Key interrupt RESET pin POC LVI WDT Clock output/buzzer output Multiplier/divider On-chip debug function Operating ambient temperature PD78F0527D only PD78F0537D only -40 to +85C PD78F0547D only Note Select either of the functions of these alternate-function pins. 26 User's Manual U17397EJ4V0UD CHAPTER 1 OUTLINE www..com 1.6 Block Diagram TO00/TI010/P01 TI000/P00 RxD6/P14 (LINSEL) TO01/TI011/P06 TI001/P05 16-bit timer/ event counter 00 Port 0 7 P00 to P06 16-bit timer/ event counter 01 Port 1 8 P10 to P17 Port 2 TOH0/P15 8-bit timer H0 Port 3 TOH1/P16 8-bit timer H1 8 P20 to P27 4 P30 to P33 Port 4 8 P40 to P47 Internal low-speed oscillator Port 5 8 P50 to P57 Port 6 Watchdog timer Port 7 TI50/TO50/P17 8-bit timer/ event counter 50 8 P60 to P67 8 P70 to P77 Port 12 5 P120 to P124 TI51/TO51/P33 8-bit timer/ event counter 51 78K/0 CPU core BANKNote 1 Flash memory Port 13 P130 Watch timer Port 14 6 P140 to P145 Buzzer output RxD0/P11 TxD0/P10 Serial interface UART0 Serial interface UART6 LINSEL Serial interface CSI10 Internal high-speed RAM Internal expansion RAM Clock output control Power on clear/ low voltage indicator Key return 8 BUZ/P141 PCL/P140 RxD6/P14 TxD6/P13 SI10/P11 SO10/P12 SCK10/P10 SI11/P03 SO11/P02 SCK11/P04 SSI11/P05 SIA0/P143 SOA0/P144 SCKA0/P142 STB0/P145 BUSY0/P141 EXSCL0/P62 SDA0/P61 SCL0/P60 ANI0/P20 to ANI7/P27 AVREF AVSS RxD6/P14 (LINSEL) INTP0/P120 INTP1/P30 to INTP4/P33 INTP5/P16 INTP6/P140, INTP7/P141 2 4 8 POC/LVI control KR0/P70 to KR7/P77 EXLVI/P120 Serial interface CSI11 Reset control Multiplier & divider On-chip debugNote 2 OCD0ANote 2/X1, OCD1ANote 2/P31 OCD0BNote 2/X2, OCD1BNote 2/P32 RESET X1/P121 X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124 Serial interface CSIA0 Serial interface IIC0 System control Internal high-speed oscillator A/D converter VDD, VSS, FLMD0 EVDD EVSS Voltage regulator REGC Interrupt control Notes 1. 2. Available only in the PD78F0546, 78F0547, and 78F0547D. Available only in the PD78F0547D. User's Manual U17397EJ4V0UD 27 CHAPTER 1 OUTLINE www..com 1.7 Outline of Functions (1/2) Item Internal memory Flash memory (self-programming Note 1 supported) Memory bank Note 2 PD78F0544 48 KB PD78F0545 60 KB PD78F0546 96 KB PD78F0547 128 KB PD78F0547D - 1 KB 1 KB 32 bytes 64 KB 2 KB - 4 banks 6 banks High-speed RAM Expansion RAM Buffer RAM Memory space Note 1 Note 1 4 KB 6 KB Main system High-speed system clock clock (oscillation frequency) Internal high-speed oscillation clock Subsystem clock (oscillation frequency) Internal low-speed oscillation clock (for TMH1, WDT) General-purpose registers X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) 1 to 20 MHz: VDD = 4.0 to 5.5 V, 1 to 10 MHz: VDD = 2.7 to 5.5 V, 1 to 5 MHz: VDD = 1.8 to 5.5 V Internal oscillation 8 MHz (TYP.): VDD = 1.8 to 5.5 V XT1 (crystal) oscillation, external subsystem clock input (EXCLKS) 32.768 kHz (TYP.): VDD = 1.8 to 5.5 V Internal oscillation 240 kHz (TYP.): VDD = 1.8 to 5.5 V 8 bits x 32 registers (8 bits x 8 registers x 4 banks) 0.25 s (internal high-speed oscillation clock: @ fRH = 8 MHz (TYP.) operation) 122 s (subsystem clock: @ fSUB = 32.768 kHz operation) Minimum instruction execution time 0.1 s (high-speed system clock: @ fXH = 20 MHz operation) Instruction set * * * * 8-bit operation, 16-bit operation Multiply/divide (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulate (set, reset, test, and Boolean operation) BCD adjust, etc. 71 66 1 4 2 channels 2 channels 2 channels 1 channel 1 channel I/O ports Total: CMOS I/O: CMOS output: N-ch open-drain I/O (6 V tolerance): Timers * * * * * Timer outputs 16-bit timer/event counter: 8-bit timer/event counter: 8-bit timer: Watch timer: Watchdog timer: 6 (PWM output: 4, PPG output: 2) * 156.25 kHz, 312.5 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (peripheral hardware clock: @ fPRS = 20 MHz operation) * 32.768 kHz (subsystem clock: @ fSUB = 32.768 kHz operation) 2.44 kHz, 4.88 kHz, 9.77 kHz, 19.54 kHz (peripheral hardware clock: @ fPRS = 20 MHz operation) 10-bit resolution x 8 channels (AVREF = 2.3 to 5.5 V)) Clock output Buzzer output A/D converter Notes 1. The internal flash memory capacity, internal high-speed RAM capacity, and internal expansion RAM capacity can be changed using the internal memory size switching register (IMS) and the internal expansion RAM size switching register (IXS). 2. Memory banks to be used can be changed using the memory bank select register (BANK). 28 User's Manual U17397EJ4V0UD CHAPTER 1 OUTLINE www..com (2/2) Item Serial interface * * * * * PD78F0544 PD78F0545 PD78F0546 PD78F0547 1 channel 1 channel 1 channel 1 channel 1 channel PD78F0547D UART supporting LIN-bus: Note 3-wire serial I/O/UART : 3-wire serial I/O: 3-wire serial I/O with automatic transmit/receive function: 2 I C bus: Multiplier/divider Vectored Internal interrupt sources External Key interrupt Reset * 16 bits x 16 bits = 32 bits (multiplication) * 32 bits / 16 bits = 32 bits remainder of 16 bits (division) 20 9 Key interrupt (INTKR) occurs by detecting falling edge of key input pins (KR0 to KR7). * * * * Reset using RESET pin Internal reset by watchdog timer Internal reset by power-on-clear Internal reset by low-voltage detector Provided On-chip debug function Power supply voltage Operating ambient temperature Package None VDD = 1.8 to 5.5 V TA = -40 to +85C * 80-pin plastic LQFP (14 x 14) * 80-pin plastic LQFP (fine pitch) (12 x 12) Note Select either of the functions of these alternate-function pins. An outline of the timer is shown below. 16-Bit Timer/ Event Counters 00 and 01 TM00 Function Interval timer External event counter PPG output PWM output Pulse width measurement Square-wave output Carrier generator Timer output Watchdog timer Interrupt source 1 channel 1 channel 1 output - 2 inputs 1 output - - - 2 TM01 1 channel 1 channel 1 output - 2 inputs 1 output - - - 2 8-Bit Timer/ Event Counters 50 and 51 TM50 1 channel 1 channel - 1 output - 1 output - - - 1 TM51 1 channel 1 channel - 1 output - 1 output - - - 1 8-Bit Timers H0 and H1 Watch Timer Watchdog Timer TMH0 1 channel - - 1 output - 1 output - - - 1 TMH1 1 channel - - 1 output - 1 output 1 output - - 1 Nore 2 1 channel - - - - - - 1 channel - 1 Note 1 - - - - - - - Nore 1 - 1 channel - Notes 1. 2. In the watch timer, the watch timer function and interval timer function can be used simultaneously. TM51 and TMH1 can be used in combination as a carrier generator mode. User's Manual U17397EJ4V0UD 29 www..com CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List There are three types of pin I/O buffer power supplies: AVREF, EVDD, and VDD. The relationship between these power supplies and the pins is shown below. Table 2-1. Pin I/O Buffer Power Supplies Power Supply AVREF EVDD VDD P20 to P27 Port pins other than P20 to P27 and P121 to P124 * P121 to P124 * Pins other than port Corresponding Pins (1) Port functions (1/2) Function Name P00 P01 P02 P03 P04 P05 P06 P10 P11 P12 P13 P14 P15 P16 P17 P20 to P27 I/O Port 2. 8-bit I/O port. Input/output can be specified in 1-bit units. P30 P31 P32 P33 I/O Port 3. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input port INTP1 INTP2/OCD1A INTP3/OCD1B Note I/O I/O Port 0. 7-bit I/O port. Function After Reset Input port Alternate Function TI000 TI010/TO00 SO11 SI11 SCK11 TI001/SSI11 TI011/TO01 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. I/O Port 1. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input port SCK10/TxD0 SI10/RxD0 SO10 TxD6 RxD6 TOH0 TOH1/INTP5 TI50/TO50 Analog input ANI0 to ANI7 Note TI51/TO51/INTP4 Note PD78F0547D only 30 User's Manual U17397EJ4V0UD CHAPTER 2 PIN FUNCTIONS www..com (1) Port functions (2/2) Function Name P40 to P47 I/O I/O Port 4. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P50 to P57 I/O Port 5. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P60 P61 P62 P63 to P67 P70 to P77 I/O I/O Port 6. 8-bit I/O port. Output of P60 to P63 is N-ch open-drain output (6 V tolerance). Input/output can be specified in 1-bit units. Only for P64 to P67, use of an on-chip pull-up resistor can be specified by a software setting. Port 7. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P120 P121 P122 P123 P124 P130 Output Port 13. 1-bit output-only port. P140 P141 P142 P143 P144 P145 I/O Port 14. 6-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input port PCL/INTP6 BUZ/BUSY0/INTP7 SCKA0 SIA0 SOA0 STB0 Output port I/O Port 12. 5-bit I/O port. Input/output can be specified in 1-bit units. Only for P120, use of an on-chip pull-up resistor can be specified by a software setting. Input port INTP0/EXLVI X1/OCD0A Note Function After Reset Input port Alternate Function - Input port - Input port SCL0 SDA0 EXSCL0 - Input port KR0 to KR7 X2/EXCLK/OCD0B XT1 XT2/EXCLKS - Note Note PD78F0547D only User's Manual U17397EJ4V0UD 31 CHAPTER 2 PIN FUNCTIONS www..com (2) Non-port functions (1/2) Function Name ANI0 to ANI7 I/O Input Function A/D converter analog input After Reset Analog input BUSY0 BUZ EXLVI EXSCL0 Input Output Input Input - Input CSIA0 busy input Buzzer output Potential input for external low-voltage detection External clock input for I C. To input an external clock, input a clock of 6.4 MHz. FLMD0 INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTP7 KR0 to KR7 PCL Input Output - Key interrupt input Clock output (for trimming of high-speed system clock, subsystem clock) REGC Connecting regulator output (2.5 V) stabilization capacitance for internal operation. Connect to VSS via a capacitor (0.47 to 1 F: recommended). RESET RxD0 RxD6 SCK10 SCK11 SCKA0 SCL0 SDA0 SI10 SI11 SIA0 SO10 SO11 SOA0 SSI11 STB0 Output Input Output Serial data output from CSIA0 Chip select input to CSI11 Strobe output from CSIA0 Input port Input port Input port Input Output Serial data input to CSIA0 Serial data output from CSI10, CSI11 Input port Input port I/O I/O I/O Input Clock input/output for CSIA0 Clock input/output for I C Serial data I/O for I C Serial data input to CSI10, CSI11 2 2 2 Alternate Function P20 to P27 Input port Input port Input port Input port - Input port P141/BUZ/INTP7 P141/BUSY0/INTP7 P120/INTP0 P62 - P120/EXLVI P30 P31/OCD1A P32/OCD1B Note Flash memory programming mode setting External interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified Note P33/TI51/TO51 P16/TOH1 P140/PCL P141/BUZ/BUSY0 Input port Input port - P70 to P77 P140/INTP6 - Input Input Input I/O System reset input Serial data input to UART0 Serial data input to UART6 Clock input/output for CSI10, CSI11 - Input port Input port Input port P11/SI10 P14 P10/TxD0 P04 Input port Input port Input port Input port P142 P60 P61 P11/RxD0 P03 P143 P12 P02 P144 P05/TI001 P145 - Note PD78F0547D only 32 User's Manual U17397EJ4V0UD CHAPTER 2 PIN FUNCTIONS www..com (2) Non-port functions (2/2) Function Name TI000 I/O Input Function External count clock input to 16-bit timer/event counter 00 Capture trigger input to capture registers (CR000, CR010) of 16-bit timer/event counter 00 TI001 External count clock input to 16-bit timer/event counter 01 Capture trigger input to capture registers (CR001, CR011) of 16-bit timer/event counter 01 TI010 Input Capture trigger input to capture register (CR000) of 16-bit timer/event counter 00 TI011 Capture trigger input to capture register (CR001) of 16-bit timer/event counter 01 TI50 TI51 TO00 TO01 TO50 TO51 TOH0 TOH1 TxD0 TxD6 X1 X2 EXCLK XT1 XT2 EXCLKS VDD EVDD Output Output - - Input - - Input - - - - - - Note After Reset Input port Alternate Function P00 P05/SSI11 Input port P01/TO00 P06/TO01 Input External count clock input to 8-bit timer/event counter 50 External count clock input to 8-bit timer/event counter 51 Input port P17/TO50 P33/TO51/INTP4 Output 16-bit timer/event counter 00 output 16-bit timer/event counter 01 output Input port P01/TI010 P06/TI011 Output 8-bit timer/event counter 50 output 8-bit timer/event counter 51 output Input port P17/TI50 P33/TI51/INTP4 Output 8-bit timer H0 output 8-bit timer H1 output Serial data output from UART0 Serial data output from UART6 Connecting resonator for main system clock Input port P15 P16/INTP5 Input port Input port Input port Input port P10/SCK10 P13 P121/OCD0A Note P122/EXCLK/OCD0B P122/X2/OCD0B P123 P124/EXCLKS P124/XT2 - - - - - - P121/X1 P31/INTP2 P122/X2/EXCLK P32/INTP3 Note Note External clock input for main system clock Connecting resonator for subsystem clock Input port Input port Input port External clock input for subsystem clock Positive power supply for P121 to P124 and other than ports Positive power supply for ports other than P20 to P27 and P121 to P124. Make EVDD the same potential as VDD. Input port - - - - - - Input port AVREF A/D converter reference voltage input and positive power supply for P20 to P27 and A/D converter VSS EVSS Ground potential for P121 to P124 and other than ports Ground potential for ports other than P20 to P27 and P121 to P124. Make EVSS the same potential as VSS. AVSS A/D converter ground potential. Make the same potential as VSS. OCD0A OCD1A OCD0B OCD1B Input Connection for on-chip debug mode setting pins (PD78F0547D only) Note Note - Note Note PD78F0547D only User's Manual U17397EJ4V0UD 33 CHAPTER 2 PIN FUNCTIONS www..com 2.2 Description of Pin Functions 2.2.1 P00 to P06 (port 0) P00 to P06 function as a 7-bit I/O port. These pins also function as timer I/O, serial interface data I/O, clock I/O, and chip select input. The following operation modes can be specified in 1-bit units. (1) Port mode P00 to P06 function as a 7-bit I/O port. P00 to P06 can be set to input or output port in 1-bit units using port mode register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0). (2) Control mode P00 to P06 function as timer I/O, serial interface data I/O, clock I/O, and chip select input. (a) TI000, TI001 These are the pins for inputting an external count clock to 16-bit timer/event counters 00 and 01 and are also for inputting a capture trigger signal to the capture registers (CR000, CR010 or CR001, CR011) of 16-bit timer/event counters 00 and 01. (b) TI010, TI011 These are the pins for inputting a capture trigger signal to the capture register (CR000 or CR001) of 16-bit timer/event counters 00 and 01. (c) TO00, TO01 These are timer output pins of 16-bit timer/event counters 00 and 01. (d) SI11 This is a serial data input pin of serial interface CSI11. (e) SO11 This is a serial data output pin of serial interface CSI11. (f) SCK11 This is a serial clock I/O pin of serial interface CSI11. (g) SSI11 This is a chip select input pin of serial interface CSI11. 34 User's Manual U17397EJ4V0UD CHAPTER 2 PIN FUNCTIONS www..com 2.2.2 P10 to P17 (port 1) P10 to P17 function as an 8-bit I/O port. These pins also function as pins for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P10 to P17 function as an 8-bit I/O port. P10 to P17 can be set to input or output port in 1-bit units using port mode register 1 (PM1). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1). (2) Control mode P10 to P17 function as external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. (a) SI10 This is a serial data input pin of serial interface CSI10. (b) SO10 This is a serial data output pin of serial interface CSI10. (c) SCK10 This is a serial clock I/O pin of serial interface CSI10. (d) RxD0 This is a serial data input pin of serial interface UART0. (e) RxD6 This is a serial data input pin of serial interface UART6. (f) TxD0 This is a serial data output pin of serial interface UART0. (g) TxD6 This is a serial data output pin of serial interface UART6. (h) TI50 This is the pin for inputting an external count clock to 8-bit timer/event counter 50. (i) TO50 This is a timer output pin of 8-it timer/event counter 50. (j) TOH0, TOH1 These are the timer output pins of 8-bit timers H0 and H1. (k) INTP5 This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. User's Manual U17397EJ4V0UD 35 CHAPTER 2 PIN FUNCTIONS www..com 2.2.3 P20 to P27 (port 2) P20 to P27 function as an 8-bit I/O port. These pins also function as pins for A/D converter analog input. The following operation modes can be specified in 1-bit units. (1) Port mode P20 to P27 function as an 8-bit I/O port. P20 to P27 can be set to input or output port in 1-bit units using port mode register 2 (PM2). (2) Control mode P20 to P27 function as A/D converter analog input pins (ANI0 to ANI7). When using these pins as analog input pins, see (5) ANI0/P20 to ANI7/P27 in 13.6 Cautions for A/D Converter. Caution ANI0/P20 to ANI7/P27 are set in the analog input mode after release of reset. 2.2.4 P30 to P33 (port 3) P30 to P33 function as a 4-bit I/O port. These pins also function as pins for external interrupt request input and timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P30 to P33 function as a 4-bit I/O port. P30 to P33 can be set to input or output port in 1-bit units using port mode register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3). (2) Control mode P30 to P33 function as external interrupt request input and timer I/O. (a) INTP1 to INTP4 These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) TI51 This is an external count clock input pin to 8-bit timer/event counter 51. (c) TO51 This is a timer output pin from 8-bit timer/event counter 51. Cautions 1. In the product with an on-chip debug function (PD78F0547D), be sure to pull the P31/INTP2/OCD1ANote pin down before a reset release, to prevent malfunction. 2. For products without an on-chip debug function (other than the PD78F0547D) and having a product rank of "I", "K", or "E", and for the product with an on-chip debug function (PD78F0547D), connect P31/INTP2/OCD1ANote as follows when writing the flash memory with a flash memory programmer. * P31/INTP2/OCD1ANote: Connect to EVSS via a resistor (10 k: recommended). The above connection is not necessary when writing the flash memory by means of self programming. Note OCD1A is provided to the PD78F0547D only. 36 User's Manual U17397EJ4V0UD CHAPTER 2 PIN FUNCTIONS www..com Remarks 1. For the product ranks, consult an NEC Electronics sales representative. 2. Only for the PD78F0547D, P31 and P32 can be used as on-chip debug mode setting pins (OCD1A, OCD1B) when the on-chip debug function is used. For how to connect an in-circuit emulator supporting on-chip debugging (QB-78K0MINI), see CHAPTER 28 ON-CHIP DEBUG FUNCTION (PD78F0547D ONLY). 2.2.5 P40 to P47 (port 4) P40 to P47 function as an 8-bit I/O port. P40 to P47 can be set to input or output port in 1-bit units using port mode register 4 (PM4). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4 (PU4). 2.2.6 P50 to P57 (port 5) P50 to P57 function as an 8-bit I/O port. P50 to P57 can be set to input or output port in 1-bit units using port mode register 5 (PM5). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 5 (PU5). 2.2.7 P60 to P67 (port 6) P60 to P67 function as an 8-bit I/O port. These pins also function as pins for serial interface data I/O, clock I/O, and external clock input. The following operation modes can be specified in 1-bit units. (1) Port mode P60 to P67 function as an 8-bit I/O port. P60 to P67 can be set to input port or output port in 1-bit units using port mode register 6 (PM6). Only for P64 to P67, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 6 (PU6). Output of P60 to P63 is N-ch open-drain output (6 V tolerance). (2) Control mode P60 to P67 function as serial interface data I/O, clock I/O, and external clock input. (a) SDA0 This is a serial data I/O pin for serial interface IIC0. (b) SCL0 This is a serial clock I/O pin for serial interface IIC0. (c) EXSCL0 This is an external clock input pin to serial interface IIC0. To input an external clock, input a clock of 6.4 MHz. User's Manual U17397EJ4V0UD 37 CHAPTER 2 PIN FUNCTIONS www..com 2.2.8 P70 to P77 (port 7) P70 to P77 function as an 8-bit I/O port. These pins also function as key interrupt input pins. The following operation modes can be specified in 1-bit units. (1) Port mode P70 to P77 function as an 8-bit I/O port. P70 to P77 can be set to input or output port in 1-bit units using port mode register 7 (PM7). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (PU7). (2) Control mode P70 to P77 function as key interrupt input pins. (a) KR0 to KR7 These are the key interrupt input pins 2.2.9 P120 to P124 (port 12) P120 to P124 function as a 5-bit I/O port. These pins also function as pins for external interrupt request input, potential input for external low-voltage detection, connecting resonator for main system clock, connecting resonator for subsystem clock, external clock input for main system clock, and external clock input for subsystem clock. The following operation modes can be specified in 1-bit units. (1) Port mode P120 to P124 function as a 5-bit I/O port. P120 to P124 can be set to input or output port using port mode register 12 (PM12). Only for P120, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12). (2) Control mode P120 to P124 function as pins for external interrupt request input, potential input for external low-voltage detection, connecting resonator for main system clock, connecting resonator for subsystem clock, external clock input for main system clock, and external clock input for subsystem clock. (a) INTP0 This functions as an external interrupt request input (INTP0) for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) EXLVI This is a potential input pin for external low-voltage detection. (c) X1, X2 These are the pins for connecting a resonator for main system clock. (d) EXCLK This is an external clock input pin for main system clock. (e) XT1, XT2 These are the pins for connecting a resonator for subsystem clock. 38 User's Manual U17397EJ4V0UD CHAPTER 2 PIN FUNCTIONS www..com (f) EXCLKS This is an external clock input pin for subsystem clock. Caution For products without an on-chip debug function (other than the PD78F0547D) and having a product rank of "I", "K", or "E", and for the product with an on-chip debug function (PD78F0547D), connect P121/X1/OCD0ANote as follows when writing the flash memory with a flash memory programmer. * P121/X1/OCD0ANote: When using this pin as a port, connect it to VSS via a resistor (10 k: recommended) (in the input mode) or leave it open (in the output mode). The above connection is not necessary when writing the flash memory by means of self programming. Note OCD0A is provided to the PD78F0547D only. Remarks 1. For the product ranks, consult an NEC Electronics sales representative. 2. Only for the PD78F0547D, X1 and X2 can be used as on-chip debug mode setting pins (OCD0A, OCD0B) when the on-chip debug function is used. For how to connect an in-circuit emulator supporting on-chip debugging (QB-78K0MINI), see CHAPTER 28 ON-CHIP DEBUG FUNCTION (PD78F0547D ONLY). 2.2.10 P130 (port 13) P130 functions as a 1-bit output-only port. Remark When the device is reset, P130 outputs a low level. Therefore, to output a high level from P130 before the device is reset, the output signal of P130 can be used as a pseudo reset signal of the CPU (see the figure for Remark in 5.2.10 Port 13). 2.2.11 P140 to P145 (port 14) P140 to P145 function as a 6-bit I/O port. These pins also function as external interrupt request input, clock output, buzzer output, serial interface data I/O, clock I/O, busy input, and strobe output pins. The following operation modes can be specified in 1-bit units. (1) Port mode P140 to P145 function as a 6-bit I/O port. P140 to P145 can be set to input or output port in 1-bit units using port mode register 14 (PM14). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14 (PU14). (2) Control mode P140 to P145 function as external interrupt request input, clock output, buzzer output, serial interface data I/O, clock I/O, busy input, and strobe output pins. (a) INTP6, INTP7 These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) PCL This is a clock output pin. User's Manual U17397EJ4V0UD 39 CHAPTER 2 PIN FUNCTIONS www..com (c) BUZ This is a buzzer output pin. (d) BUSY0 This is a serial interface CSIA0 busy input pin. (e) SIA0 This is a serial interface CSIA0 serial data input pin. (f) SOA0 This is a serial interface CSIA0 serial data output pin. (g) SCKA0 This is a serial interface CSIA0 serial clock I/O pin. (h) STB0 This is a serial interface CSIA0 strobe output pin. 2.2.12 AVREF This is the A/D converter reference voltage input pin and the positive power supply pin of P20 to P27 and A/D converter. When the A/D converter is not used, connect this pin directly to EVDD or VDDNote. Note Make the AVREF pin the same potential as the VDD pin when port 2 is used as a digital port. 2.2.13 AVSS This is the A/D converter ground potential pin. Even when the A/D converter is not used, always use this pin with the same potential as the VSS pin. 2.2.14 RESET This is the active-low system reset input pin. 2.2.15 REGC This is the pin for connecting regulator output (2.5 V) stabilization capacitance for internal operation. Connect this pin to VSS via a capacitor (0.47 to 1 F: recommended). REGC VSS Caution Keep the wiring length as short as possible for the broken-line part in the above figure. 40 User's Manual U17397EJ4V0UD CHAPTER 2 PIN FUNCTIONS www..com 2.2.16 VDD and EVDD VDD is the positive power supply pin for P121 to P124 and other than ports. EVDD is the positive power supply pin for ports other than P20 to P27 and P121 to P124. Always make EVDD the same potential as VDD. 2.2.17 VSS and EVSS VSS is the ground potential pin for P121 to P124 and other than ports. EVSS is the ground potential pin for ports other than P20 to P27 and P121 to P124. Always make EVSS the same potential as VSS. 2.2.18 FLMD0 This is a pin for setting flash memory programming mode. Connect FLMD0 to EVSS or VSS in the normal operation mode. In flash memory programming mode, connect this pin to the flash memory programmer. User's Manual U17397EJ4V0UD 41 CHAPTER 2 PIN FUNCTIONS www..com 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-2 shows the types of pin I/O circuits and the recommended connections of unused pins. See Figure 2-1 for the configuration of the I/O circuit of each type. Table 2-2. Pin I/O Circuit Types (1/2) Pin Name P00/TI000 P01/TI010/TO00 P02/SO11 P03/SI11 P04/SCK11 P05/TI001/SSI11 P06/TI011/TO01 P10/SCK10/TxD0 P11/SI10/RxD0 P12/SO10 P13/TxD6 P14/RxD6 P15/TOH0 P16/TOH1/INTP5 P17/TI50/TO50 ANI0/P20 to ANI7/P27 Note 1 I/O Circuit Type 5-AH I/O I/O Input: Recommended Connection of Unused Pins Independently connect to EVDD or EVSS via a resistor. Output: Leave open. 5-AG 5-AH 5-AG 5-AH 5-AG 5-AH 11-G Input P30/INTP1 P31/INTP2/OCD1A P32/INTP3/OCD1B Notes 2, 3 5-AH I/O Input: Output: Leave open. Note 3 P33/TI51/TO51/INTP4 P40 to P47 P50 to P57 P60/SCL0 P61/SDA0 P62/EXSCL0 P63 13-P 13-AD Input: Connect to EVSS. the output latch of the port to 0. Output: Leave this pin open at low-level output after clearing 5-AG Notes 1. ANI0/P20 to ANI7/P27 are set in the analog input mode after release of reset. 2. For products without an on-chip debug function (other than the PD78F0547D) and having a product rank of "I", "K", or "E", and for the product with an on-chip debug function (PD78F0547D), connect P31/INTP2/OCD1ANote 3 as follows when writing the flash memory with a flash memory programmer. * P31/INTP2/OCD1ANote 3: Connect to EVSS via a resistor (10 k: recommended). The above connection is not necessary when writing the flash memory by means of self programming. 3. OCD1A and OCD1B are provided to the PD78F0547D only. Remark For the product ranks, consult an NEC Electronics sales representative. 42 User's Manual U17397EJ4V0UD CHAPTER 2 PIN FUNCTIONS www..com Table 2-2. Pin I/O Circuit Types (2/2) Pin Name P64 to P67 P70/KR0 to P77/KR7 P120/INTP0/EXLVI P121/X1/OCD0A Notes 1, 5 Notes 1, 2, 5 I/O Circuit Type 5-AG 5-AH I/O I/O Input: Recommended Connection of Unused Pins Independently connect to EVDD or EVSS via a resistor. Output: Leave open. 37 Input: Independently connect to VDD or VSS via a resistor. P122/X2/EXCLK/ OCD0B Note 1 Output: Leave open. P123/XT1 P124/XT2/EXCLKS P130 P140/PCL/INTP6 Note 1 3-C 5-AH Output I/O Leave open. Input: Independently connect to EVDD or EVSS via a resistor. P141/BUZ/BUSY0/INTP7 P142/SCKA0 P143/SIA0 P144/SOA0 P145/STB0 AVREF AVSS FLMD0 RESET 38 2 - - - - - Input 5-AG Output: Leave open. Connect directly to EVDD or VDD Note 3 . Connect directly to EVSS or VSS. Connect to EVSS or VSS Note 4 . Connect directly to VDD or via a resistor. Notes 1. Use recommended connection above in I/O port mode (see Figure 6-2 Format of Clock Operation Mode Select Register (OSCCTL)) when these pins are not used. 2. For products without an on-chip debug function (other than the PD78F0547D) and having a product rank of "I", "K", or "E", and for the product with an on-chip debug function (PD78F0547D), connect P121/X1/OCD0ANote 5 as follows when writing the flash memory with a flash memory programmer. * P121/X1/OCD0ANote 5: When using this pin as a port, connect it to VSS via a resistor (10 k: recommended) (in the input mode) or leave it open (in the output mode). The above connection is not necessary when writing the flash memory by means of self programming. 3. Make the same potential as the VDD pin when port 2 is used as a digital port. 4. FLMD0 is a pin that is used to write data to the flash memory. To rewrite the data of the flash memory on-board, connect this pin to EVSS or VSS via a resistor (10 k: recommended). The same applies when executing on-chip debugging with a product with an on-chip debug function (PD78F0547D). 5. OCD0A and OCD0B are provided to the PD78F0547D only. Remark For the product ranks, consult an NEC Electronics sales representative. User's Manual U17397EJ4V0UD 43 CHAPTER 2 PIN FUNCTIONS www..com Figure 2-1. Pin I/O Circuit List (1/2) Type 2 Type 5-AH EVDD Pull-up enable P-ch IN Data EVDD P-ch IN/OUT Schmitt-triggered input with hysteresis characteristics Output disable N-ch EVSS Input enable Type 3-C Type 11-G AVREF Data P-ch EVDD IN/OUT P-ch Output disable N-ch Data OUT P-ch Comparator + AVSS N-ch _ N-ch Series resistor string voltage EVSS AVSS Input enable Type 5-AG EVDD Type 13-P Pull-up enable P-ch Data EVDD Data IN/OUT N-ch Output disable P-ch EVSS IN/OUT Output disable N-ch Input enable EVSS Input enable 44 User's Manual U17397EJ4V0UD CHAPTER 2 PIN FUNCTIONS www..com Figure 2-1. Pin I/O Circuit List (2/2) Type 13-AD Data Output disable N-ch IN/OUT Type 38 IN EVSS Input enable Input enable Type 37 VDD Data P-ch X2, XT2 Output disable RESET N-ch VSS Input enable VDD Data P-ch P-ch X1, XT1 N-ch Output disable RESET N-ch VSS Input enable User's Manual U17397EJ4V0UD 45 www..com CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Products in the 78K0/KF2 can access a 64 KB memory space. Figures 3-1 to 3-5 show the memory maps. Cautions 1. Regardless of the internal memory capacity, the initial values of the internal memory size switching register (IMS) and internal expansion RAM size switching register (IXS) of all products in the 78K0/KF2 are fixed (IMS = CFH, IXS = 0CH). corresponding to each product as indicated below. 2. To set the memory size, set IMS and then IXS. Set the memory size so that the internal ROM and internal expansion RAM areas do not overlap. Table 3-1. Set Values of Internal Memory Size Switching Register (IMS) and Internal Expansion RAM Size Switching Register (IXS) Flash Memory Version (78K0/KF2) IMS IXS ROM Capacity Internal High-Speed RAM Capacity CCH CFH CCH Note1 Note2 Therefore, set the value Internal Expansion RAM Capacity 1 KB 2 KB 4 KB 6 KB PD78F0544 PD78F0545 PD78F0546 PD78F0547, 78F0547D 0AH 08H 04H 00H 48 KB 60 KB 96 KB Note2 1 KB CCH Note2 128 KB Note2 Notes 1. The ROM and RAM capacities of the products with the on-chip debug function can be debugged according to the debug target products. Set IMS and IXS according to the debug target products. 2. The PD78F0546, 78F0547, and 78F0547D have internal ROMs of 96 KB and 128 KB, respectively. However, the set value of IMS of these devices is the same as those of the 48 KB product because memory banks are used. For how to set the memory banks, see 4.2 Memory Bank Select Register (BANK). 46 User's Manual U17397EJ4V0UD CHAPTER 3 CPU ARCHITECTURE www..com Figure 3-1. Memory Map (PD78F0544) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH FB00H FAFFH FA20H FA1FH Data memory space General-purpose registers 32 x 8 bits Internal high-speed RAM 1024 x 8 bits Reserved Buffer RAM 32 x 8 bits FA00H F9FFH F800H F7FFH Reserved 1000H 0FFFH CALLF entry area 2048 x 8 bits 0800H 07FFH Program area 1915 x 8 bits 0085H 0084H 0080H 007FH Option byte areaNote 1 5 x 8 bits CALLT table area 64 x 8 bits Boot cluster 0Note 2 1085H 1084H 1080H 107FH BFFFH Program area 1FFFH Option byte areaNote 1 5 x 8 bits Boot cluster 1 Program area Program RAM area RAM space in which instruction can be fetched F400H F3FFH Reserved C000H BFFFH Program memory space 0000H Flash memory 49152 x 8 bits 0040H 003FH Internal expansion RAM 1024 x 8 bits Vector table area 64 x 8 bits 0000H Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H. When boot swap is used: Setting). Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see Table 3-2 Correspondence Between Address Values and Block Numbers in Flash Memory. BFFFH BC00H BBFFH Block 2FH Set the option bytes to 0080H to 0084H and 1080H to 1084H. Security 2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 07FFH 0400H 03FFH 0000H Block 01H Block 00H 1 KB User's Manual U17397EJ4V0UD 47 CHAPTER 3 CPU ARCHITECTURE www..com Figure 3-2. Memory Map (PD78F0545) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH FB00H FAFFH FA20H FA1FH General-purpose registers 32 x 8 bits Internal high-speed RAM 1024 x 8 bits Reserved Buffer RAM 32 x 8 bits Data memory space FA00H F9FFH F800H F7FFH Reserved 1000H 0FFFH CALLF entry area 2048 x 8 bits Internal expansion RAM 2048 x 8 bits 0800H 07FFH Program area 1915 x 8 bits 0085H 0084H 0080H 007FH Flash memory 61440 x 8 bits Option byte areaNote 1 5 x 8 bits CALLT table area 64 x 8 bits Boot cluster 0Note 2 1085H 1084H 1080H 107FH EFFFH Program area 1FFFH Option byte areaNote 1 5 x 8 bits Boot cluster 1 Program area Program RAM area RAM space in which instruction can be fetched F000H EFFFH Program memory space 0040H 003FH Vector table area 64 x 8 bits 0000H 0000H Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H. When boot swap is used: Setting). Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see Table 3-2 Correspondence Between Address Values and Block Numbers in Flash Memory. EFFFH EC00H EBFFH Block 3BH Set the option bytes to 0080H to 0084H and 1080H to 1084H. Security 2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 07FFH 0400H 03FFH 0000H Block 01H Block 00H 1 KB 48 User's Manual U17397EJ4V0UD CHAPTER 3 CPU ARCHITECTURE www..com Figure 3-3. Memory Map (PD78F0546) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH FB00H FAFFH FA20H FA1FH Data memory space FA00H F9FFH F800H F7FFH Program RAM area RAM space in which instruction can be fetched E800H E7FFH C000H BFFFH Bank area 8000H Program 7FFFH memory space Common area Flash memory 16384 x 8 bits (memory bank 0) 0085H 0084H 0080H 007FH (Memory bank 3) General-purpose registers 32 x 8 bits Internal high-speed RAM 1024 x 8 bits Reserved Buffer RAM 32 x 8 bits Reserved 1000H 0FFFH (Memory bank 2) 7FFFH Program area 1FFFH 1085H 1084H 1080H 107FH Option byte areaNote 1 5 x 8 bits Boot cluster 1 Program area Internal expansion RAM 4096 x 8 bits CALLF entry area 2048 x 8 bits 0800H 07FFH Program area 1915 x 8 bits Option byte areaNote 1 5 x 8 bits CALLT table area 64 x 8 bits Boot cluster 0Note 2 Reserved Flash memory 32768 x 8 bits (Memory bank 1) 0040H 003FH Vector table area 64 x 8 bits 0000H 0000H Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H. When boot swap is used: Setting). Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see Table 3-2 Correspondence Between Address Values and Block Numbers in Flash Memory. (Memory bank 0) BFFFH Bank area BC00H BBFFH 84FFH 83FFH 8000H 7FFFH 7C00H 7BFFH Common area 07FFH 0400H 03FFH 1 KB Set the option bytes to 0080H to 0084H and 1080H to 1084H. Security 2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 (Memory bank 1) Block 3FH (Memory bank 2) Block 4FH (Memory bank 3) Block 5FH Block 2FH Block 20H Block 1FH Block 30H Block 40H Block 50H Block 01H Block 00H 0000H User's Manual U17397EJ4V0UD 49 CHAPTER 3 CPU ARCHITECTURE www..com Figure 3-4. Memory Map (PD78F0547) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH FB00H FAFFH FA20H FA1FH Data memory space FA00H F9FFH F800H F7FFH Program RAM area RAM space in which instruction can be fetched E000H DFFFH C000H BFFFH Bank area 8000H Program 7FFFH memory space Common area Flash memory 16384 x 8 bits (memory bank 0) (Memory bank 5) (Memory bank 3) General-purpose registers 32 x 8 bits Internal high-speed RAM 1024 x 8 bits Reserved Buffer RAM 32 x 8 bits Reserved (Memory bank 4) (Memory bank 2) 7FFFH Program area 1FFFH 1085H 1084H 1080H 107FH Option byte area 5 x 8 bits Note 1 Boot cluster 1 Program area 1000H 0FFFH CALLF entry area 2048 x 8 bits 0800H 07FFH Program area 1915 x 8 bits 0085H 0084H 0080H 007FH Option byte areaNote 1 5 x 8 bits CALLT table area 64 x 8 bits Boot cluster 0Note 2 Internal expansion RAM 6144 x 8 bits Reserved Flash memory 32768 x 8 bits 0040H 003FH (Memory bank 1) Vector table area 64 x 8 bits 0000H 0000H Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H. When boot swap is used: Setting). Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see Table 3-2 Correspondence Between Address Values and Block Numbers in Flash Memory. (Memory bank 0) BFFFH BC00H BBFFH 84FFH 83FFH 8000H 7FFFH 7C00H 7BFFH Common area 07FFH 0400H 03FFH 0000H Block 01H Block 00H Block 20H Block 1FH Block 30H Block 40H Block 2FH Block 3FH Block 4FH ... Block 70H Block 7FH (Memory bank 1) (Memory bank 2) (Memory bank 5) Set the option bytes to 0080H to 0084H and 1080H to 1084H. Security 2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 Bank area 1 KB 50 User's Manual U17397EJ4V0UD CHAPTER 3 CPU ARCHITECTURE www..com Figure 3-5. Memory Map (PD78F0547D) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH FB00H FAFFH FA20H FA1FH Data memory space FA00H F9FFH F800H F7FFH Program RAM area RAM space in which instruction can be fetched E000H DFFFH C000H BFFFH Bank area 8000H 7FFFH Program memory space Common area Flash memory 16384 x 8 bits (memory bank 0) (Memory bank 5) (Memory bank 3) 7FFFH General-purpose registers 32 x 8 bits Internal high-speed RAM 1024 x 8 bits Reserved Buffer RAM 32 x 8 bits Reserved (Memory bank 4) (Memory bank 2) Program area 108FH 108EH 1FFFH On-chip debug security ID setting areaNote 1 10 x 8 bits Option byte areaNote 1 5 x 8 bits Program area 1000H 0FFFH CALLF entry area 2048 x 8 bits 0800H 07FFH Program area 1905 x 8 bits 1085H 1084H 1080H 107FH Boot cluster 1 Internal expansion RAM 6144 x 8 bits Reserved 008FH 008EH 0085H 0084H 0080H 007FH On-chip debug security ID setting areaNote 1 10 x 8 bits Option byte areaNote 1 5 x 8 bits CALLT table area 64 x 8 bits Boot cluster 0Note 2 Flash memory 32768 x 8 bits 0040H 003FH (Memory bank 1) Vector table area 64 x 8 bits 0000H 0000H Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H, and the on-chip debug security IDs to 0085H to 008EH. When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H, and the on-chip debug security IDs to 0085H to 008EH and 1085H to 108EH. 2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 Setting). Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see Table 3-2 Correspondence Between Address Values and Block Numbers in Flash Memory. (Memory bank 0) BFFFH BC00H BBFFH 84FFH 83FFH 8000H 7FFFH 7C00H 7BFFH Common area 07FFH 0400H 03FFH 0000H Block 01H Block 00H Block 20H Block 1FH Block 30H Block 40H Block 2FH Block 3FH Block 4FH ... Block 70H Block 7FH (Memory bank 1) (Memory bank 2) (Memory bank 5) Security Bank area 1 KB User's Manual U17397EJ4V0UD 51 CHAPTER 3 CPU ARCHITECTURE www..com Correspondence between the address values and block numbers in the flash memory are shown below. Table 3-2. Correspondence Between Address Values and Block Numbers in Flash Memory (1/2) (1) PD78F0544, 78F0545 Address Value Block Number 0000H to 03FFH 0400H to 07FFH 0800H to 0BFFH 0C00H to 0FFFH 1000H to 13FFH 1400H to 17FFH 1800H to 1BFFH 1C00H to 1FFFH 2000H to 23FFH 2400H to 27FFH 2800H to 2BFFH 2C00H to 2FFFH 3000H to 33FFH 3400H to 37FFH 3800H to 3BFFH 3C00H to 3FFFH 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 4000H to 43FFH 4400H to 47FFH 4800H to 4BFFH 4C00H to 4FFFH 5000H to 53FFH 5400H to 57FFH 5800H to 5BFFH 5C00H to 5FFFH 6000H to 63FFH 6400H to 67FFH 6800H to 6BFFH 6C00H to 6FFFH 7000H to 73FFH 7400H to 77FFH 7800H to 7BFFH 7C00H to 7FFFH Address Value Block Number 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 8000H to 83FFH 8400H to 87FFH 8800H to 8BFFH 8C00H to 8FFFH 9000H to 93FFH 9400H to 97FFH 9800H to 9BFFH 9C00H to 9FFFH A000H to A3FFH A400H to A7FFH A800H to ABFFH AC00H to AFFFH B000H to B3FFH B400H to B7FFH B800H to BBFFH BC00H to BFFFH Address Value Block Number 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH C000H to C3FFH C400H to C7FFH C800H to CBFFH CC00H to CFFFH D000H to D3FFH D400H to D7FFH D800H to DBFFH DC00H to DFFFH E000H to E3FFH E400H to E7FFH E800H to EBFFH EC00H to EFFFH Address Value Block Number 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH Remark PD78F0544: Block numbers 00H to 2FH PD78F0545: Block numbers 00H to 3BH 52 User's Manual U17397EJ4V0UD CHAPTER 3 CPU ARCHITECTURE www..com Table 3-2. Correspondence Between Address Values and Block Numbers in Flash Memory (2/2) (2) PD78F0546, 78F0547, 78F0547D Memory Bank Memory Bank Memory Bank 4 5 Address Value Block Number Address Value Block Number Address Value Block Number Address Value Block Number 0000H to 03FFH 0400H to 07FFH 0800H to 0BFFH 0C00H to 0FFFH 1000H to 13FFH 1400H to 17FFH 1800H to 1BFFH 1C00H to 1FFFH 2000H to 23FFH 2400H to 27FFH 2800H to 2BFFH 2C00H to 2FFFH 3000H to 33FFH 3400H to 37FFH 3800H to 3BFFH 3C00H to 3FFFH 4000H to 43FFH 4400H to 47FFH 4800H to 4BFFH 4C00H to 4FFFH 5000H to 53FFH 5400H to 57FFH 5800H to 5BFFH 5C00H to 5FFFH 6000H to 63FFH 6400H to 67FFH 6800H to 6BFFH 6C00H to 6FFFH 7000H to 73FFH 7400H to 77FFH 7800H to 7BFFH 7C00H to 7FFFH 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 8000H to 83FFH 8400H to 87FFH 8800H to 8BFFH 8C00H to 8FFFH 9000H to 93FFH 9400H to 97FFH 9800H to 9BFFH 9C00H to 9FFFH A000H to A3FFH A400H to A7FFH A800H to ABFFH AC00H to AFFFH B000H to B3FFH B400H to B7FFH B800H to BBFFH BC00H to BFFFH 8000H to 83FFH 8400H to 87FFH 8800H to 8BFFH 8C00H to 8FFFH 9000H to 93FFH 9400H to 97FFH 9800H to 9BFFH 9C00H to 9FFFH A000H to A3FFH A400H to A7FFH A800H to ABFFH AC00H to AFFFH B000H to B3FFH B400H to B7FFH B800H to BBFFH BC00H to BFFFH 0 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 8000H to 83FFH 8400H to 87FFH 8800H to 8BFFH 8C00H to 8FFFH 9000H to 93FFH 9400H to 97FFH 9800H to 9BFFH 9C00H to 9FFFH A000H to A3FFH A400H to A7FFH A800H to ABFFH AC00H to AFFFH B000H to B3FFH B400H to B7FFH B800H to BBFFH BC00H to BFFFH 8000H to 83FFH 8400H to 87FFH 8800H to 8BFFH 8C00H to 8FFFH 9000H to 93FFH 9400H to 97FFH 9800H to 9BFFH 9C00H to 9FFFH A000H to A3FFH A400H to A7FFH A800H to ABFFH AC00H to AFFFH B000H to B3FFH B400H to B7FFH B800H to BBFFH BC00H to BFFFH 2 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 8000H to 83FFH 8400H to 87FFH 8800H to 8BFFH 8C00H to 8FFFH 9000H to 93FFH 9400H to 97FFH 9800H to 9BFFH 9C00H to 9FFFH A000H to A3FFH A400H to A7FFH A800H to ABFFH AC00H to AFFFH B000H to B3FFH B400H to B7FFH B800H to BBFFH BC00H to BFFFH 8000H to 83FFH 8400H to 87FFH 8800H to 8BFFH 8C00H to 8FFFH 9000H to 93FFH 9400H to 97FFH 9800H to 9BFFH 9C00H to 9FFFH A000H to A3FFH A400H to A7FFH A800H to ABFFH AC00H to AFFFH B000H to B3FFH B400H to B7FFH B800H to BBFFH BC00H to BFFFH 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH 1 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 3 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH Remark PD78F0546: Block numbers 00H to 5FH PD78F0547, 78F0547D: Block numbers 00H to 7FH User's Manual U17397EJ4V0UD 53 CHAPTER 3 CPU ARCHITECTURE www..com 3.1.1 Internal program memory space The internal program memory space stores the program and table data. Normally, it is addressed with the program counter (PC). 78K0/KF2 products incorporate internal ROM (flash memory), as shown below. Table 3-3. Internal ROM Capacity Part Number Structure Internal ROM Capacity 49152 x 8 bits (0000H to BFFFH) 61440 x 8 bits (0000H to EFFFH) 98304 x 8 bits (0000H to 7FFFH (common area: 32 KB) + 8000H to BFFFH (bank area: 16 KB) x 4) 131072 x 8 bits (0000H to 7FFFH (common area: 32 KB) + 8000H to BFFFH (bank area: 16 KB) x 6) PD78F0544 PD78F0545 PD78F0546 PD78F0547, 78F0547D Flash memory The internal program memory space is divided into the following areas. (1) Vector table area The 64-byte area 0000H to 003FH is reserved as a vector table area. The program start addresses for branch upon reset or generation of each interrupt request are stored in the vector table area. Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses. Table 3-4. Vector Table Vector Table Address 0000H 0004H 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H 0018H 001AH 001CH 001EH 0020H Interrupt Source RESET input, POC, LVI, WDT INTLVI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTSRE6 INTSR6 INTST6 INTCSI10/INTST0 INTTMH1 INTTMH0 INTTM50 INTTM000 Vector Table Address 0022H 0024H 0026H 0028H 002AH 002CH 002EH 0030H 0032H 0034H 0036H 0038H 003AH 003CH 003EH Interrupt Source INTTM010 INTAD INTSR0 INTWTI INTTM51 INTKR INTWT INTP6 INTP7 INTIIC0/INTDMU INTCSI11 INTTM001 INTTM011 INTACSI BRK 54 User's Manual U17397EJ4V0UD CHAPTER 3 CPU ARCHITECTURE www..com (2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) Option byte area A 5-byte area of 0080H to 0084H and 1080H to 1084H can be used as an option byte area. Set the option byte at 0080H to 0084H when the boot swap is not used, and at 0080H to 0084H and 1080H to 1084H when the boot swap is used. For details, see CHAPTER 26 OPTION BYTE. (4) CALLF instruction entry area The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF). (5) On-chip debug security ID setting area (PD78F0547D only) A 10-byte area of 0085H to 008EH and 1085H to 108EH can be used as an on-chip debug security ID setting area. Set the on-chip debug security ID of 10 bytes at 0085H to 008EH when the boot swap is not used and at 0085H to 008EH and 1085H to 108EH when the boot swap is used. For details, see CHAPTER 28 ON-CHIP DEBUG FUNCTION (PD78F0547D ONLY). 3.1.2 Memory bank (PD78F0546, 78F0547, and 78F0547D only) The 16 KB area 8000H to BFFFH is assigned to memory banks 0 to 3 in the PD78F0546, and assigned to memory banks 0 to 5 in the PD78F0547 and 78F0547D. The banks are selected by using a memory bank select register (BANK). For details, see CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F0546, 78F0547, AND 78F0547D ONLY)). Cautions 1. Instructions cannot be fetched between different memory banks. 2. Branch and access cannot be directly executed between different memory banks. Execute branch or access between different memory banks via the common area. 3. Allocate interrupt servicing in the common area. 4. An instruction that extends from 7FFFH to 8000H can only be executed in memory bank 0. User's Manual U17397EJ4V0UD 55 CHAPTER 3 CPU ARCHITECTURE www..com 3.1.3 Internal data memory space 78K0/KF2 products incorporate the following RAMs. (1) Internal high-speed RAM Table 3-5. Internal High-Speed RAM Capacity Part Number Internal High-Speed RAM 1024 x 8 bits (FB00H to FEFFH) PD78F0544 PD78F0545 PD78F0546 PD78F0547, 78F0547D The 32-byte area FEE0H to FEFFH is assigned to four general-purpose register banks consisting of eight 8-bit registers per bank. This area cannot be used as a program area in which instructions are written and executed. The internal high-speed RAM can also be used as a stack memory. (2) Internal expansion RAM Table 3-6. Internal Expansion RAM Capacity Part Number Internal Expansion RAM 1024 x 8 bits (F400H to F7FFH) 2048 x 8 bits (F000H to F7FFH) 4096 x 8 bits (E800H to F7FFH) 6144 x 8 bits (E000H to F7FFH) PD78F0544 PD78F0545 PD78F0546 PD78F0547, 78F0547D The internal expansion RAM can also be used as a normal data area similar to the internal high-speed RAM, as well as a program area in which instructions can be written and executed. The internal expansion RAM cannot be used as a stack memory. 3.1.4 Special function register (SFR) area On-chip peripheral hardware special function registers (SFRs) are allocated in the area FF00H to FFFFH (see Table 3-6 Special Function Register List in 3.2.3 Special function registers (SFRs)). Caution Do not access addresses to which SFRs are not assigned. 56 User's Manual U17397EJ4V0UD CHAPTER 3 CPU ARCHITECTURE www..com 3.1.5 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the 78K0/KF2, based on operability and other considerations. For areas containing data memory in particular, special addressing methods designed for the functions of special function registers (SFR) and general-purpose registers are available for use. Figures 3-6 to 3-9 show correspondence between data memory and addressing. For details of each addressing mode, see 3.4 Operand Address Addressing. Figure 3-6. Correspondence Between Data Memory and Addressing (PD78F0544) FFFFH Special function registers (SFR) 256 x 8 bits FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Register addressing Short direct addressing SFR addressing Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH FA20H FA1FH Reserved Buffer RAM 32 x 8 bits FA00H F9FFH F800H F7FFH Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved Internal expansion RAM 1024 x 8 bits F400H F3FFH Reserved C000H BFFFH Flash memory 49152 x 8 bits 0000H User's Manual U17397EJ4V0UD 57 CHAPTER 3 CPU ARCHITECTURE www..com Figure 3-7. Correspondence Between Data Memory and Addressing (PD78F0545) FFFFH Special function registers (SFR) 256 x 8 bits FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Register addressing Short direct addressing SFR addressing Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH FA20H FA1FH Reserved Buffer RAM 32 x 8 bits Direct addressing Register indirect addressing Based addressing Based indexed addressing FA00H F9FFH F800H F7FFH Reserved Internal expansion RAM 2048 x 8 bits F000H EFFFH Flash memory 61440 x 8 bits 0000H 58 User's Manual U17397EJ4V0UD CHAPTER 3 CPU ARCHITECTURE www..com Figure 3-8. Correspondence Between Data Memory and Addressing (PD78F0546) FFFFH Special function registers (SFR) 256 x 8 bits FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Register addressing Short direct addressing SFR addressing Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH FA20H FA1FH Reserved Buffer RAM 32 x 8 bits Direct addressing Register indirect addressing Based addressing Based indexed addressing FA00H F9FFH F800H F7FFH Reserved Internal expansion RAM 4096 x 8 bits 16384 x 8 bits (memory bank 2)Note E800H E7FFH Reserved C000H BFFFH Flash memory 16384 x 8 bits (memory bank 0)Note 8000H 7FFFH Flash memory 32768 x 8 bits 0000H 16384 x 8 bits (memory bank 3)Note 16384 x 8 bits (memory bank 1)Note Note To branch to or address a memory bank that is not set by the memory bank select register (BANK), change the setting of the memory bank by using BANK. User's Manual U17397EJ4V0UD 59 CHAPTER 3 CPU ARCHITECTURE www..com Figure 3-9. Correspondence Between Data Memory and Addressing (PD78F0547, 78F0547D) FFFFH Special function registers (SFR) 256 x 8 bits FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Register addressing Short direct addressing SFR addressing Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH FA20H FA1FH Reserved Buffer RAM 32 x 8 bits FA00H F9FFH F800H F7FFH Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved Internal expansion RAM 6144 x 8 bits 16384 x 8 bits (memory bank 4)Note 16384 x 8 bits (memory bank 2)Note E000H DFFFH Reserved C000H BFFFH Flash memory 16384 x 8 bits (memory bank 0)Note 8000H 7FFFH Flash memory 32768 x 8 bits 0000H 16384 x 8 bits (memory bank 5)Note 16384 x 8 bits (memory bank 3)Note 16384 x 8 bits (memory bank 1)Note Note To branch to or address a memory bank that is not set by the memory bank select register (BANK), change the setting of the memory bank by using BANK. 60 User's Manual U17397EJ4V0UD CHAPTER 3 CPU ARCHITECTURE www..com 3.2 Processor Registers The 78K0/KF2 products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed. In normal operation, PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data and register contents are set. Reset signal generation sets the reset vector table values at addresses 0000H and 0001H to the program counter. Figure 3-10. Format of Program Counter 15 0 PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 (2) Program status word (PSW) The program status word is an 8-bit register consisting of various flags set/reset by instruction execution. Program status word contents are stored in the stack area upon interrupt request generation or PUSH PSW instruction execution and are restored upon execution of the RETB, RETI and POP PSW instructions. Reset signal generation sets PSW to 02H. Figure 3-11. Format of Program Status Word 7 PSW IE Z RBS1 AC RBS0 0 ISP 0 CY (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupt requests are disabled. When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgment is controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority specification flag. The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI instruction execution. User's Manual U17397EJ4V0UD 61 CHAPTER 3 CPU ARCHITECTURE www..com (b) Zero flag (Z) When the operation result is zero, this flag is set (1). It is reset (0) in all other cases. (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is stored. (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (e) In-service priority flag (ISP) This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, lowlevel vectored interrupt requests specified by a priority specification flag register (PR0L, PR0H, PR1L, PR1H) (see 20.3 (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H)) can not be acknowledged. Actual request acknowledgment is controlled by the interrupt enable flag (IE). (f) Carry flag (CY) This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 3-12. Format of Stack Pointer 15 0 SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the stack memory. Each stack operation saves/restores data as shown in Figures 3-13 and 3-14. Caution Since reset signal generation makes the SP contents undefined, be sure to initialize the SP before using the stack. 62 User's Manual U17397EJ4V0UD CHAPTER 3 CPU ARCHITECTURE www..com Figure 3-13. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEE0H) SP FEE0H FEE0H FEDFH Register pair higher Register pair lower SP FEDEH FEDEH (b) CALL, CALLF, CALLT instructions (when SP = FEE0H) SP FEE0H FEE0H FEDFH PC15 to PC8 PC7 to PC0 SP FEDEH FEDEH (c) Interrupt, BRK instructions (when SP = FEE0H) SP FEE0H FEE0H FEDFH FEDEH PSW PC15 to PC8 PC7 to PC0 SP FEDDH FEDDH User's Manual U17397EJ4V0UD 63 CHAPTER 3 CPU ARCHITECTURE www..com Figure 3-14. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH) SP FEE0H FEE0H FEDFH Register pair higher Register pair lower SP FEDEH FEDEH (b) RET instruction (when SP = FEDEH) SP FEE0H FEE0H FEDFH PC15 to PC8 PC7 to PC0 SP FEDEH FEDEH (c) RETI, RETB instructions (when SP = FEDDH) SP FEE0H FEE0H FEDFH FEDEH PSW PC15 to PC8 PC7 to PC0 SP FEDDH FEDDH 64 User's Manual U17397EJ4V0UD CHAPTER 3 CPU ARCHITECTURE www..com 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL). These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupts for each bank. Figure 3-15. Configuration of General-Purpose Registers (a) Function name 16-bit processing FEFFH H Register bank 0 FEF8H HL L D Register bank 1 FEF0H BC C A Register bank 3 FEE0H 15 0 7 0 AX X DE E B Register bank 2 FEE8H 8-bit processing (b) Absolute name 16-bit processing FEFFH R7 Register bank 0 FEF8H RP3 R6 R5 Register bank 1 FEF0H RP1 R2 R1 Register bank 3 FEE0H 15 User's Manual U17397EJ4V0UD 8-bit processing RP2 R4 R3 Register bank 2 FEE8H RP0 R0 0 7 0 65 CHAPTER 3 CPU ARCHITECTURE www..com 3.2.3 Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions. The manipulatable bit units, 1, 8, and 16, depend on the special function register type. Each manipulation bit unit can be specified as follows. * 1-bit manipulation Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This manipulation can also be specified with an address. * 8-bit manipulation Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can also be specified with an address. * 16-bit manipulation Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp). When specifying an address, describe an even address. Table 3-7 gives a list of the special function registers. The meanings of items in the table are as follows. * Symbol Symbol indicating the address of a special function register. It is a reserved word in the RA78K0, and is defined as an sfr variable using the #pragma sfr directive in the CC78K0. When using the RA78K0, ID78K0-QB, and SM+ for 78K0/KX2, symbols can be written as an instruction operand. * R/W Indicates whether the corresponding special function register can be read or written. R/W: Read/write enable R: W: Read only Write only * Manipulatable bit units Indicates the manipulatable bit unit (1, 8, or 16). "-" indicates a bit unit for which manipulation is not possible. * After reset Indicates each register status upon reset signal generation. 66 User's Manual U17397EJ4V0UD CHAPTER 3 CPU ARCHITECTURE www..com Table 3-7. Special Function Register List (1/4) Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit 1 Bit FF00H FF01H FF02H FF03H FF04H FF05H FF06H FF07H FF08H FF09H FF0AH FF0BH FF0CH FF0DH FF0EH FF0FH FF10H FF11H FF12H FF13H FF14H FF15H FF16H FF17H FF18H FF19H FF1AH FF1BH FF1FH FF20H FF21H FF22H FF23H FF24H FF25H FF26H FF27H FF28H FF29H FF2CH FF2EH FF2FH 8-bit timer counter 50 8-bit timer compare register 50 8-bit timer H compare register 00 8-bit timer H compare register 10 8-bit timer H compare register 01 8-bit timer H compare register 11 8-bit timer counter 51 Port mode register 0 Port mode register 1 Port mode register 2 Port mode register 3 Port mode register 4 Port mode register 5 Port mode register 6 Port mode register 7 A/D converter mode register Analog input channel specification register Port mode register 12 Port mode register 14 A/D port configuration register TM50 CR50 CMP00 CMP10 CMP01 CMP11 TM51 PM0 PM1 PM2 PM3 PM4 PM5 PM6 PM7 ADM ADS PM12 PM14 ADPC R R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - - - - - - - - - - - - - - - - - - - - - - - - - - - 00H 00H 00H 00H 00H 00H 00H FFH FFH FFH FFH FFH FFH FFH FFH 00H 00H FFH FFH 00H 16-bit timer capture/compare register 010 CR010 R/W - - 0000H 16-bit timer capture/compare register 000 CR000 R/W - - 0000H Port register 0 Port register 1 Port register 2 Port register 3 Port register 4 Port register 5 Port register 6 Port register 7 10-bit A/D conversion result register 8-bit A/D conversion result register Receive buffer register 6 Transmit buffer register 6 Port register 12 Port register 13 Port register 14 Serial I/O shift register 10 16-bit timer counter 00 P0 P1 P2 P3 P4 P5 P6 P7 ADCR ADCRH RXB6 TXB6 P12 P13 P14 SIO10 TM00 R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R R - - - - - - 8 Bits - - 16 Bits - - - - - - - - - - - - - - - After Reset 00H 00H 00H 00H 00H 00H 00H 00H 0000H 00H FFH FFH 00H 00H 00H 00H 0000H User's Manual U17397EJ4V0UD 67 CHAPTER 3 CPU ARCHITECTURE www..com Table 3-7. Special Function Register List (2/4) Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit 1 Bit FF30H FF31H FF33H FF34H FF35H FF36H FF37H FF3CH FF3EH FF40H FF41H FF43H FF48H FF49H FF4AH FF4CH FF4FH FF50H FF53H FF55H FF56H FF57H FF58H FF60H FF61H FF62H FF63H FF64H FF65H FF66H FF67H FF68H FF69H FF6AH FF6BH FF6CH FF6DH FF6EH FF6FH Multiplier/divider control register 0 8-bit timer H mode register 0 Timer clock selection register 50 8-bit timer mode control register 50 8-bit timer H mode register 1 8-bit timer H carrier control register 1 Key return mode register Watch timer operation mode register Multiplication/division data register B0 Multiplication/division data register A0 Pull-up resistor option register 0 Pull-up resistor option register 1 Pull-up resistor option register 3 Pull-up resistor option register 4 Pull-up resistor option register 5 Pull-up resistor option register 6 Pull-up resistor option register 7 Pull-up resistor option register 12 Pull-up resistor option register 14 Clock output selection register 8-bit timer compare register 51 8-bit timer mode control register 51 External interrupt rising edge enable register External interrupt falling edge enable register Serial I/O shift register 11 Transmit buffer register 11 Input switch control register Asynchronous serial interface operation mode register 6 Asynchronous serial interface reception error status register 6 Asynchronous serial interface transmission status register 6 Clock selection register 6 Baud rate generator control register 6 Asynchronous serial interface control register 6 Remainder data register 0 PU0 PU1 PU3 PU4 PU5 PU6 PU7 PU12 PU14 CKS CR51 TMC51 EGP EGN SIO11 SOTB11 ISC ASIM6 ASIS6 ASIF6 CKSR6 BRGC6 ASICL6 SDR0 SDR0L SDR0H 8 Bits 16 Bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - After Reset 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 01H 00H 00H 00H FFH 16H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R R R/W R/W R/W R - - - - - - - - - - - - - - - MDA0L MDA0LL MDA0LH R/W MDA0H MDA0HL MDA0HH R/W MDB0 MDB0L MDB0H R/W DMUC0 TMHMD0 TCL50 TMC50 TMHMD1 TMCYC1 KRM WTM R/W R/W R/W R/W R/W R/W R/W R/W 68 User's Manual U17397EJ4V0UD CHAPTER 3 CPU ARCHITECTURE www..com Table 3-7. Special Function Register List (3/4) Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit 1 Bit FF70H FF71H FF72H FF73H FF74H FF80H FF81H FF84H FF88H FF89H FF8CH FF90H FF91H FF92H FF93H FF94H FF95H FF96H FF97H FF99H FF9FH FFA0H FFA1H FFA2H FFA3H FFA4H FFA5H FFA6H FFA7H FFA8H FFA9H FFAAH FFABH FFACH FFB0H FFB1H Asynchronous serial interface operation mode register 0 Baud rate generator control register 0 Receive buffer register 0 Asynchronous serial interface reception error status register 0 Transmit shift register 0 Serial operation mode register 10 Serial clock selection register 10 Transmit buffer register 10 Serial operation mode register 11 Serial clock selection register 11 Timer clock selection register 51 Serial operation mode specification register 0 Serial status register 0 Serial trigger register 0 Division value selection register 0 Automatic data transfer address point specification register 0 Automatic data transfer interval specification register 0 Serial I/O shift register 0 Automatic data transfer address count register 0 Watchdog timer enable register Clock operation mode select register Internal oscillation mode register Main clock mode register Main OSC control register ASIM0 BRGC0 RXB0 ASIS0 TXS0 CSIM10 CSIC10 SOTB10 CSIM11 CSIC11 TCL51 CSIMA0 CSIS0 CSIT0 BRGCA0 ADTP0 ADTI0 SIOA0 ADTC0 WDTE OSCCTL RCM MCM MOC R/W R/W R R W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R R/W R R - - - - - - - - - - - - - - - - 8 Bits - 16 Bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - After Reset 01H 1FH FFH 00H FFH 00H 00H 00H 00H 00H 00H 00H 00H 00H 03H 00H 00H 00H 00H Note 1 1AH/9AH 00H 80H Note 2 00H 80H 00H 05H 00H 00H 00H 00H 00H 00H 00H 00H Note 3 Oscillation stabilization time counter status register OSTC Oscillation stabilization time select register IIC shift register 0 IIC control register 0 Slave address register 0 IIC clock selection register 0 IIC function expansion register 0 IIC status register 0 IIC flag register 0 Reset control flag register 16-bit timer counter 01 OSTS IIC0 IICC0 SVA0 IICCL0 IICX0 IICS0 IICF0 RESF TM01 0000H Notes 1. 2. 3 The reset value of WDTE is determined by setting of option byte. The value of this register is 00H immediately after a reset release but automatically changes to 80H after oscillation accuracy stabilization of high-speed internal oscillator has been waited. The reset value of RESF varies depending on the reset source. User's Manual U17397EJ4V0UD 69 CHAPTER 3 CPU ARCHITECTURE www..com Table 3-7. Special Function Register List (4/4) Address Special Function Register (SFR) Name Symbol R/W - - - - - Manipulatable Bit Unit 1 Bit FFB2H FFB3H FFB4H FFB5H FFB6H FFB7H FFB8H FFB9H FFBAH FFBBH FFBCH FFBDH FFBEH FFBFH FFE0H FFE1H FFE2H FFE3H FFE4H FFE5H FFE6H FFE7H FFE8H FFE9H FFEAH FFEBH FFF0H FFF3H FFF4H FFFBH 16-bit timer mode control register 01 Prescaler mode register 01 Capture/compare control register 01 16-bit timer output control register 01 16-bit timer mode control register 00 Prescaler mode register 00 Capture/compare control register 00 16-bit timer output control register 00 Low-voltage detection register Low-voltage detection level selection register Interrupt request flag register 0L Interrupt request flag register 0H Interrupt request flag register 1L Interrupt request flag register 1H Interrupt mask flag register 0L Interrupt mask flag register 0H Interrupt mask flag register 1L Interrupt mask flag register 1H Priority specification flag register 0L Priority specification flag register 0H Priority specification flag register 1L Priority specification flag register 1H Internal memory size switching register Memory bank select register Internal expansion RAM size switching register Processor clock control register Note 2 Note 2 8 Bits - - 16 Bits - - - - - - - - - - - - - - After Reset 0000H 0000H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H Note 1 Note 1 16-bit timer capture/compare register 001 16-bit timer capture/compare register 011 CR001 CR011 TMC01 PRM01 CRC01 TOC01 TMC00 PRM00 CRC00 TOC00 LVIM LVIS IF0 IF1 MK0 MK1 PR0 PR1 IMS BANK IXS PCC IF0L IF0H IF1L IF1H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00H 00H 00H 00H FFH FFH FFH FFH FFH FFH FFH FFH CFH 00H 0CH 01H MK0L R/W MK0H R/W MK1L R/W MK1H R/W PR0L R/W PR0H R/W PR1L R/W PR1H R/W R/W R/W R/W R/W Notes 1. 2. The reset values of LVIM and LVIS vary depending on the reset source. Regardless of the internal memory capacity, the initial values of the internal memory size switching register (IMS) and internal expansion RAM size switching register (IXS) of all products in the 78K0/KF2 are fixed (IMS = CFH, IXS = 0CH). Therefore, set the value corresponding to each product as indicated below. Flash Memory Version (78K0/KF2) IMS IXS ROM Capacity Internal High-Speed RAM Capacity Internal Expansion RAM Capacity 1 KB 2 KB 4 KB 6 KB PD78F0544 PD78F0545 PD78F0546 PD78F0547, 78F0547D Note3 CCH CFH CCH CCH 0AH 08H 04H 00H 48 KB 60 KB 96 KB 128 KB 1 KB 3. The ROM and RAM capacities of the products with the on-chip debug function can be debugged according to the debug target products. Set IMS and IXS according to the debug target products. 70 User's Manual U17397EJ4V0UD CHAPTER 3 CPU ARCHITECTURE www..com 3.3 Instruction Address Addressing An instruction address is determined by contents of the program counter (PC) and memory bank select register (BANK), and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to PC and branched by the following addressing (for details of instructions, refer to the 78K/0 Series Instructions User's Manual (U12326E)). 3.3.1 Relative addressing [Function] The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) and branched. displacement value is treated as signed two's complement data (-128 to +127) and bit 7 becomes a sign bit. In other words, relative addressing consists of relative branching from the start address of the following instruction to the -128 to +127 range. This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed. [Illustration] 15 PC + 15 8 7 S jdisp8 15 PC 0 6 0 0 ... PC indicates the start address of the instruction after the BR instruction. The When S = 0, all bits of are 0. When S = 1, all bits of are 1. User's Manual U17397EJ4V0UD 71 CHAPTER 3 CPU ARCHITECTURE www..com 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space. However, before branching to a memory bank that is not set by the memory bank select register (BANK), change the setting of the memory bank by using BANK. The CALLF !addr11 instruction is branched to the 0800H to 0FFFH area. [Illustration] In the case of CALL !addr16 and BR !addr16 instructions 7 CALL or BR Low Addr. High Addr. 0 15 PC 87 0 In the case of CALLF !addr11 instruction 76 fa10-8 fa7-0 4 3 CALLF 0 15 PC 0 0 0 0 11 10 1 87 0 72 User's Manual U17397EJ4V0UD CHAPTER 3 CPU ARCHITECTURE www..com 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed. This instruction references the address stored in the memory table from 40H to 7FH, and allows branching to the entire memory space. However, before branching to a memory bank that is not set by the memory bank select register (BANK), change the setting of the memory bank by using BANK. [Illustration] 7 Operation code 1 6 1 5 ta4-0 1 0 1 15 Effective address 0 0 0 0 0 0 0 8 0 7 0 6 1 5 10 0 7 Memory (Table) Low Addr. 0 Effective address+1 High Addr. 15 PC 8 7 0 3.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration] 7 rp A 0 7 X 0 15 PC 8 7 0 User's Manual U17397EJ4V0UD 73 CHAPTER 3 CPU ARCHITECTURE www..com 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically (implicitly) addressed. Of the 78K0/KF2 instruction words, the following instructions employ implied addressing. Instruction MULU DIVUW ADJBA/ADJBS ROR4/ROL4 Register to Be Specified by Implied Addressing A register for multiplicand and AX register for product storage AX register for dividend and quotient storage A register for storage of numeric values that become decimal correction targets A register for storage of digit data that undergoes digit rotation [Operand format] Because implied addressing can be automatically determined with an instruction, no particular operand format is necessary. [Description example] In the case of MULU X With an 8-bit x 8-bit multiply instruction, the product of the A register and X register is stored in AX. In this example, the A and AX registers are specified by implied addressing. 74 User's Manual U17397EJ4V0UD CHAPTER 3 CPU ARCHITECTURE www..com 3.4.2 Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes of an operation code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [Operand format] Identifier r rp Description X, A, C, B, E, D, L, H AX, BC, DE, HL `r' and `rp' can be described by absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL). [Description example] MOV A, C; when selecting C register as r Operation code 0 1 1 0 0 0 1 0 Register specify code INCW DE; when selecting DE register pair as rp Operation code 1 0 0 0 0 1 0 0 Register specify code User's Manual U17397EJ4V0UD 75 CHAPTER 3 CPU ARCHITECTURE www..com 3.4.3 Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. This addressing can be carried out for all of the memory spaces. However, before addressing a memory bank that is not set by the memory bank select register (BANK), change the setting of the memory bank by using BANK. [Operand format] Identifier addr16 Description Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code 1 0 0 0 1 1 1 0 OP code 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH [Illustration] 7 OP code addr16 (lower) addr16 (upper) 0 Memory 76 User's Manual U17397EJ4V0UD CHAPTER 3 CPU ARCHITECTURE www..com 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal high-speed RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the overall SFR area. Ports that are frequently accessed in a program and compare and capture registers of the timer/event counter are mapped in this area, allowing SFRs to be manipulated with a small number of bytes and clocks. When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH, bit 8 is set to 1. See the [Illustration] shown below. [Operand format] Identifier saddr saddrp Description Immediate data that indicate label or FE20H to FF1FH Immediate data that indicate label or FE20H to FF1FH (even address only) [Description example] LB1 EQU 0FE30H ; Defines FE30H by LB1. : MOV LB1, A ; When LB1 indicates FE30H of the saddr area and the value of register A is transferred to that address Operation code 1 1 1 1 0 0 1 0 OP code 0 0 1 1 0 0 0 0 30H (saddr-offset) [Illustration] 7 OP code saddr-offset 0 Short direct memory 15 Effective address 1 1 1 1 1 1 1 87 0 When 8-bit immediate data is 20H to FFH, = 0 When 8-bit immediate data is 00H to 1FH, = 1 User's Manual U17397EJ4V0UD 77 CHAPTER 3 CPU ARCHITECTURE www..com 3.4.5 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing. [Operand format] Identifier sfr sfrp Special function register name 16-bit manipulatable special function register name (even address only) Description [Description example] MOV PM0, A; when selecting PM0 (FF20H) as sfr Operation code 1 1 1 1 0 1 1 0 OP code 0 0 1 0 0 0 0 0 20H (sfr-offset) [Illustration] 7 OP code sfr-offset 0 SFR 15 Effective address 1 1 1 1 1 1 1 87 1 0 78 User's Manual U17397EJ4V0UD CHAPTER 3 CPU ARCHITECTURE www..com 3.4.6 Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be carried out for all of the memory spaces. However, before addressing a memory bank that is not set by the memory bank select register (BANK), change the setting of the memory bank by using BANK. [Operand format] Identifier - [DE], [HL] Description [Description example] MOV A, [DE]; when selecting [DE] as register pair Operation code 1 0 0 0 0 1 0 1 [Illustration] 16 DE D 87 E The memory address specified with the register pair DE 0 7 The contents of the memory addressed are transferred. 7 A 0 Memory 0 User's Manual U17397EJ4V0UD 79 CHAPTER 3 CPU ARCHITECTURE www..com 3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all of the memory spaces. However, before addressing a memory bank that is not set by the memory bank select register (BANK), change the setting of the memory bank by using BANK. [Operand format] Identifier - [HL + byte] Description [Description example] MOV A, [HL + 10H]; when setting byte to 10H Operation code 1 0 1 0 1 1 1 0 0 0 0 1 0 0 0 0 [Illustration] 16 HL H 87 L +10 0 7 The contents of the memory addressed are transferred. 7 A 0 Memory 0 80 User's Manual U17397EJ4V0UD CHAPTER 3 CPU ARCHITECTURE www..com 3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory. Addition is performed by expanding the B or C register contents as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all of the memory spaces. However, before addressing a memory bank that is not set by the memory bank select register (BANK), change the setting of the memory bank by using BANK. [Operand format] Identifier - [HL + B], [HL + C] Description [Description example] MOV A, [HL +B]; when selecting B register Operation code 1 0 1 0 1 0 1 1 [Illustration] 16 HL H + 7 B 0 8 7 L 0 7 The contents of the memory addressed are transferred. 7 A 0 Memory 0 User's Manual U17397EJ4V0UD 81 CHAPTER 3 CPU ARCHITECTURE www..com 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. With stack addressing, only the internal high-speed RAM area can be accessed. [Description example] PUSH DE; when saving DE register Operation code 1 0 1 1 0 1 0 1 [Illustration] 7 SP FEE0H FEE0H FEDFH SP FEDEH FEDEH D E Memory 0 82 User's Manual U17397EJ4V0UD www..com CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F0546, 78F0547, AND 78F0547D ONLY) 4.1 Memory Bank The PD78F0546, 78F0547, and 78F0547D implement a ROM capacity of 96 KB or 128 KB by selecting a memory bank from a memory space of 8000H to BFFFH. The PD78F0546 has memory banks 0 to 3, and the PD78F0547 and 78F0547D have memory banks 0 to 5, as shown below. The memory banks are selected by using a memory bank select register (BANK). Figure 4-1. Internal ROM (Flash Memory) Configuration (a) PD78F0546 (Memory bank 3) (Memory bank 2) (Memory bank 1) BFFFH Bank area 8000H 7FFFH Common area Flash memory 16384 x 8 bits (memory bank 0) Flash memory 32768 x 8 bits 0000H (b) PD78F0547, 78F0547D (Memory bank 5) (Memory bank 4) (Memory bank 3) (Memory bank 2) (Memory bank 1) BFFFH Bank area 8000H 7FFFH Common area Flash memory 16384 x 8 bits (memory bank 0) Flash memory 32768 x 8 bits 0000H User's Manual U17397EJ4V0UD 83 CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F0546, 78F0547, AND 78F0547D ONLY) www..com Memory bank 5 Memory bank 4 Memory bank 3 Memory bank 2 Memory bank 1 (b) Flash memory real address (HEX FORMAT [BANK]) 1FFFFH 1C000H 1BFFFH 18000H 17FFFH 14000H 13FFFH 10000H 0FFFFH 0C000H 0BFFFH Memory bank 5 (16 KB) Memory bank 4 (16 KB) Memory bank 3 (16 KB) Memory bank 2 (16 KB) Memory bank 1 (16 KB) Memory bank 0 (16 KB) Common (32 KB) 00000H BFFFH Bank area 8000H 7FFFH Common area Memory bank 0 (16 KB) Common (32 KB) 08000H 07FFFH 0000H "Memory bank number + CPU address" is represented with a vacancy in the address space, while the flash memory real address is shown with no vacancy in the address space. "Memory bank number + CPU address" is used for addressing in the user program. For on-board programming and self programming not using the self programming sample libraryNote 1, the flash memory real address is used. Note that the HEX file that is output by the assembler (RA78K0) by default uses the flash memory real address. For address representation of the other tools such as the simulator and the debuggerNote 2, see Table 4-1. Notes 1. "Memory bank number + CPU address" can be used when performing self programming, using the self programming sample library, because the addresses are automatically translated. 2. SM+ for 78K0/Kx2, ID78K0-QB 84 User's Manual U17397EJ4V0UD CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F0546, 78F0547, AND 78F0547D ONLY) www..com Table 4-1. Memory Bank Address Representation Memory Bank Number CPU Address Flash Memory Real Address Address Representation in Simulator and Debugger Memory bank 0 Memory bank 1 Memory bank 2 Memory bank 3 Memory bank 4 Memory bank 5 08000H-0BFFFH Note 2 Note 1 08000H-0BFFFH 0C000H-0FFFFH 10000H-13FFFH 14000H-17FFFH 18000H-1BFFFH 1C000H-1FFFFH 08000H-0BFFFH 18000H-1BFFFH 28000H-2BFFFH 38000H-3BFFFH 48000H-4BFFFH 58000H-5BFFFH Notes 1. SM+ for 78K0/Kx2, ID78K0-QB 2. Set the memory bank to be used by the memory bank select register (BANK) (see Figure 4-3). For details, see the RA78K0 Ver. 3.80 Assembler Package Operation User's Manual (U17199E) and the 78K0/Kx2 Flash Memory Self Programming User's Manual (U17516E). 4.3 Memory Bank Select Register (BANK) The memory bank select register (BANK) is used to select a memory bank to be used. BANK can be set by an 8-bit memory manipulation instruction. Reset signal generation clears BANK to 00H. Figure 4-3. Format of Memory Bank Select Register (BANK) Address: FFF3H After reset: 00H R/W Symbol BANK 7 0 6 0 5 0 4 0 3 0 2 BANK2 1 BANK1 0 BANK0 BANK2 BANK1 BANK0 Bank setting PD78F0546 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 PD78F0547, 78F0547D Common area (32 K) + memory bank 0 (16 K) Common area (32 K) + memory bank 1 (16 K) Common area (32 K) + memory bank 2 (16 K) Common area (32 K) + memory bank 3 (16 K) Setting prohibited Common area (32 K) + memory bank 4 (16 K) 1 0 1 Common area (32 K) + memory bank 5 (16 K) Other than above Setting prohibited Caution Be sure to change the value of the BANK register in the common area (0000H to 7FFFH). If the value of the BANK register is changed in the bank area (8000H to BFFFH), an inadvertent program loop occurs in the CPU. Therefore, never change the value of the BANK register in the bank area. User's Manual U17397EJ4V0UD 85 CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F0546, 78F0547, AND 78F0547D ONLY) www..com 4.4 Selecting Memory Bank The memory bank selected by the memory bank select register (BANK) is reflected on the bank area and can be addressed. Therefore, to access a memory bank different from the one currently selected, that memory bank must be selected by using the BANK register. The value of the BANK register must not be changed in the bank area (8000H to BFFFH). Therefore, to change the memory bank, branch an instruction to the common area (0000H to 7FFFH) and change the value of the BANK register in that area. Cautions 1. Instructions cannot be fetched between different memory banks. 2. Branching and accessing cannot be directly executed between different memory banks. Execute branching or accessing between different memory banks via the common area. 3. Allocate interrupt servicing in the common area. 4. An instruction that extends from 7FFFH to 8000H can only be executed in memory bank 0. 4.4.1 Referencing values between memory banks Values cannot be directly referenced from one memory bank to another. To access another memory bank from one memory bank, branch once to the common area (0000H to 7FFFH), change the setting of the BANK register there, and then reference a value. Memory bank n Bank area Memory bank m Referencing value Common area Memory bank n Bank area Memory bank m Common area Referencing value 86 User's Manual U17397EJ4V0UD CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F0546, 78F0547, AND 78F0547D ONLY) www..com * Software example (to store a value to be referenced in register A) RAMD R_BNKA: R_BNKN: R_BNKRN: DSEG DS DS DS SADDR 2 1 1 ; Secures RAM for specifying an address at the reference destination. ; Secures RAM for specifying a memory bank number at the reference destination. ; Secures RAM for saving a memory bank number at the reference source. ETRC ENTRY: CSEG UNIT MOV MOVW CALL R_BNKN,#BANKNUM R_BNKA,#DATA1 !BNKRD : : AT 7000H DATA1 ; Stores the memory bank number at the reference destination. ; Stores the address at the reference destination. ; Calls a subroutine for referencing between memory banks. BNKC BNKRD: CSEG PUSH MOV XCH MOV XCHW MOVW XCHW MOV XCH MOV MOV POP RET DATA DATA1: END CSEG DB HL A,R_BNKN A,BANK R_BNKRN,A AX,HL AX,R_BNKA AX,HL A,[HL] A,R_BNKRN BANK,A A,R_BNKRN HL ; Subroutine for referencing between memory banks. ; Saves the contents of the HL register. ; Acquires the memory bank number at the reference destination. ; Swaps the memory bank number at the reference source for that at the reference ; destination ; Saves the memory bank number at the reference source. ; Saves the contents of the X register. ; Acquires the address at the reference destination. ; Specifies the address at the reference destination. ; Reads the target value. ; Acquires the memory bank number at the reference source. ; Specifies the memory bank number at the reference source. ; Write the target value to the A register. ; Restores the contents of the HL register. ; Return BANK3 0AAH User's Manual U17397EJ4V0UD 87 CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F0546, 78F0547, AND 78F0547D ONLY) www..com 4.4.2 Branching instruction between memory banks Instructions cannot branch directly from one memory bank to another. To branch an instruction from one memory bank to another, branch once to the common area (0000H to 7FFFH), change the setting of the BANK register there, and then execute the branch instruction again. Memory bank n Bank area Memory bank m Instruction branch Common area Memory bank n Bank area Memory bank m Instruction branch Common area 88 User's Manual U17397EJ4V0UD CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F0546, 78F0547, AND 78F0547D ONLY) www..com * Software example 1 (to branch from all areas) RAMD R_BNKA: R_BNKN: RSAVEAX: DSEG DS DS DS SADDR 2 1 2 ; Secures RAM for specifying a memory bank at the branch destination. ; Secures RAM for specifying a memory bank number at the branch destination. ; Secures RAM for saving the AX register. ETRC ENTRY: CSEG MOV MOVW BR : : UNIT R_BNKN,#BANKNUM R_BNKA,#TEST !BNKBR TEST ; Stores the memory bank number at the branch destination in RAM. ; Stores the address at the branch destination in RAM. ; Branches to inter-memory bank branch processing. BNKC BNKBR: CSEG MOVW MOV MOV MOVW PUSH MOVW RET AT 7000H ; ; Saves the AX register. ; Acquires the memory bank number at the branch destination. ; Specifies the memory bank number at the branch destination. ; Specifies the address at the branch destination. ; Sets the address at the branch destination to stack. ; Restores the AX register. ; Branch RSAVEAX,AX A,R_BNKN BANK,A AX,R_BNKA AX AX,RSAVEAX BN3 TEST: CSEG MOV : : BANK3 END * Software example 2 (to branch from common area to any bank area) ETRC ENTRY: CSEG MOV BR AT 2000H ; Stores the memory bank number at the branch destination in RAM. ; Stores the address at the branch destination in RAM. R_BNKN,#BANKNUM TEST !TEST BN3 TEST: CSEG MOV : : BANK3 END User's Manual U17397EJ4V0UD 89 CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F0546, 78F0547, AND 78F0547D ONLY) www..com 4.4.3 Subroutine call between memory banks Subroutines cannot be directly called between memory banks. To call a subroutine between memory banks, branch once to the common area (0000H to 7FFFH), specify the memory bank at the calling destination by using the BANK register there, execute the CALL instruction, and branch to the call destination by that instruction. At this time, save the current value of the BANK register to RAM. Restore the value of the BANK register before executing the RET instruction. Memory bank n Bank area Memory bank m CALL instruction Common area Memory bank n Bank area Memory bank m BR instruction Common area CALL instruction CALL instruction RET instruction RET instruction Change BANK and save memory bank number at calling source. 90 User's Manual U17397EJ4V0UD CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F0546, 78F0547, AND 78F0547D ONLY) www..com * Software example RAMD R_BNKA: R_BNKN: R_BNKRN: RSAVEAX: ETRC ENTRY: DSEG DS DS DS DS CSEG MOV MOVW CALL SADDR 2 1 1 2 UNIT R_BNKN,#BANKNUM R_BNKA,#TEST !BNKCAL : : AT 7000H ; Inter-memory bank calling processing routine ; Saves the AX register. ; Acquires the memory bank number at the calling destination. ; Changes the bank and acquires the memory bank number at the calling source. ; Saves the memory bank number at the calling source to RAM. ; Calls a subroutine to branch to the calling destination. ; Saves the AX register. ; Acquires the memory bank number at the calling source. ; Specifies the memory bank number at the calling source. ; Restores the AX register. ; Returns to the calling source. TEST ; Store the memory bank number at the calling destination in RAM. ; Stores the address at the calling destination in RAM. ; Branches to an inter-memory bank calling processing routine. ; Secures RAM for specifying an address at the calling destination. ; Secures RAM for specifying a memory bank number at the calling destination. ; Secures RAM for saving a memory bank number at the calling source. ; Secures RAM for saving the AX register. BNKC BNKCAL: CSEG MOVW MOV XCH MOV CALL MOVW XCH MOV MOVW RET RSAVEAX,AX A,R_BNKN A,BANK R_BNKRN,A !BNKCALS RSAVEAX,AX A,R_BNKRN BANK,A RSAVEAX,AX BNKCALS: MOVW PUSH MOVW RET BN3 TEST: CSEG MOV : : RET END AX,R_BNKA AX AX,RSAVEAX AX BANK3 ; ; Specifies the address at the calling destination. ; Sets the address at the calling destination to stack. ; Restores source AX register. ; Branches to the calling destination. Remark In the software example above, multiplexed processing is not supported. User's Manual U17397EJ4V0UD 91 CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F0546, 78F0547, AND 78F0547D ONLY) www..com 4.4.4 Instruction branch to bank area by interrupt When an interrupt occurs, instructions can branch to the memory bank specified by the BANK register by using the vector table, but it is difficult to identify the BANK register when the interrupt occurs. Therefore, specify the branch destination address specified by the vector table in the common area (0000H to 7FFFH), specify the memory bank at the branch destination by using the BANK register in the common area, and execute the CALL instruction. At this time, save the BANK register value before the change to RAM, and restore the value of the BANK register before executing the RETI instruction. Remark Allocate interrupt servicing that requires a quick response in the common area. Memory bank n Bank area Instruction branch Memory bank m Common area Save the original memory bank number. Specify the address and memory bank at the destination, and execute the call instruction. Vector table * Software example (when using interrupt request of 16-bit timer/event counter 00) VCTBL CSEG DW AT 0020H BNKITM000 SADDR 1 ; Specifies an address at the timer interrupt destination. RAMD DSEG R_BNKRN: DS ; Secures RAM for saving the memory bank number before the interrupt occurs. BNKC CSEG AT 7000H ; Inter-memory bank interrupt servicing routine ; Saves the contents of the AX register. BNKITM000: PUSH MOV MOV MOV CALL MOV MOV POP RETI BN3 TEST: CSEG MOV : : RET END AX A,BANK R_BNKRN,A BANK,#BANKNUM TEST !TEST A,R_BNKRN BANK,A AX ; Saves the memory bank number before the interrupt to RAM. ; Specifies the memory bank number of the interrupt routine. ; Calls the interrupt routine. ; Restores the memory bank number before the interrupt. ; Restores the contents of the AX register. BANK3 ; Interrupt servicing routine 92 User's Manual U17397EJ4V0UD CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F0546, 78F0547, AND 78F0547D ONLY) www..co Remark Note the following points to use the memory bank select function efficiently. * Allocate a routine that is used often in the common area. * If a value that is planned to be referenced is placed in RAM, it can be referenced from all of the areas. * If the reference destination and the branch destination of the routine placed in a memory bank are placed in the same memory bank, then the code size and processing are more efficient. * Allocate interrupt servicing that requires a quick response in the common area. User's Manual U17397EJ4V0UD 93 www..com CHAPTER 5 PORT FUNCTIONS 5.1 Port Functions There are three types of pin I/O buffer power supplies: AVREF, EVDD, and VDD. The relationship between these power supplies and the pins is shown below. Table 5-1. Pin I/O Buffer Power Supplies Power Supply AVREF EVDD VDD P20 to P27 Port pins other than P20 to P27 and P121 to P124 * P121 to P124 * Non-port pins Corresponding Pins 78K0/KF2 products are provided with the ports shown in Figure 5-1, which enable variety of control operations. The functions of each port are shown in Table 5-2. In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate functions, see CHAPTER 2 PIN FUNCTIONS. Figure 5-1. Port Types P50 P00 Port 5 P06 P57 P10 P60 Port 0 Port 1 Port 6 P17 P67 P20 P70 Port 2 Port 7 P27 P77 P30 P120 Port 12 P124 Port 13 P130 P140 Port 14 P145 P47 Port 4 P33 P40 Port 3 94 User's Manual U17397EJ4V0UD CHAPTER 5 PORT FUNCTIONS www..com Table 5-2. Port Functions (1/2) Function Name P00 P01 P02 P03 P04 P05 P06 P10 P11 P12 P13 P14 P15 P16 P17 P20 to P27 I/O Port 2. 8-bit I/O port. Input/output can be specified in 1-bit units. P30 P31 P32 P33 P40 to P47 I/O I/O Port 3. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Port 4. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P50 to P57 I/O Port 5. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P60 P61 P62 P63 to P67 I/O Port 6. 8-bit I/O port. Output of P60 to P63 is N-ch open-drain output (6 V tolerance). Input/output can be specified in 1-bit units. Only for P64 to P67, use of an on-chip resistor can be specified by a software setting. P70 to P77 I/O Port 7. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input port KR0 to KR7 Input port SCL0 SDA0 EXSCL0 - Input port - Input port Analog input INTP1 INTP2/OCD1A INTP3/OCD1B Note I/O I/O Port 0. 7-bit I/O port. Function After Reset Input port Alternate Function TI000 TI010/TO00 SO11 SI11 SCK11 TI001/SSI11 TI011/TO01 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. I/O Port 1. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input port SCK10/TxD0 SI10/RxD0 SO10 TxD6 RxD6 TOH0 TOH1/INTP5 TI50/TO50 Input port ANI0 to ANI7 Note TI51/TO51/INTP4 - Note PD78F0547D only User's Manual U17397EJ4V0UD 95 CHAPTER 5 PORT FUNCTIONS www..com Table 5-2. Port Functions (2/2) Function Name P120 P121 P122 P123 P124 P130 Output Port 13. 1-bit output-only port. P140 P141 P142 P143 P144 P145 I/O Port 14. 6-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input port PCL/INTP6 BUZ/BUSY0/INTP7 SCKA0 SIA0 SOA0 STB0 Output port I/O I/O Port 12. 5-bit I/O port. Input/output can be specified in 1-bit units. Only for P120, use of an on-chip pull-up resistor can be specified by a software setting. Function After Reset Input port Alternate Function INTP0/EXLVI X1/OCD0A Note X2/EXCLK/OCD0B XT1 XT2/EXCLKS - Note Note PD78F0547D only 5.2 Port Configuration Ports include the following hardware. Table 5-3. Port Configuration Item Control registers Configuration Port mode register (PM0 to PM7, PM12, PM14) Port register (P0 to P7, P12 to P14) Pull-up resistor option register (PU0, PU1, PU3 to PU7, PU12, PU14) A/D port configuration register (ADPC) Port Pull-up resistor Total: 71 (CMOS I/O: 66, CMOS output: 1, N-ch open drain I/O: 4) Total: 54 96 User's Manual U17397EJ4V0UD CHAPTER 5 PORT FUNCTIONS www..com 5.2.1 Port 0 Port 0 is a 7-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 to P06 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0). This port can also be used for timer I/O, serial interface data I/O, clock I/O, and chip select input. Reset signal generation sets port 0 to input mode. Figures 5-2 to 5-5 show block diagrams of port 0. Caution To use P02/SO11 and P04/SCK11 as general-purpose ports, set serial operation mode register 11 (CSIM11) and serial clock selection register 11 (CSIC11) to the default status (00H). Figure 5-2. Block Diagram of P00, P03, and P05 EVDD WRPU PU0 PU00, PU03, PU05 P-ch Alternate function RD Selector Internal bus WRPORT P0 Output latch (P00, P03, P05) WRPM PM0 PM00, PM03, PM05 P00/TI000, P03/SI11, P05/SSI11/TI001 P0: PU0: PM0: RD: Port register 0 Pull-up resistor option register 0 Port mode register 0 Read signal WRxx: Write signal User's Manual U17397EJ4V0UD 97 CHAPTER 5 PORT FUNCTIONS www..com Figure 5-3. Block Diagram of P01 and P06 EVDD WRPU PU0 PU01, PU06 P-ch Alternate function RD Internal bus WRPORT P0 Output latch (P01, P06) WRPM PM0 PM01, PM06 P01/TI010/TO00, P06/TI011/TO01 Alternate function P0: PU0: PM0: RD: Port register 0 Pull-up resistor option register 0 Port mode register 0 Read signal WRxx: Write signal 98 User's Manual U17397EJ4V0UD Selector CHAPTER 5 PORT FUNCTIONS www..com Figure 5-4. Block Diagram of P02 EVDD WRPU PU0 PU02 RD P-ch Internal bus WRPORT P0 Output latch (P02) WRPM PM0 PM02 P02/SO11 Alternate function P0: PU0: PM0: RD: Port register 0 Pull-up resistor option register 0 Port mode register 0 Read signal WRxx: Write signal Selector User's Manual U17397EJ4V0UD 99 CHAPTER 5 PORT FUNCTIONS www..com Figure 5-5. Block Diagram of P04 EVDD WRPU PU0 PU04 P-ch Alternate function RD Internal bus WRPORT P0 Output latch (P04) WRPM PM0 PM04 P04/SCK11 Alternate function P0: PU0: PM0: RD: Port register 0 Pull-up resistor option register 0 Port mode register 0 Read signal WRxx: Write signal 100 User's Manual U17397EJ4V0UD Selector CHAPTER 5 PORT FUNCTIONS www..com 5.2.2 Port 1 Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1). This port can also be used for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. Reset signal generation sets port 1 to input mode. Figures 5-6 to 5-10 show block diagrams of port 1. Caution To use P10/SCK10/TxD0 and P12/SO10 as general-purpose ports, set serial operation mode register 10 (CSIM10) and serial clock selection register 10 (CSIC10) to the default status (00H). Figure 5-6. Block Diagram of P10 EVDD WRPU PU1 PU10 P-ch Alternate function RD Internal bus WRPORT P1 Output latch (P10) WRPM PM1 PM10 P10/SCK10/TxD0 Alternate function P1: PU1: PM1: RD: Port register 1 Pull-up resistor option register 1 Port mode register 1 Read signal WRxx: Write signal Selector User's Manual U17397EJ4V0UD 101 CHAPTER 5 PORT FUNCTIONS www..com Figure 5-7. Block Diagram of P11 and P14 EVDD WRPU PU1 PU11, PU14 P-ch Alternate function RD Internal bus Selector WRPORT P1 Output latch (P11, P14) WRPM PM1 PM11, PM14 P11/SI10/RxD0, P14/RxD6 P1: PU1: PM1: RD: Port register 1 Pull-up resistor option register 1 Port mode register 1 Read signal WRxx: Write signal 102 User's Manual U17397EJ4V0UD CHAPTER 5 PORT FUNCTIONS www..com Figure 5-8. Block Diagram of P12 and P15 EVDD WRPU PU1 PU12, PU15 RD P-ch Internal bus WRPORT P1 Output latch (P12, P15) WRPM PM1 PM12, PM15 P12/SO10 P15/TOH0 Alternate function P1: PU1: PM1: RD: Port register 1 Pull-up resistor option register 1 Port mode register 1 Read signal WRxx: Write signal Selector User's Manual U17397EJ4V0UD 103 CHAPTER 5 PORT FUNCTIONS www..com Figure 5-9. Block Diagram of P13 EVDD WRPU PU1 PU13 RD P-ch Internal bus WRPORT P1 Output latch (P13) WRPM PM1 PM13 P13/TxD6 Alternate function P1: PU1: PM1: RD: Port register 1 Pull-up resistor option register 1 Port mode register 1 Read signal WRxx: Write signal 104 User's Manual U17397EJ4V0UD Selector CHAPTER 5 PORT FUNCTIONS www..com Figure 5-10. Block Diagram of P16 and P17 EVDD WRPU PU1 PU16, PU17 P-ch Alternate function RD Internal bus WRPORT P1 Output latch (P16, P17) WRPM PM1 PM16, PM17 P16/TOH1/INTP5, P17/TI50/TO50 Alternate function P1: PU1: PM1: RD: Port register 1 Pull-up resistor option register 1 Port mode register 1 Read signal WRxx: Write signal Selector User's Manual U17397EJ4V0UD 105 CHAPTER 5 PORT FUNCTIONS www..com 5.2.3 Port 2 Port 2 is an 8-bit I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port mode register 2 (PM2). This port can also be used for A/D converter analog input. To use P20/ANI0 to P27/ANI7 as digital input pins, set them in the digital I/O mode by using the A/D port configuration register (ADPC) and in the input mode by using PM2. Use these pins starting from the lower bit. To use P20/ANI0 to P27/ANI7 as digital output pins, set them in the digital I/O mode by using ADPC and in the output mode by using PM2. Table 5-4. Setting Functions of P20/ANI0 to P27/ANI7 Pins ADPC Digital I/O selection PM2 Input mode Output mode Analog input selection Input mode Selects ANI. Does not select ANI. Output mode Selects ANI. Does not select ANI. ADS - - P20/ANI0 to P27/ANI7 Pin Digital input Digital output Analog input (to be converted) Analog input (not to be converted) Setting prohibited All P20/ANI0 to P27/ANI7 are set in the analog input mode when the reset signal is generated. Figure 5-11 shows a block diagram of port 2. Caution Make the AVREF pin the same potential as the VDD pin when port 2 is used as a digital port. Figure 5-11. Block Diagram of P20 to P27 RD Internal bus WRPORT P2 Output latch (P20 to P27) WRPM PM2 PM20 to PM27 A/D converter P20/ANI0 to P27/ANI7 P2: PM2: RD: Port register 2 Port mode register 2 Read signal WRxx: Write signal 106 User's Manual U17397EJ4V0UD Selector CHAPTER 5 PORT FUNCTIONS www..com 5.2.4 Port 3 Port 3 is a 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When the P30 to P33 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 3 (PU3). This port can also be used for external interrupt request input and timer I/O. Reset signal generation sets port 3 to input mode. Figures 5-12 and 5-13 show block diagrams of port 3. Cautions 1. In the product with an on-chip debug function (PD78F0547D), be sure to pull the P31/INTP2/OCD1ANote pin down before a reset release, to prevent malfunction. 2. For products without an on-chip debug function (other than the PD78F0547D) and having a product rank of "I", "K", or "E", and for the product with an on-chip debug function (PD78F0547D), connect P31/INTP2/OCD1ANote as follows when writing the flash memory with a flash programmer. * P31/INTP2/OCD1ANote: Connect to EVSS via a resistor (10 k: recommended). The above connection is not necessary when writing the flash memory by means of self programming. Note OCD1A is provided to the PD78F0547D only. Remarks 1. For the product ranks, consult an NEC Electronics sales representative. 2. Only for the PD78F0547D, P31 and P32 can be used as on-chip debug mode setting pins (OCD1A, OCD1B) when the on-chip debug function is used. (PD78F0547D ONLY). For how to connect an in-circuit emulator supporting on-chip debugging (QB-78K0MINI), see CHAPTER 28 ON-CHIP DEBUG FUNCTION User's Manual U17397EJ4V0UD 107 CHAPTER 5 PORT FUNCTIONS www..com Figure 5-12. Block Diagram of P30 to P32 EVDD WRPU PU3 PU30 to PU32 P-ch Alternate function RD Internal bus Selector WRPORT P3 Output latch (P30 to P32) WRPM PM3 PM30 to PM32 P30/INTP1, P31/INTP2/OCD1ANote, P32/INTP3/OCD1BNote P3: PU3: PM3: RD: Port register 3 Pull-up resistor option register 3 Port mode register 3 Read signal WRxx: Write signal Note PD78F0547D only 108 User's Manual U17397EJ4V0UD CHAPTER 5 PORT FUNCTIONS www..com Figure 5-13. Block Diagram of P33 EVDD WRPU PU3 PU33 P-ch Alternate function RD Internal bus WRPORT P3 Output latch (P33) WRPM PM3 PM33 P33/INTP4/TI51/TO51 Alternate function P3: PU3: PM3: RD: Port register 3 Pull-up resistor option register 3 Port mode register 3 Read signal WRxx: Write signal Selector User's Manual U17397EJ4V0UD 109 CHAPTER 5 PORT FUNCTIONS www..com 5.2.5 Port 4 Port 4 is an 8-bit I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (PM4). When the P40 to P47 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 4 (PU4). Reset signal generation sets port 4 to input mode. Figure 5-14 shows a block diagram of port 4. Figure 5-14. Block Diagram of P40 to P47 EVDD WRPU PU4 PU40 to PU47 P-ch RD Internal bus Selector WRPORT P4 Output latch (P40 to P47) P40 to P47 WRPM PM4 PM40 to PM47 P4: PU4: PM4: RD: Port register 4 Pull-up resistor option register 4 Port mode register 4 Read signal WRxx: Write signal 110 User's Manual U17397EJ4V0UD CHAPTER 5 PORT FUNCTIONS www..com 5.2.6 Port 5 Port 5 is an 8-bit I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (PM5). When the P50 to P57 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 5 (PU5). Reset signal generation sets port 5 to input mode. Figure 5-15 shows a block diagram of port 5. Figure 5-15. Block Diagram of P50 to P57 EVDD WRPU PU5 PU50 to PU57 P-ch RD Internal bus Selector WRPORT P5 Output latch (P50 to P57) P50 to P57 WRPM PM5 PM50 to PM57 P5: PU5: PM5: RD: Port register 5 Pull-up resistor option register 5 Port mode register 5 Read signal WRxx: Write signal User's Manual U17397EJ4V0UD 111 CHAPTER 5 PORT FUNCTIONS www..com 5.2.7 Port 6 Port 6 is an 8-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). When the P64 to P67 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 6 (PU6). The output of the P60 to P63 pins is N-ch open-drain output (6 V tolerance). This port can also be used for serial interface data I/O, clock I/O, and external clock input. Reset signal generation sets port 6 to input mode. Figures 5-16 to 5-19 show block diagrams of port 6. Remark When using P62/EXSCL0 as an external clock input pin of the serial interface, input a clock of 6.4 MHz to it. Figure 5-16. Block Diagram of P60 and P61 Alternate function RD Selector WRPORT Internal bus P6 Output latch (P60, P61) WRPM PM6 PM60, PM61 P60/SCL0, P61/SDA0 Alternate function P6: PM6: RD: Port register 6 Port mode register 6 Read signal WRxx: Write signal 112 User's Manual U17397EJ4V0UD CHAPTER 5 PORT FUNCTIONS www..com Figure 5-17. Block Diagram of P62 Alternate function RD Internal bus WRPORT P6 Output latch (P62) WRPM PM6 PM62 P62/EXSCL0 P6: PM6: RD: Port register 6 Port mode register 6 Read signal WRxx: Write signal Figure 5-18. Block Diagram of P63 RD Selector Internal bus WRPORT P6 Output latch (P63) WRPM PM6 PM63 P63 P6: PM6: RD: Port register 6 Port mode register 6 Read signal WRxx: Write signal Selector User's Manual U17397EJ4V0UD 113 CHAPTER 5 PORT FUNCTIONS www..com Figure 5-19. Block Diagram of P64 to P67 EVDD WRPU PU6 PU64 to PU67 P-ch RD Internal bus WRPORT P6 Output latch (P64 to P67) WRPM PM6 PM64 to PM67 P64 to P67 P6: PM6: RD: Port register 6 Port mode register 6 Read signal WRxx: Write signal 114 User's Manual U17397EJ4V0UD Selector CHAPTER 5 PORT FUNCTIONS www..com 5.2.8 Port 7 Port 7 is an 8-bit I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (PM7). When the P70 to P77 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 7 (PU7). This port can also be used for key return input. Reset signal generation sets port 7 to input mode. Figure 5-20 shows a block diagram of port 7. Figure 5-20. Block Diagram of P70 to P77 EVDD WRPU PU7 PU70 to PU77 P-ch Alternate function RD Internal bus WRPORT P7 Output latch (P70 to P77) WRPM PM7 PM70 to PM77 P70/KR0 to P77/KR7 P7: PU7: PM7: RD: Port register 7 Pull-up resistor option register 7 Port mode register 7 Read signal WRxx: Write signal Selector User's Manual U17397EJ4V0UD 115 CHAPTER 5 PORT FUNCTIONS www..com 5.2.9 Port 12 Port 12 is a 5-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When used as an input port only for P120, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12). This port can also be used as pins for external interrupt request input, potential input for external low-voltage detection, connecting resonator for main system clock, connecting resonator for subsystem clock, external clock input for main system clock, and external clock input for subsystem clock. Reset signal generation sets port 12 to input mode. Figures 5-21 and 5-22 show block diagrams of port 12. Cautions 1. When using the P121 to P124 pins to connect a resonator for the main system clock (X1, X2) or subsystem clock (XT1, XT2), or to input an external clock for the main system clock (EXCLK) or subsystem clock (EXCLKS), the X1 oscillation mode, XT1 oscillation mode, or external clock input mode must be set by using the clock operation mode select register (OSCCTL) (for details, see 6.3 (1) Clock operation mode select register (OSCCTL) and (3) Setting of operation mode for subsystem clock pin). The reset value of OSCCTL is 00H (all of the P121 to P124 pins are I/O port pins). At this time, setting of the PM121 to PM124 and P121 to P124 pins is not necessary. 2. For products without an on-chip debug function (other than the PD78F0547D) and having a product rank of "I", "K", or "E", and for the product with an on-chip debug function (PD78F0547D), connect P121/X1/OCD0ANote as follows when writing the flash memory with a flash programmer. * P121/X1/OCD0ANote: When using this pin as a port, connect it to VSS via a resistor (10 k: recommended) (in the input mode) or leave it open (in the output mode). The above connection is not necessary when writing the flash memory by means of self programming. Note OCD0A is provided to the PD78F0547D only. Remarks 1. For the product ranks, consult an NEC Electronics sales representative. 2. Only for the PD78F0547D, P31 and P32 can be used as on-chip debug mode setting pins (OCD1A, OCD1B) when the on-chip debug function is used. (PD78F0547D ONLY). For how to connect an in-circuit emulator supporting on-chip debugging (QB-78K0MINI), see CHAPTER 28 ON-CHIP DEBUG FUNCTION 116 User's Manual U17397EJ4V0UD CHAPTER 5 PORT FUNCTIONS www..com Figure 5-21. Block Diagram of P120 EVDD WRPU PU12 PU120 P-ch Alternate function RD Internal bus WRPORT P12 Output latch (P120) WRPM PM12 PM120 P120/INTP0/EXLVI P12: PU12: PM12: RD: Port register 12 Pull-up resistor option register 12 Port mode register 12 Read signal WRxx: Write signal Selector User's Manual U17397EJ4V0UD 117 CHAPTER 5 PORT FUNCTIONS www..com Figure 5-22. Block Diagram of P121 to P124 OSCCTL OSCSEL/ OSCSELS RD WRPORT P12 Output latch (P122/P124) WRPM PM12 PM122/PM124 P122/X2/EXCLK/OCD0BNote, P124/XT2/EXCLKS OSCCTL OSCSEL/ OSCSELS Internal bus Selector OSCCTL EXCLK, OSCSEL/ EXCLKS, OSCSELS RD WRPORT P12 Output latch (P121/P123) WRPM PM12 PM121/PM123 P121/X1/OCD0ANote, P123/XT1 OSCCTL OSCSEL/ OSCSELS P12: PU12: PM12: RD: WRxx: Port register 12 Pull-up resistor option register 12 Port mode register 12 Read signal Write signal OSCCTL: Clock operation mode select register Note PD78F0547D only 118 Selector User's Manual U17397EJ4V0UD CHAPTER 5 PORT FUNCTIONS www..com 5.2.10 Port 13 Port 13 is a 1-bit output-only port. Figure 5-23 shows a block diagram of port 13. Figure 5-23. Block Diagram of P130 RD Internal bus WRPORT P13 Output latch (P130) P130 P13: RD: Port register 13 Read signal WRxx: Write signal Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected, the output signal of P130 can be dummy-output as the CPU reset signal. Reset signal P130 Set by software User's Manual U17397EJ4V0UD 119 CHAPTER 5 PORT FUNCTIONS www..com 5.2.11 Port 14 Port 14 is a 6-bit I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units using port mode register 14 (PM14). When the P140 to P145 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 14 (PU14). This port can also be used for external interrupt request input, buzzer output, clock output, serial interface data I/O, clock I/O, busy input, and strobe output. Reset signal generation sets port 14 to input mode. Figures 5-24 to 5-27 shows a block diagram of port 14. Figure 5-24. Block Diagram of P140 and P141 EVDD WRPU PU14 PU140, PU141 P-ch Alternate function RD Selector WRPORT P14 Output latch (P140, P141) WRPM PM14 PM140, PM141 P140/PCL/INTP6, P141/BUZ/BUSY0/INTP7 Alternate function Internal bus P14: PU14: PM14: RD: Port register 14 Pull-up resistor option register 14 Port mode register 14 Read signal WRxx: Write signal 120 User's Manual U17397EJ4V0UD CHAPTER 5 PORT FUNCTIONS www..com Figure 5-25. Block Diagram of P142 EVDD WRPU PU14 PU142 P-ch Alternate function RD Internal bus WRPORT P14 Output latch (P142) WRPM PM14 PM142 P142/SCKA0 Alternate function P14: PU14: PM14: RD: Port register 14 Pull-up resistor option register 14 Port mode register 14 Read signal WRxx: Write signal Selector User's Manual U17397EJ4V0UD 121 CHAPTER 5 PORT FUNCTIONS www..com Figure 5-26. Block Diagram of P143 EVDD WRPU PU14 PU143 P-ch Alternate function RD Internal bus Selector WRPORT P14 Output latch (P143) WRPM PM14 PM143 P143/SIA0 P14: PU14: PM14: RD: Port register 14 Pull-up resistor option register 14 Port mode register 14 Read signal WRxx: Write signal 122 User's Manual U17397EJ4V0UD CHAPTER 5 PORT FUNCTIONS www..com Figure 5-27. Block Diagram of P144 and P145 EVDD WRPU PU14 PU144, PU145 RD P-ch Internal bus WRPORT P14 Output latch (P144, P145) WRPM PM14 PM144, PM145 P144/SOA0, P145/STB0 Alternate function P14: PU14: PM14: RD: Port register 14 Pull-up resistor option register 14 Port mode register 14 Read signal WRxx: Write signal Selector User's Manual U17397EJ4V0UD 123 CHAPTER 5 PORT FUNCTIONS www..com 5.3 Registers Controlling Port Function Port functions are controlled by the following four types of registers. * Port mode registers (PM0 to PM7, PM12, PM14) * Port registers (P0 to P7, P12 to P14) * Pull-up resistor option registers (PU0, PU1, PU3 to PU7, PU12, PU14) * A/D port configuration register (ADPC) (1) Port mode registers (PM0 to PM7, PM12, and PM14) These registers specify input or output mode for the port in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. When port pins are used as alternate-function pins, set the port mode register by referencing 5.5 Settings of Port Mode Register and Output Latch When Using Alternate Function. 124 User's Manual U17397EJ4V0UD CHAPTER 5 PORT FUNCTIONS www..com Figure 5-28. Format of Port Mode Register Symbol PM0 7 1 6 PM06 5 PM05 4 PM04 3 PM03 2 PM02 1 PM01 0 PM00 Address FF20H After reset FFH R/W R/W PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FF21H FFH R/W PM2 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 FF22H FFH R/W PM3 1 1 1 1 PM33 PM32 PM31 PM30 FF23H FFH R/W PM4 PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40 FF24H FFH R/W PM5 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 FF25H FFH R/W PM6 PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60 FF26H FFH R/W PM7 PM77 PM76 PM75 PM74 PM73 PM72 PM71 PM70 FF27H FFH R/W PM12 1 1 1 PM124 PM123 PM122 PM121 PM120 FF2CH FFH R/W PM14 1 1 PM145 PM144 PM143 PM142 PM141 PM140 FF2EH FFH R/W PMmn Pmn pin I/O mode selection (m = 0 to 7, 12, 14; n = 0 to 7) 0 1 Output mode (output buffer on) Input mode (output buffer off) Caution Be sure to set bit 7 of PM0, bits 4 to 7 of PM3, bits 5 to 7 of PM12, and bits 6 and 7 of PM14 to "1". User's Manual U17397EJ4V0UD 125 CHAPTER 5 PORT FUNCTIONS www..com (2) Port registers (P0 to P7, P12 to P14) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is read. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 5-29. Format of Port Register Symbol P0 7 0 6 P06 5 P05 4 P04 3 P03 2 P02 1 P01 0 P00 Address FF00H After reset 00H (output latch) R/W R/W P1 P17 P16 P15 P14 P13 P12 P11 P10 FF01H 00H (output latch) R/W P2 P27 P26 P25 P24 P23 P22 P21 P20 FF02H 00H (output latch) R/W P3 0 0 0 0 P33 P32 P31 P30 FF03H 00H (output latch) R/W P4 P47 P46 P45 P44 P43 P42 P41 P40 FF04H 00H (output latch) R/W P5 P57 P56 P55 P54 P53 P52 P51 P50 FF05H 00H (output latch) R/W P6 P67 P66 P65 P64 P63 P62 P61 P60 FF06H 00H (output latch) R/W P7 P77 P76 P75 P74 P73 P72 P71 P70 FF07H 00H (output latch) R/W P12 0 0 0 P124Note P123Note P122Note P121Note P120 FF0CH 00H (output latch) R/W P13 0 0 0 0 0 0 0 P130 FF0DH 00H (output latch) R/W P14 0 0 P145 P144 P143 P142 P141 P140 FF0EH 00H (output latch) R/W Pmn m = 0 to 7, 12 to 14; n = 0 to 7 Output data control (in output mode) Input data read (in input mode) Input low level Input high level 0 1 Output 0 Output 1 Note "0" is always read from the output latch of P121 to P124 if the pin is in the external clock input mode. 126 User's Manual U17397EJ4V0UD CHAPTER 5 PORT FUNCTIONS www..com (3) Pull-up resistor option registers (PU0, PU1, PU3 to PU7, PU12, and PU14) These registers specify whether the on-chip pull-up resistors of P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, or P140 to P145 are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified in PU0, PU1, PU3 to PU7, PU12, and PU14. On-chip pull-up resistors cannot be connected to bits set to output mode and bits used as alternate-function output pins, regardless of the settings of PU0, PU1, PU3 to PU7, PU12, and PU14. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 5-30. Format of Pull-up Resistor Option Register Symbol PU0 7 0 6 PU06 5 PU05 4 PU04 3 PU03 2 PU02 1 PU01 0 PU00 Address FF30H After reset 00H R/W R/W PU1 PU17 PU16 PU15 PU14 PU13 PU12 PU11 PU10 FF31H 00H R/W PU3 0 0 0 0 PU33 PU32 PU31 PU30 FF33H 00H R/W PU4 PU47 PU46 PU45 PU44 PU43 PU42 PU41 PU40 FF34H 00H R/W PU5 PU57 PU56 PU55 PU54 PU53 PU52 PU51 PU50 FF35H 00H R/W PU6 PU67 PU66 PU65 PU64 0 0 0 0 FF36H 00H R/W PU7 PU77 PU76 PU75 PU74 PU73 PU72 PU71 PU70 FF37H 00H R/W PU12 0 0 0 0 0 0 0 PU120 FF3CH 00H R/W PU14 0 0 PU145 PU144 PU143 PU142 PU141 PU140 FF3EH 00H R/W PUmn Pmn pin on-chip pull-up resistor selection (m = 0, 1, 3 to 7, 12, 14; n = 0 to 7) 0 1 On-chip pull-up resistor not connected On-chip pull-up resistor connected User's Manual U17397EJ4V0UD 127 CHAPTER 5 PORT FUNCTIONS www..com (4) A/D port configuration register (ADPC) This register switches the P20/ANI0 to P27/ANI7 pins to digital I/O of port or analog input of A/D converter. ADPC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 5-31. Format of A/D Port Configuration Register (ADPC) Address: FF2FH Symbol ADPC 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 ADPC3 2 ADPC2 1 ADPC1 0 ADPC0 ADPC3 ADPC2 ADPC1 ADPC0 Digital I/O (D)/analog input (A) switching P27/ P26/ P25/ P24/ P23/ P22/ P21/ P20/ ANI7 ANI6 ANI5 ANI4 ANI3 ANI2 ANI1 ANI0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 A A A A A A A A D A A A A A A A D D A A A A A A D D D A A A A A D D D D A A A A D D D D D A A A D D D D D D A A D D D D D D D A D D D D D D D D Other than above Setting prohibited Cautions 1. Set the channel used for A/D conversion to the input mode by using port mode register 2 (PM2). 2. If data is written to ADPC, a wait cycle is generated. Do not write data to ADPC when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 34 CAUTIONS FOR WAIT. 128 User's Manual U17397EJ4V0UD CHAPTER 5 PORT FUNCTIONS www..com 5.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 5.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared when a reset signal is generated. (2) Input mode A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared when a reset signal is generated. 5.4.2 Reading from I/O port (1) Output mode The output latch contents are read by a transfer instruction. The output latch contents do not change. (2) Input mode The pin status is read by a transfer instruction. The output latch contents do not change. 5.4.3 Operations on I/O port (1) Output mode An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared when a reset signal is generated. (2) Input mode The pin level is read and an operation is performed on its contents. The result of the operation is written to the output latch, but since the output buffer is off, the pin status does not change. The data of the output latch is cleared when a reset signal is generated. 5.5 Settings of Port Mode Register and Output Latch When Using Alternate Function To use the alternate function of a port pin, set the port mode register and output latch as shown in Table 5-5. User's Manual U17397EJ4V0UD 129 CHAPTER 5 PORT FUNCTIONS www..com Table 5-5. Settings of Port Mode Register and Output Latch When Using Alternate Function (1/2) Pin Name Alternate Function Function Name P00 P01 TI000 TI010 TO00 P02 P03 P04 SO11 SI11 SCK11 I/O Input Input Output Output Input Input Output P05 SSI11 TI001 P06 TI011 TO01 P10 SCK10 Input Input Input Output Input Output TxD0 P11 SI10 RxD0 P12 P13 P14 P15 P16 SO10 TxD6 RxD6 TOH0 TOH1 INTP5 P17 TI50 TO50 P20 to P27 P30 to P32 P33 Note 1 PMxx Pxx 1 1 0 0 1 1 0 1 1 1 0 1 0 0 1 1 0 0 1 0 0 1 1 0 1 1 1 1 0 0 0 1 1 1 1 - x x x 0 0 x x 1 x x x 0 x 1 1 x x 0 1 x 0 0 x x 0 x x x x 0 0 0 x x x x x Output Input Input Output Output Input Output Output Input Input Output Note 1 ANI0 to ANI7 Input Input Input Input Output I/O I/O Input Input Input Input INTP1 to INTP3 INTP4 TI51 TO51 P60 P61 P62 P70 to P77 P120 SCL0 SDA0 EXSCL0 KR0 to KR7 INTP0 EXLVI P121 X1 Note 2 Remark x: Pxx: Don't care Port output latch PMxx: Port mode register (Notes 1 and 2 are listed on the next page.) 130 User's Manual U17397EJ4V0UD CHAPTER 5 PORT FUNCTIONS www..com Table 5-5. Settings of Port Mode Register and Output Latch When Using Alternate Function (2/2) Pin Name Alternate Function Function Name P122 X2 Note 2 PMxx I/O - x x - - x x x 0 1 0 1 1 1 0 1 0 0 Pxx x x x x x 0 x 0 x x x 1 x 0 0 EXCLK P123 P124 XT1 XT2 Note 2 Input Note 2 Note 2 EXCLKS P140 PCL INTP6 P141 BUZ INTP7 BUSY0 P142 SCKA0 Note 2 Input Output Input Output Input Input Input Output P143 P144 P145 SIA0 SOA0 STB0 Input Output Output Remarks 1. x: Pxx: Don't care Port output latch For how to connect an in-circuit ON-CHIP DEBUG PMxx: Port mode register 2. Only for the PD78F0547D, X1, X2, P31, and P32 can be used as on-chip debug mode setting pins (OCD1A, OCD1B) when the on-chip debug function is used. FUNCTION (PD78F0547D ONLY). Notes 1. The function of the ANI0/P20 to ANI7/P27 pins can be selected by using the A/D port configuration register (ADPC), the analog input channel specification register (ADS), and PM2. Table 5-6. Setting Functions of ANI0/P20 to ANI7/P27 Pins ADPC Analog input selection PM2 Input mode ADS Selects ANI. Does not select ANI. Output mode Selects ANI. Does not select ANI. Digital I/O selection Input mode Output mode - - Digital input Digital output ANI0/P20 to ANI7/P27 Pins Analog input (to be converted) Analog input (not to be converted) Setting prohibited emulator supporting on-chip debugging (QB-78K0MINI), see CHAPTER 28 2. When using the P121 to P124 pins to connect a resonator for the main system clock (X1, X2) or subsystem clock (XT1, XT2), or to input an external clock for the main system clock (EXCLK) or subsystem clock (EXCLKS), the X1 oscillation mode, XT1 oscillation mode, or external clock input mode must be set by using the clock operation mode select register (OSCCTL) (for details, see 6.3 (1) Clock operation mode select register (OSCCTL) and (3) Setting of operation mode for subsystem clock pin). The reset value of OSCCTL is 00H (all of the P121 to P124 are I/O port pins). At this time, setting of PM121 to PM124 and P121 to P124 is not necessary. User's Manual U17397EJ4V0UD 131 CHAPTER 5 PORT FUNCTIONS www..com 5.6 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit. Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode. 1-bit manipulation instruction (set1 P1.0) is executed for P10 bit. P10 Low-level output P11 to P17 Pin status: High level Port 1 output latch 0 0 0 0 0 0 0 0 P10 Low-level output P11 to P17 Pin status: High level Port 1 output latch 1 1 1 1 1 1 1 1 1-bit manipulation instruction for P10 bit <1> Port register 1 (P1) is read in 8-bit units. * In the case of P10, an output port, the value of the port output latch (0) is read. * In the case of P11 to P17, input ports, the pin status (1) is read. <2> Set the P10 bit to 1. <3> Write the results of <2> to the output latch of port register 1 (P1) in 8-bit units. 132 User's Manual U17397EJ4V0UD www..com CHAPTER 6 CLOCK GENERATOR 6.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three kinds of system clocks and clock oscillators are selectable. (1) Main system clock <1> X1 oscillator This circuit oscillates a clock of fX = 1 to 20 MHz by connecting a resonator to X1 and X2. Oscillation can be stopped by executing the STOP instruction or using the main OSC control register (MOC). <2> Internal high-speed oscillator This circuit oscillates a clock of fRH = 8 MHz (TYP.). After a reset release, the CPU always starts operating with this internal high-speed oscillation clock. Oscillation can be stopped by executing the STOP instruction or using the internal oscillation mode register (RCM). An external main system clock (fEXCLK = 1 to 20 MHz) can also be supplied from the EXCLK/X2/P122 pin. An external main system clock input can be disabled by executing the STOP instruction or using RCM. As the main system clock, a high-speed system clock (X1 clock or external main system clock) or internal highspeed oscillation clock can be selected by using the main clock mode register (MCM). (2) Subsystem clock * Subsystem clock oscillator This circuit oscillates at a frequency of fXT = 32.768 kHz by connecting a 32.768 kHz resonator across XT1 and XT2. Oscillation can be stopped by using the processor clock control register (PCC) and clock operation mode select register (OSCCTL). An external subsystem clock (fEXCLKS = 32.768 kHz) can also be supplied from the EXCLKS/XT2/P124 pin. An external subsystem clock input can be disabled by setting PCC and OSCCTL. Remarks 1. fX: 2. fRH: 3. fEXCLK: 4. fXT: X1 clock oscillation frequency Internal high-speed oscillation clock frequency External main system clock frequency XT1 clock oscillation frequency 5. fEXCLKS: External subsystem clock frequency User's Manual U17397E4V0UD 133 CHAPTER 6 CLOCK GENERATOR www..com (3) Internal low-speed oscillation clock (clock for watchdog timer) * Internal low-speed oscillator This circuit oscillates a clock of fRL = 240 kHz (TYP.). After a reset release, the internal low-speed oscillation clock always starts operating. Oscillation can be stopped by using the internal oscillation mode register (RCM) when "internal low-speed oscillator can be stopped by software" is set by option byte. The internal low-speed oscillation clock cannot be used as the CPU clock. The following hardware operates with the internal low-speed oscillation clock. * Watchdog timer * TMH1 (when fRL, fRL/27, or fRL/29 is selected) Remark fRL: Internal low-speed oscillation clock frequency 6.2 Configuration of Clock Generator The clock generator includes the following hardware. Table 6-1. Configuration of Clock Generator Item Control registers Configuration Clock operation mode select register (OSCCTL) Processor clock control register (PCC) Internal oscillation mode register (RCM) Main OSC control register (MOC) Main clock mode register (MCM) Oscillation stabilization time counter status register (OSTC) Oscillation stabilization time select register (OSTS) X1 oscillator XT1 oscillator Internal high-speed oscillator Internal low-speed oscillator Oscillators 134 User's Manual U17397E4V0UD Internal bus Clock operation mode select register (OSCCTL) AMPH EXCLK OSCSEL Main OSC control register (MOC) MSTOP Main clock mode register (MCM) MCS Oscillation stabilization time select register (OSTS) OSTS2 OSTS1 OSTS0 3 Main clock mode register (MCM) XSEL MCM0 XTSTART CLS Processor clock control register (PCC) CSS PCC2 PCC1 PCC0 4 STOP X1 oscillation stabilization time counter Oscillation stabilization MOST MOST MOST MOST MOST time counter 11 13 14 15 16 status register (OSTC) To subsystem clock oscillator High-speed system clock oscillator X1/P121 Crystal/ceramic oscillation External input clock fX Peripheral hardware clock switch Peripheral hardware clock (fPRS) fXH CHAPTER 6 CLOCK GENERATOR Controller User's Manual U17397E4V0UD X2/EXCLK/ P122 fEXCLK Internal highfRH speed oscillator (8 MHz (TYP.)) Main system fXP clock switch fXP 2 Prescaler fXP 22 fXP 23 fXP 24 Selector CPU clock (fCPU) Subsystem clock oscillator XT1/P123 XT2/EXCLKS/ P124 Crystal oscillation External input clock fXT 1/2 fSUB 2 fSUB Watch timer, clock output Internal lowspeed oscillator fRL (240 kHz (TYP.)) Watchdog timer, 8-bit timer H1 fEXCLKS XTSTART EXCLKS OSCSELS RSTS LSRSTOP RSTOP Option byte 1: Cannot be stopped 0: Can be stopped Processor clock control register (PCC) Clock operation mode select register (OSCCTL) Internal bus Internal oscillation mode register (RCM) www..com 135 CHAPTER 6 CLOCK GENERATOR www..com Remarks 1. fX: 2. fRH: 3. fEXCLK: 4. fXH: 5. fXP: 6. fPRS: 7. fCPU: 8. fXT: 10. fSUB: 11. fRL: X1 clock oscillation frequency Internal high-speed oscillation clock frequency External main system clock frequency High-speed system clock frequency Main system clock frequency Peripheral hardware clock frequency CPU clock frequency XT1 clock oscillation frequency Subsystem clock frequency Internal low-speed oscillation clock frequency 9. fEXCLKS: External subsystem clock frequency 6.3 Registers Controlling Clock Generator The following seven registers are used to control the clock generator. * Clock operation mode select register (OSCCTL) * Processor clock control register (PCC) * Internal oscillation mode register (RCM) * Main OSC control register (MOC) * Main clock mode register (MCM) * Oscillation stabilization time counter status register (OSTC) * Oscillation stabilization time select register (OSTS) (1) Clock operation mode select register (OSCCTL) This register selects the operation modes of the high-speed system and subsystem clocks, and the gain of the on-chip oscillator. OSCCTL can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. 136 User's Manual U17397E4V0UD CHAPTER 6 CLOCK GENERATOR www..com Figure 6-2. Format of Clock Operation Mode Select Register (OSCCTL) Address: FF9FH Symbol OSCCTL After reset: 00H <7> EXCLK EXCLK 0 0 1 1 <6> OSCSEL OSCSEL 0 1 0 1 R/W <5> EXCLKS Note <4> OSCSELS Note 3 0 P121/X1 pin I/O port 2 0 1 0 <0> AMPH High-speed system clock pin operation mode I/O port mode X1 oscillation mode I/O port mode External clock input mode P122/X2/EXCLK pin Crystal/ceramic resonator connection I/O port I/O port External clock input AMPH 0 1 1 MHz fXH 10 MHz 10 MHz < fXH 20 MHz Operating frequency control Note EXCLKS and OSCSELS are used in combination with XTSTART (bit 6 of the processor clock control register (PCC)). See (3) Setting of operation mode for subsystem clock pin. Cautions 1. Be sure to set AMPH to 1 if the high-speed system clock oscillation frequency exceeds 10 MHz. 2. Set AMPH before setting the peripheral functions after a reset release. The value of AMPH can be changed only once after a reset release. When the high-speed system clock (X1 oscillation) is selected as the CPU clock, supply of the CPU User's Manual U17397E4V0UD 137 CHAPTER 6 CLOCK GENERATOR www..com (2) Processor clock control register (PCC) This register is used to select the CPU clock, the division ratio, and operation mode for subsystem clock. PCC is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PCC to 01H. Figure 6-3. Format of Processor Clock Control Register (PCC) Address: FFFBH Symbol PCC 7 0 CLS 0 1 CSS 0 Main system clock Subsystem clock PCC2 0 0 0 0 1 1 0 0 0 0 1 PCC1 0 0 1 1 0 0 0 1 1 0 PCC0 0 1 0 1 0 0 1 0 1 0 Setting prohibited fXP fXP/2 (default) fXP/2 fXP/2 fXP/2 2 3 After reset: 01H 6 XTSTART Note2 R/W Note 1 <5> CLS <4> CSS 3 0 CPU clock status 2 PCC2 1 PCC1 0 PCC0 CPU clock (fCPU) selection 4 fSUB/2 Other than above Notes 1. Bit 5 is read-only. 2. XTSTART is used in combination with EXCLKS and OSCSELS (bits 5 and 4 of the clock operation mode select register (OSCCTL)). See (3) subsystem clock pin. Caution Be sure to clear bits 3 and 7 to "0". Main system clock oscillation frequency Setting of operation mode for Remarks 1. fXP: 2. fSUB: Subsystem clock oscillation frequency The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/KF2. Therefore, the relationship between the CPU clock (fCPU) and the minimum instruction execution time is as shown in Table 6-2. 138 User's Manual U17397E4V0UD CHAPTER 6 CLOCK GENERATOR www..com Table 6-2. Relationship Between CPU Clock and Minimum Instruction Execution Time CPU Clock (fCPU) Minimum Instruction Execution Time: 2/fCPU Main System Clock High-Speed System Clock At 10 MHz Operation fXP fXP/2 fXP/2 fXP/2 fXP/2 2 3 4 Note Subsystem Clock Internal High-Speed Note Oscillation Clock At 8 MHz (TYP.) Operation 0.25 s (TYP.) 0.5 s (TYP.) 1.0 s (TYP.) 2.0 s (TYP.) 4.0 s (TYP.) - 122.1 s At 32.768 kHz Operation - - - - - At 20 MHz Operation 0.1 s 0.2 s 0.4 s 0.8 s 1.6 s - 0.2 s 0.4 s 0.8 s 1.6 s 3.2 s fSUB/2 Note The main clock mode register (MCM) is used to set the main system clock supplied to CPU clock (highspeed system clock/internal high-speed oscillation clock) (see Figure 6-6). (3) Setting of operation mode for subsystem clock pin The operation mode for the subsystem clock pin can be set by using bit 6 (XTSTART) of the processor clock control register (PCC) and bits 5 and 4 (EXCLKS, OSCSELS) of the clock operation mode select register (OSCCTL) in combination. Table 6-3. Setting of Operation Mode for Subsystem Clock Pin PCC Bit 6 XTSTART 0 0 0 0 1 OSCCTL Bit 5 EXCLKS 0 0 1 1 x Bit 4 OSCSELS 0 1 0 1 x I/O port mode XT1 oscillation mode I/O port mode External clock input mode XT1 oscillation mode I/O port Crystal resonator connection I/O port I/O port External clock input Subsystem Clock Pin Operation Mode P123/XT1 Pin P124/XT2/EXCLKS Pin Crystal resonator connection Caution Confirm that bit 5 (CLS) of the processor clock control register (PCC) is 0 (CPU is operating with main system clock) when changing the current values of XTSTART, EXCLKS, and OSCSELS. Remark x: don't care User's Manual U17397E4V0UD 139 CHAPTER 6 CLOCK GENERATOR www..com (4) Internal oscillation mode register (RCM) This register sets the operation mode of internal oscillator. RCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 80HNote 1. Figure 6-4. Format of Internal Oscillation Mode Register (RCM) Address: FFA0H Symbol RCM After reset: 80H <7> RSTS 6 0 Note 1 R/W 5 0 Note 2 4 0 3 0 2 0 <1> LSRSTOP <0> RSTOP RSTS 0 1 Status of internal high-speed oscillator Waiting for accuracy stabilization of internal high-speed oscillator Stability operating of internal high-speed oscillator LSRSTOP 0 1 Internal low-speed oscillator oscillating/stopped Internal low-speed oscillator oscillating Internal low-speed oscillator stopped RSTOP 0 1 Internal high-speed oscillator oscillating/stopped Internal high-speed oscillator oscillating Internal high-speed oscillator stopped Notes 1. The value of this register is 00H immediately after a reset release but automatically changes to 80H after internal high-speed oscillator has been stabilized. 2. Bit 7 is read-only. Caution When setting RSTOP to 1, be sure to confirm that the CPU operates with a clock other than the internal high-speed oscillation clock. Specifically, set under either of the following conditions. * When MCS = 1 (when CPU operates with the high-speed system clock) * When CLS = 1 (when CPU operates with the subsystem clock) In addition, stop peripheral hardware that is operating on the internal high-speed oscillation clock before setting RSTOP to 1. 140 User's Manual U17397E4V0UD CHAPTER 6 CLOCK GENERATOR www..com (5) Main OSC control register (MOC) This register selects the operation mode of the high-speed system clock. This register is used to stop the X1 oscillator or to disable an external clock input from the EXCLK pin when the CPU operates with a clock other than the high-speed system clock. MOC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 80H. Figure 6-5. Format of Main OSC Control Register (MOC) Address: FFA2H Symbol MOC After reset: 80H <7> MSTOP 6 0 R/W 5 0 4 0 3 0 2 0 1 0 0 0 MSTOP Control of high-speed system clock operation X1 oscillation mode External clock input mode External clock from EXCLK pin is enabled External clock from EXCLK pin is disabled 0 1 X1 oscillator operating X1 oscillator stopped Cautions 1. When setting MSTOP to 1, be sure to confirm that the CPU operates with a clock other than the high-speed system clock. Specifically, set under either of the following conditions. * When MCS = 0 (when CPU operates with the internal high-speed oscillation clock) * When CLS = 1 (when CPU operates with the subsystem clock) In addition, stop peripheral hardware that is operating on the high-speed system clock before setting MSTOP to 1. 2. Do not clear MSTOP to 0 while bit 6 (OSCSEL) of the clock operation mode select register (OSCCTL) is 0 (I/O port mode). 3. The peripheral hardware cannot operate when the peripheral hardware clock is stopped. To resume the operation of the peripheral hardware after the peripheral hardware clock has been stopped, initialize the peripheral hardware. User's Manual U17397E4V0UD 141 CHAPTER 6 CLOCK GENERATOR www..com (6) Main clock mode register (MCM) This register selects the main system clock supplied to CPU clock and clock supplied to peripheral hardware clock. MCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 6-6. Format of Main Clock Mode Register (MCM) Address: FFA1H Symbol MCM 7 0 After reset: 00H 6 0 R/W Note 5 0 4 0 3 0 <2> XSEL <1> MCS <0> MCM0 XSEL MCM0 Selection of clock supplied to main system clock and peripheral hardware Main system clock (fXP) Peripheral hardware clock (fPRS) Internal high-speed oscillation clock (fRH) High-speed system clock (fXH) High-speed system clock (fXH) 0 0 1 1 0 1 0 1 Internal high-speed oscillation clock (fRH) MCS 0 1 Main system clock status Operates with internal high-speed oscillation clock Operates with high-speed system clock Note Bit 1 is read-only. Cautions 1. XSEL can be changed only once after a reset release. 2. A clock other than fPRS is supplied to the following peripheral functions regardless of the setting of XSEL and MCM0. * Watchdog timer (operates with internal low-speed oscillation clock) * When "fRL", "fRL/27", or "fRL/29" is selected as the count clock for 8-bit timer H1 (operates with internal low-speed oscillation clock) * Peripheral hardware selects the external clock as the clock source (Except when the external count clock of TM0n (n = 0, 1) is selected (TI00n pin valid edge)) 142 User's Manual U17397E4V0UD CHAPTER 6 CLOCK GENERATOR www..com (7) Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. When X1 clock oscillation starts with the internal high-speed oscillation clock or subsystem clock used as the CPU clock, the X1 clock oscillation stabilization time can be checked. OSTC can be read by a 1-bit or 8-bit memory manipulation instruction. When reset is released (reset by RESET input, POC, LVI, and WDT), the STOP instruction and MSTOP (bit 7 of MOC register) = 1 clear OSTC to 00H. Figure 6-7. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFA3H Symbol OSTC 7 0 After reset: 00H 6 0 R 5 0 4 MOST11 3 MOST13 2 MOST14 1 MOST15 0 MOST16 MOST11 MOST13 MOST14 MOST15 MOST16 Oscillation stabilization time status fX = 10 MHz fX = 20 MHz 1 1 1 1 1 0 1 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 0 0 1 2 /fX min. 2 /fX min. 2 /fX min. 2 /fX min. 2 /fX min. 16 15 14 13 11 204.8 s min. 102.4 s min. 819.2 s min. 409.6 s min. 1.64 ms min. 819.2 s min. 3.27 ms min. 1.64 ms min. 6.55 ms min. 3.27 ms min. Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and remain 1. 2. The oscillation stabilization time counter counts up to the oscillation stabilization time set by OSTS. If the STOP mode is entered and then released while the internal high-speed oscillation clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. 3. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts ("a" below). STOP mode release X1 pin voltage waveform a Remark fX: X1 clock oscillation frequency User's Manual U17397E4V0UD 143 CHAPTER 6 CLOCK GENERATOR www..com (8) Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP mode is released. When the internal high-speed oscillation clock is selected as the CPU clock, confirm with OSTC that the desired oscillation stabilization time has elapsed after the STOP mode is released. The oscillation stabilization time can be checked up to the time set using OSTC. OSTS can be set by an 8-bit memory manipulation instruction. Reset signal generation sets OSTS to 05H. Figure 6-8. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFA4H Symbol OSTS 7 0 After reset: 05H 6 0 R/W 5 0 4 0 3 0 2 OSTS2 1 OSTS1 0 OSTS0 OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection fX = 10 MHz fX = 20 MHz 102.4 s 409.6 s 819.2 s 1.64 ms 3.27 ms 0 0 0 1 1 0 1 1 0 0 Other than above 1 0 1 0 1 2 /fX 2 /fX 2 /fX 2 /fX 2 /fX Setting prohibited 16 15 14 13 11 204.8 s 819.2 s 1.64 ms 3.27 ms 6.55 ms Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS before executing the STOP instruction. 2. Do not change the value of the OSTS register during the X1 clock oscillation stabilization time. 3. The oscillation stabilization time counter counts up to the oscillation stabilization time set by OSTS. If the STOP mode is entered and then released while the internal high-speed oscillation clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. 4. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts ("a" below). STOP mode release X1 pin voltage waveform a Remark fX: X1 clock oscillation frequency User's Manual U17397E4V0UD 144 CHAPTER 6 CLOCK GENERATOR www..com 6.4 System Clock Oscillator 6.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (1 to 20 MHz) connected to the X1 and X2 pins. An external clock can also be input. In this case, input the clock signal to the EXCLK pin. Figure 6-9 shows an example of the external circuit of the X1 oscillator. Figure 6-9. Example of External Circuit of X1 Oscillator (a) Crystal or ceramic oscillation VSS X1 (b) External clock X2 Crystal resonator or ceramic resonator External clock EXCLK Cautions are listed on the next page. 6.4.2 XT1 oscillator The XT1 oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins. An external clock can also be input. In this case, input the clock signal to the EXCLKS pin. Figure 6-10 shows an example of the external circuit of the XT1 oscillator. Figure 6-10. Example of External Circuit of XT1 Oscillator (a) Crystal oscillation (b) External clock VSS XT1 32.768 kHz XT2 External clock EXCLKS Cautions are listed on the next page. User's Manual U17397E4V0UD 145 CHAPTER 6 CLOCK GENERATOR www..com Caution 1. When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the broken lines in the Figures 6-9 and 6-10 to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. Note that the XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption. Figure 6-11 shows examples of incorrect resonator connection. Figure 6-11. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORT VSS X1 X2 VSS X1 X2 Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side. 146 User's Manual U17397E4V0UD CHAPTER 6 CLOCK GENERATOR www..com Figure 6-11. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) VDD Pmn VSS X1 X2 VSS X1 X2 High current A B High current C (e) Signals are fetched VSS X1 X2 Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side. Caution 2. When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1, resulting in malfunctioning. User's Manual U17397E4V0UD 147 CHAPTER 6 CLOCK GENERATOR www..com 6.4.3 When subsystem clock is not used If it is not necessary to use the subsystem clock for low power consumption operations, or if not using the subsystem clock as an I/O port, set the XT1 and XT2 pins to I/O mode (OSCSELS = 0) and connect them as follows. Input (PM123/PM124 = 1): Independently connect to VDD or VSS via a resistor. Output (PM123/PM124 = 0): Leave open. Remark OSCSELS: Bit 4 of clock operation mode select register (OSCCTL) PM123, PM124: Bits 3 and 4 of port mode register 12 (PM12) 6.4.4 Internal high-speed oscillator The internal high-speed oscillator is incorporated in the 78K0/KF2. Oscillation can be controlled by the internal oscillation mode register (RCM). After a reset release, the internal high-speed oscillator automatically starts oscillation (8 MHz (TYP.)). 6.4.5 Internal low-speed oscillator The internal low-speed oscillator is incorporated in the 78K0/KF2. The internal low-speed oscillation clock is only used as the watchdog timer and the clock of 8-bit timer H1. The internal low-speed oscillation clock cannot be used as the CPU clock. "Can be stopped by software" or "Cannot be stopped" can be selected by the option byte. When "Can be stopped by software" is set, oscillation can be controlled by the internal oscillation mode register (RCM). After a reset release, the internal low-speed oscillator automatically starts oscillation, and the watchdog timer is driven (240 kHz (TYP.)) if the watchdog timer operation is enabled using the option byte. 6.4.6 Prescaler The prescaler generates various clocks by dividing the main system clock when the main system clock is selected as the clock to be supplied to the CPU. 148 User's Manual U17397E4V0UD CHAPTER 6 CLOCK GENERATOR www..com 6.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode (see Figure 6-1). * Main system clock fXP * High-speed system clock fXH X1 clock fX External main system clock fEXCLK * Internal high-speed oscillation clock fRH * Subsystem clock fSUB * XT1 clock fXT * External subsystem clock fEXCLKS * Internal low-speed oscillation clock fRL * CPU clock fCPU * Peripheral hardware clock fPRS The CPU starts operation when the internal high-speed oscillator starts outputting after a reset release in the 78K0/KF2, thus enabling the following. (1) Enhancement of security function When the X1 clock is set as the CPU clock by the default setting, the device cannot operate if the X1 clock is damaged or badly connected and therefore does not operate after reset is released. However, the start clock of the CPU is the internal high-speed oscillation clock, so the device can be started by the internal high-speed oscillation clock after a reset release. Consequently, the system can be safely shut down by performing a minimum operation, such as acknowledging a reset source by software or performing safety processing when there is a malfunction. (2) Improvement of performance Because the CPU can be started without waiting for the X1 clock oscillation stabilization time, the total performance can be improved. When the power supply voltage is turned on, the clock generator operation is shown in Figure 6-12. User's Manual U17397E4V0UD 149 CHAPTER 6 CLOCK GENERATOR www..com Figure 6-12. Clock Generator Operation When Power Supply Voltage Is Turned On (When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0)) Power supply voltage (VDD) 1.8 V 1.59 V (TYP.) 0.5 V/ms (MIN.) 0V Internal reset signal <1> <3> Waiting for voltage stabilization (1.93 to 5.39 ms) Reset processing (11 to 45 s) <5> Internal high-speed oscillation clock Switched by software High-speed system clock <5> Subsystem clock CPU clock <2> Internal high-speed oscillation clock (fRH) Note 1 <4> High-speed system clock (fXH) (when X1 oscillation selected) Subsystem clock (fSUB) (when XT1 oscillation selected) X1 clock oscillation stabilization time: 11 2 /fX to 216/fXNote 2 Starting X1 oscillation <4> is set by software. Starting XT1 oscillation is set by software. <1> When the power is turned on, an internal reset signal is generated by the power-on-clear (POC) circuit. <2> When the power supply voltage exceeds 1.59 V (TYP.), the reset is released and the internal high-speed oscillator automatically starts oscillation. <3> When the power supply voltage rises with a slope of 0.5 V/ms (MIN.), the CPU starts operation on the internal high-speed oscillation clock after the reset is released and after the stabilization times for the voltage of the power supply and regulator have elapsed, and then reset processing is performed. <4> Set the start of oscillation of the X1 or XT1 clock via software (see (1) in 6.6.1 Example of controlling highspeed system clock and (1) in 6.6.3 Example of controlling subsystem clock). <5> When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to stabilize, and then set switching via software (see (3) in 6.6.1 Example of controlling high-speed system clock and (3) in 6.6.3 Example of controlling subsystem clock). Notes 1. 2. The internal voltage stabilization time includes the oscillation accuracy stabilization time of the internal high-speed oscillation clock. When releasing a reset (above figure) or releasing STOP mode while the CPU is operating on the internal high-speed oscillation clock, confirm the oscillation stabilization time for the X1 clock using the oscillation stabilization time counter status register (OSTC). If the CPU operates on the high-speed system clock (X1 oscillation), set the oscillation stabilization time when releasing STOP mode using the oscillation stabilization time select register (OSTS). 150 User's Manual U17397E4V0UD CHAPTER 6 CLOCK GENERATOR www..com Cautions 1. If the voltage rises with a slope of less than 0.5 V/ms (MIN.) from power application until the voltage reaches 1.8 V, input a low level to the RESET pin from power application until the voltage reaches 1.8 V, or set the 2.7 V/1.59 V POC mode by using the option byte (POCMODE = 1) (see Figure 6-13). By doing so, the CPU operates with the same timing as <2> and thereafter in Figure 6-12 after reset release by the RESET pin. 2. It is not necessary to wait for the oscillation stabilization time when an external clock input from the EXCLK and EXCLKS pins is used. Remark While the microcontroller is operating, a clock that is not used as the CPU clock can be stopped via software settings. The internal high-speed oscillation clock and high-speed system clock can be Example of controlling high-speed stopped by executing the STOP instruction (see (4) in 6.6.1 6.6.3 Example of controlling subsystem clock). Figure 6-13. Clock Generator Operation When Power Supply Voltage Is Turned On (When 2.7 V/1.59 V POC Mode Is Set (Option Byte: POCMODE = 1)) 2.7 V (TYP.) Power supply voltage (VDD) system clock, (3) in 6.6.2 Example of controlling internal high-speed oscillation clock, and (4) in 0V Internal reset signal <1> <3> Reset processing (11 to 45 s) <5> CPU clock <2> Internal high-speed oscillation clock (fRH) High-speed system clock (fXH) (when X1 oscillation selected) Waiting for oscillation accuracy <4> stabilization (86 to 361 s) X1 clock oscillation stabilization time: 211/fX to 216/fXNote Starting X1 oscillation <4> is set by software. Internal high-speed oscillation clock Switched by software High-speed system clock <5> Subsystem clock Subsystem clock (fSUB) (when XT1 oscillation selected) Starting XT1 oscillation is set by software. <1> When the power is turned on, an internal reset signal is generated by the power-on-clear (POC) circuit. <2> When the power supply voltage exceeds 2.7 V (TYP.), the reset is released and the internal high-speed oscillator automatically starts oscillation. <3> After the reset is released and reset processing is performed, the CPU starts operation on the internal highspeed oscillation clock. <4> Set the start of oscillation of the X1 or XT1 clock via software (see (1) in 6.6.1 Example of controlling highspeed system clock and (1) in 6.6.3 Example of controlling subsystem clock). <5> When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to stabilize, and then set switching via software (see (3) in 6.6.1 Example of controlling high-speed system clock and (3) in 6.6.3 Example of controlling subsystem clock). User's Manual U17397E4V0UD 151 CHAPTER 6 CLOCK GENERATOR www..com Note When releasing a reset (above figure) or releasing STOP mode while the CPU is operating on the internal high-speed oscillation clock, confirm the oscillation stabilization time for the X1 clock using the oscillation stabilization time counter status register (OSTC). If the CPU operates on the high-speed system clock (X1 oscillation), set the oscillation stabilization time when releasing STOP mode using the oscillation stabilization time select register (OSTS). Cautions 1. A voltage oscillation stabilization time of 1.93 to 5.39 ms is required after the supply voltage reaches 1.59 V (TYP.). If the supply voltage rises from 1.59 V (TYP.) to 2.7 V (TYP.) within 1.93 ms, the power supply oscillation stabilization time of 0 to 5.39 ms is automatically generated before reset processing. 2. It is not necessary to wait for the oscillation stabilization time when an external clock input from the EXCLK and EXCLKS pins is used. Remark While the microcontroller is operating, a clock that is not used as the CPU clock can be stopped via software settings. The internal high-speed oscillation clock and high-speed system clock can be Example of controlling high-speed stopped by executing the STOP instruction (see (4) in 6.6.1 6.6.3 Example of controlling subsystem clock). system clock, (3) in 6.6.2 Example of controlling internal high-speed oscillation clock, and (4) in 152 User's Manual U17397E4V0UD CHAPTER 6 CLOCK GENERATOR www..com 6.6 Controlling Clock 6.6.1 Controlling high-speed system clock The following two types of high-speed system clocks are available. * X1 clock: Crystal/ceramic resonator is connected across the X1 and X2 pins. * External main system clock: External clock is input to the EXCLK pin. When the high-speed system clock is not used, the X1/P121 and X2/EXCLK/P122 pins can be used as I/O port pins. Caution The X1/P121 and X2/EXCLK/P122 pins are in the I/O port mode after a reset release. The following describes examples of setting procedures for the following cases. (1) When oscillating X1 clock (2) When using external main system clock (3) When using high-speed system clock as CPU clock and peripheral hardware clock (4) When stopping high-speed system clock (1) Example of setting procedure when oscillating the X1 clock <1> Setting frequency (OSCCTL register) Using AMPH, set the gain of the on-chip oscillator according to the frequency to be used. AMPH 0 1 Note Operating Frequency Control 1 MHz fXH 10 MHz 10 MHz < fXH 20 MHz Note Set AMPH before setting the peripheral functions after a reset release. The value of AMPH can be changed only once after a reset release. When AMPH is set to 1, the clock supply to the CPU is stopped for 4.06 to 16.12 s. Remark fXH: High-speed system clock oscillation frequency <2> Setting P121/X1 and P122/X2/EXCLK pins and selecting X1 clock or external clock (OSCCTL register) When EXCLK is cleared to 0 and OSCSEL is set to 1, the mode is switched from port mode to X1 oscillation mode. EXCLK 0 OSCSEL 1 Operation Mode of HighSpeed System Clock Pin X1 oscillation mode Crystal/ceramic resonator connection P121/X1 Pin P122/X2/EXCLK Pin <3> Controlling oscillation of X1 clock (MOC register) If MSTOP is cleared to 0, the X1 oscillator starts oscillating. <4> Waiting for the stabilization of the oscillation of X1 clock Check the OSTC register and wait for the necessary time. During the wait time, other software processing can be executed with the internal high-speed oscillation clock. Cautions 1. Do not change the value of EXCLK and OSCSEL while the X1 clock is operating. User's Manual U17397E4V0UD 153 CHAPTER 6 CLOCK GENERATOR www..com Cautions 2. Set the X1 clock after the supply voltage has reached the operable voltage of the clock to be used (see CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) or CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS, TARGET )). (2) Example of setting procedure when using the external main system clock <1> Setting frequency (OSCCTL register) Using AMPH, set the frequency to be used. AMPH 0 1 Note Operating Frequency Control 1 MHz fXH 10 MHz 10 MHz < fXH 20 MHz Note Set AMPH before setting the peripheral functions after a reset release. The value of AMPH can be changed only once after a reset release. The clock supply to the CPU is stopped for the duration of 160 external clocks after AMPH is set to 1. Remark fXH: High-speed system clock oscillation frequency <2> Setting P121/X1 and P122/X2/EXCLK pins and selecting operation mode (OSCCTL register) When EXCLK and OSCSEL are set to 1, the mode is switched from port mode to external clock input mode. EXCLK 1 OSCSEL 1 Operation Mode of HighSpeed System Clock Pin External clock input mode I/O port External clock input P121/X1 Pin P122/X2/EXCLK Pin <3> Controlling external main system clock input (MOC register) When MSTOP is cleared to 0, the input of the external main system clock is enabled. Cautions 1. Do not change the value of EXCLK and OSCSEL while the external main system clock is operating. 2. Set the external main system clock after the supply voltage has reached the operable voltage of the clock to be used (see CHAPTER 30 PRODUCTS, TARGET )). (3) Example of setting procedure when using high-speed system clock as CPU clock and peripheral hardware clock <1> Setting high-speed system clock oscillationNote (See 6.6.1 (1) Example of setting procedure when oscillating the X1 clock and (2) Example of setting procedure when using the external main system clock.) Note The setting of <1> is not necessary when high-speed system clock is already operating. ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) or CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE 154 User's Manual U17397E4V0UD CHAPTER 6 CLOCK GENERATOR www..com <2> Setting the high-speed system clock as the main system clock (MCM register) When XSEL and MCM0 are set to 1, the high-speed system clock is supplied as the main system clock and peripheral hardware clock. XSEL MCM0 Selection of Main System Clock and Clock Supplied to Peripheral Hardware Main System Clock (fXP) 1 1 High-speed system clock (fXH) Peripheral Hardware Clock (fPRS) High-speed system clock (fXH) Caution If the high-speed system clock is selected as the main system clock, a clock other than the high-speed system clock cannot be set as the peripheral hardware clock. <3> Setting the main system clock as the CPU clock and selecting the division ratio (PCC register) When CSS is cleared to 0, the main system clock is supplied to the CPU. To select the CPU clock division ratio, use PCC0, PCC1, and PCC2. CSS 0 PCC2 0 0 0 0 1 PCC1 0 0 1 1 0 Other than above PCC0 0 1 0 1 0 fXP fXP/2 (default) fXP/2 fXP/2 fXP/2 2 CPU Clock (fCPU) Selection 3 4 Setting prohibited (4) Example of setting procedure when stopping the high-speed system clock The high-speed system clock can be stopped in the following two ways. * Executing the STOP instruction and stopping the X1 oscillation (disabling clock input if the external clock is used) * Setting MSTOP to 1 and stopping the X1 oscillation (disabling clock input if the external clock is used) (a) To execute a STOP instruction <1> Setting to stop peripheral hardware Stop peripheral hardware that cannot be used in the STOP mode (for peripheral hardware that cannot be used in STOP mode, see CHAPTER 22 STANDBY FUNCTION). <2> Setting the X1 clock oscillation stabilization time after standby release When the CPU is operating on the X1 clock, set the value of the OSTS register before the STOP instruction is executed. <3> Executing the STOP instruction When the STOP instruction is executed, the system is placed in the STOP mode and X1 oscillation is stopped (the input of the external clock is disabled). User's Manual U17397E4V0UD 155 CHAPTER 6 CLOCK GENERATOR www..com (b) To stop X1 oscillation (disabling external clock input) by setting MSTOP to 1 <1> Confirming the CPU clock status (PCC and MCM registers) Confirm with CLS and MCS that the CPU is operating on a clock other than the high-speed system clock. When CLS = 0 and MCS = 1, the high-speed system clock is supplied to the CPU, so change the CPU clock to the subsystem clock or internal high-speed oscillation clock. CLS 0 0 1 MCS 0 1 x CPU Clock Status Internal high-speed oscillation clock High-speed system clock Subsystem clock <2> Stopping the high-speed system clock (MOC register) When MSTOP is set to 1, X1 oscillation is stopped (the input of the external clock is disabled). Caution Be sure to confirm that MCS = 0 or CLS = 1 when setting MSTOP to 1. In addition, stop peripheral hardware that is operating on the high-speed system clock. 6.6.2 Example of controlling internal high-speed oscillation clock The following describes examples of clock setting procedures for the following cases. (1) When restarting oscillation of the internal high-speed oscillation clock (2) When using internal high-speed oscillation clock as CPU clock, and internal high-speed oscillation clock or high-speed system clock as peripheral hardware clock (3) When stopping the internal high-speed oscillation clock (1) Example of setting procedure when restarting oscillation of the internal high-speed oscillation clockNote 1 <1> Setting restart of oscillation of the internal high-speed oscillation clock (RCM register) When RSTOP is cleared to 0, the internal high-speed oscillation clock starts operating. <2> Waiting for the oscillation accuracy stabilization time of internal high-speed oscillation clock (RCM register) Wait until RSTS is set to 1Note 2. Notes 1. After a reset release, the internal high-speed oscillator automatically starts oscillating and the internal high-speed oscillation clock is selected as the CPU clock. 2. This wait time is not necessary if high accuracy is not necessary for the CPU clock and peripheral hardware clock. (2) Example of setting procedure when using internal high-speed oscillation clock as CPU clock, and internal high-speed oscillation clock or high-speed system clock as peripheral hardware clock <1> * Restarting oscillation of the internal high-speed oscillation clockNote (See 6.6.2 (1) Example of setting procedure when restarting internal high-speed oscillation clock). * Oscillating the high-speed system clockNote (This setting is required when using the high-speed system clock as the peripheral hardware clock. See 6.6.1 (1) Example of setting procedure when oscillating the X1 clock and (2) Example of setting procedure when using the external main system clock.) 156 User's Manual U17397E4V0UD CHAPTER 6 CLOCK GENERATOR www..com Note The setting of <1> is not necessary when the internal high-speed oscillation clock or highspeed system clock is already operating. <2> Selecting the clock supplied as the main system clock and peripheral hardware clock (MCM register) Set the main system clock and peripheral hardware clock using XSEL and MCM0. XSEL MCM0 Selection of Main System Clock and Clock Supplied to Peripheral Hardware Main System Clock (fXP) 0 0 1 0 1 0 Internal high-speed oscillation clock (fRH) Peripheral Hardware Clock (fPRS) Internal high-speed oscillation clock (fRH) High-speed system clock (fXH) <3> Selecting the CPU clock division ratio (PCC register) When CSS is cleared to 0, the main system clock is supplied to the CPU. To select the CPU clock division ratio, use PCC0, PCC1, and PCC2. CSS 0 PCC2 0 0 0 0 1 PCC1 0 0 1 1 0 Other than above PCC0 0 1 0 1 0 fXP fXP/2 (default) fXP/2 fXP/2 fXP/2 2 3 CPU Clock (fCPU) Selection 4 Setting prohibited (3) Example of setting procedure when stopping the internal high-speed oscillation clock The internal high-speed oscillation clock can be stopped in the following two ways. * Executing the STOP instruction to set the STOP mode * Setting RSTOP to 1 and stopping the internal high-speed oscillation clock (a) To execute a STOP instruction <1> Setting of peripheral hardware Stop peripheral hardware that cannot be used in the STOP mode (for peripheral hardware that cannot be used in STOP mode, see CHAPTER 22 STANDBY FUNCTION). <2> Setting the X1 clock oscillation stabilization time after standby release When the CPU is operating on the X1 clock, set the value of the OSTS register before the STOP instruction is executed. <3> Executing the STOP instruction When the STOP instruction is executed, the system is placed in the STOP mode and internal highspeed oscillation clock is stopped. User's Manual U17397E4V0UD 157 CHAPTER 6 CLOCK GENERATOR www..com (b) To stop internal high-speed oscillation clock by setting RSTOP to 1 <1> Confirming the CPU clock status (PCC and MCM registers) Confirm with CLS and MCS that the CPU is operating on a clock other than the internal high-speed oscillation clock. When CLS = 0 and MCS = 0, the internal high-speed oscillation clock is supplied to the CPU, so change the CPU clock to the high-speed system clock or subsystem clock. CLS 0 0 1 MCS 0 1 x CPU Clock Status Internal high-speed oscillation clock High-speed system clock Subsystem clock <2> Stopping the internal high-speed oscillation clock (RCM register) When RSTOP is set to 1, internal high-speed oscillation clock is stopped. Caution Be sure to confirm that MCS = 1 or CLS = 1 when setting RSTOP to 1. In addition, stop peripheral hardware that is operating on the internal high-speed oscillation clock. 6.6.3 Example of controlling subsystem clock The following two types of subsystem clocks are available. * XT1 clock: Crystal/ceramic resonator is connected across the XT1 and XT2 pins. * External subsystem clock: External clock is input to the EXCLKS pin. When the subsystem clock is not used, the XT1/P123 and XT2/EXCLKS/P124 pins can be used as I/O port pins. Caution The XT1/P123 and XT2/EXCLKS/P124 pins are in the I/O port mode after a reset release. The following describes examples of setting procedures for the following cases. (1) When oscillating XT1 clock (2) When using external subsystem clock (3) When using subsystem clock as CPU clock (4) When stopping subsystem clock (1) Example of setting procedure when oscillating the XT1 clock <1> Setting XT1 and XT2 pins and selecting operation mode (PCC and OSCCTL registers) When XTSTART, EXCLKS, and OSCSELS are set as any of the following, the mode is switched from port mode to XT1 oscillation mode. XTSTART EXCLKS OSCSELS Operation Mode of Subsystem Clock Pin 0 1 0 x 1 x XT1 oscillation mode P123/XT1 Pin P124/XT2/ EXCLKS Pin Crystal/ceramic resonator connection Remark x: don't care <2> Waiting for the stabilization of the subsystem clock oscillation Wait for the oscillation stabilization time of the subsystem clock by software, using a timer function. Caution Do not change the value of XTSTART, EXCLKS, and OSCSELS while the subsystem clock is operating. 158 User's Manual U17397E4V0UD CHAPTER 6 CLOCK GENERATOR www..com (2) Example of setting procedure when using the external subsystem clock <1> Setting XT1 and XT2 pins, selecting XT1 clock/external clock and controlling oscillation (PCC and OSCCTL registers) When XTSTART is cleared to 0 and EXCLKS and OSCSELS are set to 1, the mode is switched from port mode to external clock input mode. In this case, input the external clock to the EXCLKS/XT2/P124 pins. XTSTART 0 EXCLKS 1 OSCSELS 1 Operation Mode of Subsystem Clock Pin External clock input mode P123/XT1 Pin I/O port P124/XT2/ EXCLKS Pin External clock input Caution Do not change the value of XTSTART, EXCLKS, and OSCSELS while the subsystem clock is operating. (3) Example of setting procedure when using the subsystem clock as the CPU clock <1> Setting subsystem clock oscillationNote (See 6.6.3 (1) Example of setting procedure when oscillating the XT1 clock and (2) Example of setting procedure when using the external subsystem clock.) Note The setting of <1> is not necessary when while the subsystem clock is operating. <2> Switching the CPU clock (PCC register) When CSS is set to 1, the subsystem clock is supplied to the CPU. CSS 1 PCC2 0 0 0 0 1 PCC1 0 0 1 1 0 Other than above PCC0 0 1 0 1 0 Setting prohibited fSUB/2 CPU Clock (fCPU) Selection (4) Example of setting procedure when stopping the subsystem clock <1> Confirming the CPU clock status (PCC and MCM registers) Confirm with CLS and MCS that the CPU is operating on a clock other than the subsystem clock. When CLS = 1, the subsystem clock is supplied to the CPU, so change the CPU clock to the internal high-speed oscillation clock or high-speed system clock. CLS 0 0 1 MCS 0 1 x CPU Clock Status Internal high-speed oscillation clock High-speed system clock Subsystem clock <2> Stopping the subsystem clock (OSCCTL register) When OSCSELS is cleared to 0, XT1 oscillation is stopped (the input of the external clock is disabled). Caution1. Be sure to confirm that CLS = 0 when clearing OSCSELS to 0. In addition, stop the watch timer if it is operating on the subsystem clock. 2. The subsystem clock oscillation cannot be stopped using the STOP instruction. User's Manual U17397E4V0UD 159 CHAPTER 6 CLOCK GENERATOR www..com 6.6.4 Example of controlling internal low-speed oscillation clock The internal low-speed oscillation clock cannot be used as the CPU clock. Only the following peripheral hardware can operate with this clock. * Watchdog timer * 8-bit timer H1 (if fRL is selected as the count clock) In addition, the following operation modes can be selected by the option byte. * Internal low-speed oscillator cannot be stopped * Internal low-speed oscillator can be stopped by software The internal low-speed oscillator automatically starts oscillation after a reset release, and the watchdog timer is driven (240 kHz (TYP.)) if the watchdog timer operation has been enabled by the option byte. (1) Example of setting procedure when stopping the internal low-speed oscillation clock <1> Setting LSRSTOP to 1 (RCM register) When LSRSTOP is set to 1, the internal low-speed oscillation clock is stopped. (2) Example of setting procedure when restarting oscillation of the internal low-speed oscillation clock <1> Clearing LSRSTOP to 0 (RCM register) When LSRSTOP is cleared to 0, the internal low-speed oscillation clock is restarted. Caution If "Internal low-speed oscillator cannot be stopped" is selected by the option byte, oscillation of the internal low-speed oscillation clock cannot be controlled. 6.6.5 Clocks supplied to CPU and peripheral hardware The following table shows the relation among the clocks supplied to the CPU and peripheral hardware, and setting of registers. Table 6-4. Clocks Supplied to CPU and Peripheral Hardware, and Register Setting Supplied Clock Clock Supplied to CPU Internal high-speed oscillation clock Internal high-speed oscillation clock X1 clock External main system clock X1 clock External main system clock Subsystem clock Internal high-speed oscillation clock X1 clock Clock Supplied to Peripheral Hardware 0 1 1 1 1 0 1 1 External main system clock 1 1 0 0 0 0 0 1 1 1 1 1 x 0 0 1 1 x 0 1 0 1 x 0 1 0 1 x 0 0 1 1 XSEL CSS MCM0 EXCLK Remarks 1. XSEL: 2. CSS: 3. MCM0: 5. x: Bit 2 of the main clock mode register (MCM) Bit 4 of the processor clock control register (PCC) Bit 0 of MCM don't care 4. EXCLK: Bit 7 of the clock operation mode select register (OSCCTL) 160 User's Manual U17397E4V0UD CHAPTER 6 CLOCK GENERATOR www..com 6.6.6 CPU clock status transition diagram Figure 6-14 shows the CPU clock status transition diagram of this product. Figure 6-14. CPU Clock Status Transition Diagram (When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0)) Internal low-speed oscillation: Woken up Internal high-speed oscillation: Woken up X1 oscillation/EXCLK input: Stops (I/O port mode) XT1 oscillation/EXCLKS input: Stops (I/O port mode) Power ON VDD < 1.59 V (TYP.) (A) Reset release VDD 1.59 V (TYP.) Internal low-speed oscillation: Operating Internal high-speed oscillation: Operating X1 oscillation/EXCLK input: Stops (I/O port mode) XT1 oscillation/EXCLKS input: Stops (I/O port mode) Internal low-speed oscillation: Operable Internal high-speed oscillation: Selectable by CPU X1 oscillation/EXCLK input: Selectable by CPU XT1 oscillation/EXCLKS input: Operating (D) Internal low-speed oscillation: Operable Internal high-speed oscillation: Operating X1 oscillation/EXCLK input: Selectable by CPU XT1 oscillation/EXCLKS input: Selectable by CPU (B) VDD 1.8 V (MIN.) CPU: Operating with internal highspeed oscillation (H) CPU: Internal highspeed oscillation STOP Internal low-speed oscillation: Operable Internal high-speed oscillation: Stops X1 oscillation/EXCLK input: Stops XT1 oscillation/EXCLKS input: Operable CPU: Operating with XT1 oscillation or EXCLKS input (E) (C) CPU: Operating with X1 oscillation or EXCLK input CPU: Internal highspeed oscillation HALT (G) CPU: XT1 oscillation/EXCLKS input HALT Internal low-speed oscillation: Operable Internal high-speed oscillation: Operable X1 oscillation/EXCLK input: Operable XT1 oscillation/EXCLKS input: Operating Internal low-speed oscillation: Operable Internal high-speed oscillation: Operating X1 oscillation/EXCLK input: Operable XT1 oscillation/EXCLKS input: Operable Internal low-speed oscillation: Operable Internal high-speed oscillation: Selectable by CPU X1 oscillation/EXCLK input: Operating XT1 oscillation/EXCLKS input: Selectable by CPU (I) (F) CPU: X1 oscillation/EXCLK input HALT Internal low-speed oscillation: Operable Internal high-speed oscillation: Operable X1 oscillation/EXCLK input: Operating XT1 oscillation/EXCLKS input: Operable CPU: X1 oscillation/EXCLK input STOP Internal low-speed oscillation: Operable Internal high-speed oscillation: Stops X1 oscillation/EXCLK input: Stops XT1 oscillation: Operable Remark In the 2.7 V/1.59 V POC mode (option byte: POCMODE = 1), the CPU clock status changes to (A) in the above figure when the supply voltage exceeds 2.7 V (TYP.), and to (B) after reset processing (11 to 45 s). User's Manual U17397E4V0UD 161 CHAPTER 6 CLOCK GENERATOR www..com Table 6-5 shows transition of the CPU clock and examples of setting the SFR registers. Table 6-5. CPU Clock Transition and SFR Register Setting Examples (1/4) (1) CPU operating with internal high-speed oscillation clock (B) after reset release (A) Status Transition (A) (B) SFR Register Setting SFR registers do not have to be set (default status after reset release). (2) CPU operating with high-speed system clock (C) after reset release (A) (The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (A) (B) (C) (X1 clock: 1 MHz fXH 10 MHz) (A) (B) (C) (external main clock: 1 MHz fXH 10 MHz) (A) (B) (C) (X1 clock: 10 MHz < fXH 20 MHz) (A) (B) (C) (external main clock: 10 MHz < fXH 20 MHz) 1 1 1 0 1 0 1 0 0 1 1 0 0 0 1 0 AMPH EXCLK OSCSEL MSTOP OSTC Register Must be checked Must not be checked XSEL MCM0 1 1 1 1 Must be checked Must not be checked 1 1 1 1 Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) or CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS, TARGET )). (3) CPU operating with subsystem clock (D) after reset release (A) (The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (A) (B) (D) (XT1 clock) 0 1 (A) (B) (D) (external subsystem clock) 0 0 x 1 1 x 1 Unnecessary 1 XTSTART EXCLKS OSCSELS Waiting for Oscillation Stabilization Necessary 1 CSS Remarks 1. (A) to (I) in Table 6-5 correspond to (A) to (I) in Figure 6-14. 2. EXCLK, OSCSEL, EXCLKS, OSCSELS, AMPH: Bits 7 to 4 and 0 of the clock operation mode select register (OSCCTL) MSTOP: XSEL, MCM0: x: Bit 7 of the main OSC control register (MOC) Bits 2 and 0 of the main clock mode register (MCM) Don't care XTSTART, CSS: Bits 6 and 4 of the processor clock control register (PCC) 162 User's Manual U17397E4V0UD CHAPTER 6 CLOCK GENERATOR www..com Table 6-5. CPU Clock Transition and SFR Register Setting Examples (2/4) (4) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (B) (C) (X1 clock: 1 MHz fXH 10 MHz) (B) (C) (external main clock: 1 MHz fXH 10 MHz) (B) (C) (X1 clock: 10 MHz < fXH 20 MHz) (B) (C) (external main clock: 10 MHz < fXH 20 MHz) 1 0 1 0 0 0 1 0 AMPH Note EXCLK OSCSEL MSTOP OSTC Register Must be checked XSEL Note MCM0 1 1 0 1 1 0 Must not be checked 1 1 Must be checked 1 1 1 1 1 0 Must not be checked 1 1 Unnecessary if these registers are already set Unnecessary if the CPU is operating with the high-speed system clock Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has already been set. Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) or CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS, TARGET )). (5) CPU clock changing from internal high-speed oscillation clock (B) to subsystem clock (D) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (B) (D) (XT1 clock) 0 1 (B) (D) (external subsystem clock) 0 0 x 1 1 x 1 Unnecessary 1 XTSTART EXCLKS OSCSELS Waiting for Oscillation Stabilization Necessary 1 CSS Unnecessary if the CPU is operating with the subsystem clock Remarks 1. (A) to (I) in Table 6-5 correspond to (A) to (I) in Figure 6-14. 2. EXCLK, OSCSEL, EXCLKS, OSCSELS, AMPH: Bits 7 to 4 and 0 of the clock operation mode select register (OSCCTL) MSTOP: XSEL, MCM0: x: Bit 7 of the main OSC control register (MOC) Bits 2 and 0 of the main clock mode register (MCM) Don't care XTSTART, CSS: Bits 6 and 4 of the processor clock control register (PCC) User's Manual U17397E4V0UD 163 CHAPTER 6 CLOCK GENERATOR www..com Table 6-5. CPU Clock Transition and SFR Register Setting Examples (3/4) (6) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (C) (B) 0 Confirm this flag is 1. 0 RSTOP RSTS MCM0 Unnecessary if the CPU is operating with the internal high-speed oscillation clock (7) CPU clock changing from high-speed system clock (C) to subsystem clock (D) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (C) (D) (XT1 clock) 0 1 (C) (D) (external subsystem clock) 0 0 x 1 1 x 1 Unnecessary 1 XTSTART EXCLKS OSCSELS Waiting for Oscillation Stabilization Necessary 1 CSS Unnecessary if the CPU is operating with the subsystem clock (8) CPU clock changing from subsystem clock (D) to internal high-speed oscillation clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (D) (B) 0 Confirm this flag is 1. Unnecessary if the CPU is operating with the internal high-speed oscillation clock Unnecessary if XSEL is 0 0 0 RSTOP RSTS MCM0 CSS Remarks 1. (A) to (I) in Table 6-5 correspond to (A) to (I) in Figure 6-14. 2. MCM0: RSTS, RSTOP: XTSTART, CSS: x: Bit 0 of the main clock mode register (MCM) Bits 7 and 0 of the internal oscillation mode register (RCM) Bits 6 and 4 of the processor clock control register (PCC) Don't care EXCLKS, OSCSELS: Bits 5 and 4 of the clock operation mode select register (OSCCTL) 164 User's Manual U17397E4V0UD CHAPTER 6 CLOCK GENERATOR www..com Table 6-5. CPU Clock Transition and SFR Register Setting Examples (4/4) (9) CPU clock changing from subsystem clock (D) to high-speed system clock (C) (Setting sequence of SFR registers) Setting Flag of SFR Register AMPH Status Transition (D) (C) (X1 clock: 1 MHz fXH 10 MHz) (D) (C) (external main clock: 1 MHz fXH 10 MHz (D) (C) (X1 clock: 10 MHz < fXH 20 MHz) (D) (C) (external main clock: 10 MHz < fXH 20 MHz) Unnecessary if these registers are already set 1 1 1 0 1 0 1 0 0 1 1 0 0 0 1 0 Note EXCLK OSCSEL MSTOP OSTC Register Must be checked Must not be checked XSEL Note MCM0 CSS 1 1 0 1 1 0 Must be checked Must not be checked 1 1 0 1 1 0 Unnecessary if the CPU is operating with the high-speed system clock Unnecessary if this register is already set Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has already been set. Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) or CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS, TARGET )). (10) * HALT mode (E) set while CPU is operating with internal high-speed oscillation clock (B) * HALT mode (F) set while CPU is operating with high-speed system clock (C) * HALT mode (G) set while CPU is operating with subsystem clock (D) Status Transition (B) (E) (C) (F) (D) (G) Executing HALT instruction Setting (11) * STOP mode (H) set while CPU is operating with internal high-speed oscillation clock (B) * STOP mode (I) set while CPU is operating with high-speed system clock (C) (Setting sequence) Status Transition (B) (H) (C) (I) Stopping peripheral functions that cannot operate in STOP mode Setting Executing STOP instruction Remarks 1. (A) to (I) in Table 6-5 correspond to (A) to (I) in Figure 6-14. 2. EXCLK, OSCSEL, AMPH: Bits 7, 6 and 0 of the clock operation mode select register (OSCCTL) MSTOP: XSEL, MCM0: CSS: Bit 7 of the main OSC control register (MOC) Bits 2 and 0 of the main clock mode register (MCM) Bit 4 of the processor clock control register (PCC) User's Manual U17397E4V0UD 165 CHAPTER 6 CLOCK GENERATOR www..com 6.6.7 Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. Table 6-6. Changing CPU Clock CPU Clock Before Change Internal highspeed oscillation After Change X1 clock Stabilization of X1 oscillation * MSTOP = 0, OSCSEL = 1, EXCLK = 0 * After elapse of oscillation stabilization time External main system clock Enabling input of external clock from EXCLK pin * MSTOP = 0, OSCSEL = 1, EXCLK = 1 * Internal high-speed oscillator can be stopped (RSTOP = 1). * Clock supply to CPU is stopped for 4.06 to 16.12 s after AMPH has been set to 1. * Internal high-speed oscillator can be stopped (RSTOP = 1). * Clock supply to CPU is stopped for the duration of 160 external clocks from the EXCLK pin after AMPH has been set to 1. X1 clock External main system clock Internal highspeed oscillation clock X1 clock External main system clock Internal highspeed oscillation clock X1 clock External main system clock XT1 clock, external subsystem clock Internal highspeed oscillation clock Oscillation of internal high-speed oscillator and selection of internal high-speed oscillation clock as main system clock * RSTOP = 0, MCS = 0 X1 clock Stabilization of X1 oscillation and selection of high-speed system clock as main system clock * XT1 oscillation can be stopped or external subsystem clock input can be disabled (OSCSELS = 0). * Clock supply to CPU is stopped for 4.06 to 16.12 s after AMPH has been set to 1. * XT1 oscillation can be stopped or external subsystem clock input can be disabled (OSCSELS = 0). * Clock supply to CPU is stopped for the duration of 160 external clocks from the EXCLK pin after AMPH has been set to 1. External subsystem clock Enabling input of external clock from EXCLKS pin * XTSTART = 0, EXCLKS = 1, OSCSELS = 1 Internal highspeed oscillation clock XT1 clock Stabilization of XT1 oscillation * XTSTART = 0, EXCLKS = 0, OSCSELS = 1, or XTSTART = 1 * After elapse of oscillation stabilization time Oscillation of internal high-speed oscillator * RSTOP = 0 X1 oscillation can be stopped (MSTOP = 1). External main system clock input can be disabled (MSTOP = 1). Operating current can be reduced by stopping internal high-speed oscillator (RSTOP = 1). X1 oscillation can be stopped (MSTOP = 1). External main system clock input can be disabled (MSTOP = 1). Operating current can be reduced by stopping internal high-speed oscillator (RSTOP = 1). X1 oscillation can be stopped (MSTOP = 1). External main system clock input can be disabled (MSTOP = 1). XT1 oscillation can be stopped or external subsystem clock input can be disabled (OSCSELS = 0). Condition Before Change Processing After Change clock * MSTOP = 0, OSCSEL = 1, EXCLK = 0 * After elapse of oscillation stabilization time * MCS = 1 External main system clock Enabling input of external clock from EXCLK pin and selection of high-speed system clock as main system clock * MSTOP = 0, OSCSEL = 1, EXCLK = 1 * MCS = 1 166 User's Manual U17397E4V0UD CHAPTER 6 CLOCK GENERATOR www..com 6.6.8 Time required for switchover of CPU clock and main system clock By setting bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC), the CPU clock can be switched (between the main system clock and the subsystem clock) and the division ratio of the main system clock can be changed. The actual switchover operation is not performed immediately after rewriting to PCC; operation continues on the pre-switchover clock for several clocks (see Table 6-7). Whether the CPU is operating on the main system clock or the subsystem clock can be ascertained using bit 5 (CLS) of the PCC register. Table 6-7. Time Required for Switchover of CPU Clock and Main System Clock Cycle Division Factor Set Value Before Switchover CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 Set Value After Switchover 0 0 0 0 0 0 1 1 x 0 0 1 1 0 x 0 1 0 1 0 x 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 x x x 16 clocks 8 clocks 4 clocks 2 clocks 1 clock 2 clocks 4 clocks 2 clocks 1 clock 2 clocks 16 clocks 8 clocks 16 clocks 8 clocks 4 clocks 16 clocks 8 clocks 4 clocks 2 clocks 2fXP/fSUB clocks fXP/fSUB clocks fXP/2fSUB clocks fXP/4fSUB clocks fXP/8fSUB clocks 2 clocks 1 clock 2 clocks 1 clock 2 clocks 2 clocks Caution Selection of the main system clock cycle division factor (PCC0 to PCC2) and switchover from the main system clock to the subsystem clock (changing CSS from 0 to 1) should not be set simultaneously. Simultaneous setting is possible, however, for selection of the main system clock cycle division factor (PCC0 to PCC2) and switchover from the subsystem clock to the main system clock (changing CSS from 1 to 0). Remarks 1. The number of clocks listed in Table 6-7 is the number of CPU clocks before switchover. 2. When switching the CPU clock from the main system clock to the subsystem clock, calculate the number of clocks by rounding up to the next clock and discarding the decimal portion, as shown below. Example When switching CPU clock from fXP/2 to fSUB/2 (@ oscillation with fXP = 10 MHz, fSUB = 32.768 kHz) fXP/fSUB = 10000/32.768 305.1 306 clocks By setting bit 0 (MCM0) of the main clock mode register (MCM), the main system clock can be switched (between the internal high-speed oscillation clock and the high-speed system clock). The actual switchover operation is not performed immediately after rewriting to MCM0; operation continues on the pre-switchover clock for several clocks (see Table 6-8). Whether the CPU is operating on the internal high-speed oscillation clock or the high-speed system clock can be ascertained using bit 1 (MCS) of MCM. User's Manual U17397E4V0UD 167 CHAPTER 6 CLOCK GENERATOR www..com Table 6-8. Maximum Time Required for Main System Clock Switchover Set Value Before Switchover MCM0 0 0 1 1 + 2fXH/fRH clock Set Value After Switchover MCM0 1 1 + 2fRH/fXH clock Caution When switching the internal high-speed oscillation clock to the high-speed system clock, bit 2 (XSEL) of MCM must be set to 1 in advance. The value of XSEL can be changed only once after a reset release. Remarks 1. The number of clocks listed in Table 6-8 is the number of main system clocks before switchover. 2. Calculate the number of clocks in Table 6-8 by removing the decimal portion. Example When switching the main system clock from the internal high-speed oscillation clock to the high-speed system clock (@ oscillation with fRH = 8 MHz, fXH = 10 MHz) 1 + 2fRH/fXH = 1 + 2 x 8/10 = 1 + 2 x 0.8 = 1 + 1.6 = 2.6 2 clocks 6.6.9 Conditions before clock oscillation is stopped The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and conditions before the clock oscillation is stopped. Table 6-9. Conditions Before the Clock Oscillation Is Stopped and Flag Settings Clock Conditions Before Clock Oscillation Is Stopped (External Clock Input Disabled) Internal high-speed oscillation clock MCS = 1 or CLS = 1 (The CPU is operating on a clock other than the internal high-speed oscillation clock) X1 clock External main system clock XT1 clock External subsystem clock MCS = 0 or CLS = 1 (The CPU is operating on a clock other than the high-speed system clock) CLS = 0 (The CPU is operating on a clock other than the subsystem clock) OSCSELS = 0 MSTOP = 1 Flag Settings of SFR Register RSTOP = 1 168 User's Manual U17397E4V0UD CHAPTER 6 CLOCK GENERATOR www..com 6.6.10 Peripheral hardware and source clocks The following lists peripheral hardware and source clocks incorporated in the 78K0/KF2. Table 6-10. Peripheral Hardware and Source Clocks Source Clock Peripheral Hardware 16-bit timer/ event counter 8-bit timer/ event counter 8-Bit timer 00 01 50 51 H0 H1 Watch timer Watchdog timer Buzzer output Clock output A/D converter Serial interface UART0 UART6 CSI10 CSI11 CSIA0 IIC0 Peripheral Hardware Clock (fPRS) Y Y Y Y Y Y Y N Y Y Y Y Y Y Y Y Y Subsystem Clock (fSUB) N N N N N N Y N N Y N N N N N N N Internal LowSpeed Oscillation Clock (fRL) N N N N N Y N Y N N N N N N N N N TM50 Output External Clock from Peripheral Hardware Pins Y (TI000 pin) Y (TI001 pin) Y (TI50 pin) Y (TI51 pin) N N N N N N N N N Y (SCK10 pin) Y (SCK11 pin) Note Note N N N N Y N N N N N N Y Y N N N N Note Note Note Note Y (SCKA0 pin) Note Y (EXSCL0, Note SCL0 pin) Note When the CPU is operating on the subsystem clock and the internal high-speed oscillation clock has been stopped, do not start operation of these functions on the external clock input from peripheral hardware pins. Remark Y: Can be selected, N: Cannot be selected User's Manual U17397E4V0UD 169 www..com CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.1 Functions of 16-Bit Timer/Event Counters 00 and 01 16-bit timer/event counters 00 and 01 have the following functions. (1) Interval timer 16-bit timer/event counters 00 and 01 generate an interrupt request at the preset time interval. (2) Square-wave output 16-bit timer/event counters 00 and 01 can output a square wave with any selected frequency. (3) External event counter 16-bit timer/event counters 00 and 01 can measure the number of pulses of an externally input signal. (4) One-shot pulse output 16-bit timer event counters 00 and 01 can output a one-shot pulse whose output pulse width can be set freely. (5) PPG output 16-bit timer/event counters 00 and 01 can output a rectangular wave whose frequency and output pulse width can be set freely. (6) Pulse width measurement 16-bit timer/event counters 00 and 01 can measure the pulse width of an externally input signal. 170 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com 7.2 Configuration of 16-Bit Timer/Event Counters 00 and 01 16-bit timer/event counters 00 and 01 include the following hardware. Table 7-1. Configuration of 16-Bit Timer/Event Counters 00 and 01 Item Time/counter Register Timer input Timer output Control registers 16-bit timer counter 0n (TM0n) 16-bit timer capture/compare registers 00n, 01n (CR00n, CR01n) TI00n, TI01n pins TO0n pin, output controller 16-bit timer mode control register 0n (TMC0n) 16-bit timer capture/compare control register 0n (CRC0n) 16-bit timer output control register 0n (TOC0n) Prescaler mode register 0n (PRM0n) Port mode register 0 (PM0) Port register 0 (P0) Configuration Remark n = 0, 1 Figures 7-1 and 7-2 show the block diagrams. Figure 7-1. Block Diagram of 16-Bit Timer/Event Counter 00 Internal bus Capture/compare control register 00 (CRC00) CRC002CRC001 CRC000 To CR010 Selector Selector INTTM000 TI010/TO00/P01 Noise eliminator 16-bit timer capture/compare register 000 (CR000) Match Selector fPRS fPRS/22 fPRS/28 16-bit timer counter 00 (TM00) Match Clear Output controller Output latch (P01) PM01 TO00/TI010/ P01 fPRS Noise eliminator 2 Noise eliminator 16-bit timer capture/compare register 010 (CR010) Selector TI000/P00 INTTM010 CRC002 PRM001 PRM000 Prescaler mode register 00 (PRM00) TMC003 TMC002 TMC001 OVF00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 16-bit timer output 16-bit timer mode control register 00 control register 00 (TOC00) (TMC00) Internal bus (Cautions 1 to 3 are listed on the next page.) User's Manual U17397E4V0UD 171 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-2. Block Diagram of 16-Bit Timer/Event Counter 01 Internal bus Capture/compare control register 01 (CRC01) CRC012CRC011 CRC010 To CR011 Selector Selector INTTM001 TI011/TO01/P06 Noise eliminator 16-bit timer capture/compare register 001 (CR001) Match Selector fPRS fPRS/24 fPRS/26 16-bit timer counter 01 (TM01) Match Clear Output controller Output latch (P06) PM06 TO01/TI011/ P06 fPRS TI001/P05/ SSI11 Noise eliminator 2 Noise eliminator 16-bit timer capture/compare register 011 (CR011) Selector INTTM011 CRC012 PRM011 PRM010 Prescaler mode register 01 (PRM01) TMC013 TMC012 TMC011 OVF01 OSPT01 OSPE01 TOC014 LVS01 LVR01 TOC011 TOE01 16-bit timer output 16-bit timer mode control register 01 control register 01 (TOC01) (TMC01) Internal bus Cautions 1. The valid edge of TI010 and timer output (TO00) cannot be used for the P01 pin at the same time, and the valid edge of TI011 and timer output (TO01) cannot be used for the P06 pin at the same time. Select either of the functions. 2. If clearing of bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n (TMC0n) to 00 and input of the capture trigger conflict, then the captured data is undefined. 3. To change the mode from the capture mode to the comparison mode, first clear the TMC0n3 and TMC0n2 bits to 00, and then change the setting. A value that has been once captured remains stored in CR00n unless the device is reset. If the mode has been changed to the comparison mode, be sure to set a comparison value. (1) 16-bit timer counter 0n (TM0n) TM0n is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the count clock. If the count value is read during operation, then input of the count clock is temporarily stopped, and the count value at that point is read. Remark n = 0, 1 172 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-3. Format of 16-Bit Timer Counter 0n (TM0n) Address: FF10H, FF11H (TM00), FFB0H, FFB1H (TM01) FF11H (TM00), FFB1H (TM01) 15 TM0n (n = 0, 1) 14 13 12 11 10 9 8 7 After reset: 0000H R FF10H (TM00), FFB0H (TM01) 6 5 4 3 2 1 0 The count value of TM0n can be read by reading TM0n when the value of bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n (TMC0n) is other than 00. The value of TM0n is 0000H if it is read when TMC0n3 and TMC0n2 = 00. The count value is reset to 0000H in the following cases. * At reset signal generation * If TMC0n3 and TMC0n2 are cleared to 00 * If the valid edge of the TI00n pin is input in the mode in which the clear & start occurs when inputting the valid edge to the TI00n pin * If TM0n and CR00n match in the mode in which the clear & start occurs when TM0n and CR00n match * OSPT0n is set to 1 in one-shot pulse output mode or the valid edge is input to the TI00n pin Caution Even if TM0n is read, the value is not captured by CR01n. (2) 16-bit timer capture/compare register 00n (CR00n)), 16-bit timer capture/compare register 01n (CR01n) CR00n and CR01n are 16-bit registers that are used with a capture function or comparison function selected by using CRC0n. Change the value of CR00n while the timer is stopped (TMC0n3 and TMC0n2 = 00). The value of CR01n can be changed during operation if the value has been set in a specific way. For details, see 7.5.1 Rewriting CR01n during TM0n operation. These registers can be read or written in 16-bit units. Reset signal generation clears these registers to 0000H. Remark n = 0, 1 User's Manual U17397E4V0UD 173 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-4. Format of 16-Bit Timer Capture/Compare Register 00n (CR00n) Address: FF12H, FF13H (CR000), FFB2H, FFB3H (CR001) FF13H (CR000), FFB3H (CR001) 15 CR00n (n = 0, 1) 14 13 12 11 10 9 8 7 After reset: 0000H R/W FF12H (CR000), FFB2H (CR001) 6 5 4 3 2 1 0 (i) When CR00n is used as a compare register The value set in CR00n is constantly compared with the TM0n count value, and an interrupt request signal (INTTM00n) is generated if they match. The value is held until CR00n is rewritten. Caution CR00n does not perform the capture operation when it is set in the comparison mode, even if a capture trigger is input to it. (ii) When CR00n is used as a capture register The count value of TM0n is captured to CR00n when a capture trigger is input. As the capture trigger, an edge of a phase reverse to that of the TI00n pin or the valid edge of the TI01n pin can be selected by using CRC0n or PRM0n. Figure 7-5. Format of 16-Bit Timer Capture/Compare Register 01n (CR01n) Address: FF14H, FF15H (CR010), FFB4H, FFB5H (CR011) FF15H (CR010), FFB5H (CR011) 15 CR01n (n = 0, 1) 14 13 12 11 10 9 8 7 After reset: 0000H R/W FF14H (CR010), FFB4H (CR011) 6 5 4 3 2 1 0 (i) When CR01n is used as a compare register The value set in CR01n is constantly compared with the TM0n count value, and an interrupt request signal (INTTM01n) is generated if they match. Caution CR01n does not perform the capture operation when it is set in the comparison mode, even if a capture trigger is input to it. (ii) When CR01n is used as a capture register The count value of TM0n is captured to CR01n when a capture trigger is input. It is possible to select the valid edge of the TI00n pin as the capture trigger. The TI00n pin valid edge is set by PRM0n. Remark n = 0, 1 174 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com (iii) Setting range when CR00n or CR01n is used as a compare register When CR00n or CR01n is used as a compare register, set it as shown below. Operation Operation as interval timer Operation as square-wave output Operation as external event counter Operation in the clear & start mode entered by TI00n pin valid edge input Operation as free-running timer Operation as PPG output Operation as one-shot pulse output M < N FFFFH 0000H Note CR00n Register Setting Range 0000H < N FFFFH 0000H CR01n Register Setting Range Note M FFFFH Normally, this setting is not used. Mask the match interrupt signal (INTTM01n). 0000H Note N FFFFH 0000H Note M FFFFH 0000H Note M 0000H Note Note When 0000H is set, a match interrupt immediately after the timer operation does not occur and timer output is not changed, and the first match timing is as follows. A match interrupt occurs at the timing when the timer counter (TM0n register) is changed from 0000H to 0001H. * When the timer counter is cleared due to overflow * When the timer counter is cleared due to TI00n pin valid edge (when clear & start mode is entered by TI00n pin valid edge input) * When the timer counter is cleared due to compare match (when clear & start mode is entered by match between TM0n and CR00n (CR00n = other than 0000H, CR01n = 0000H)) Timer counter clear TM0n register Compare register set value (0000H) Operation Timer operation enable bit disabled (00) (TMC0n3, TMC0n2) Operation enabled (other than 00) Interrupt request signal Interrupt signal is not generated Interrupt signal is generated Remarks 1. N: CR00n register set value, M: CR01n register set value 2. For details of TMC0n3 and TMC0n2, see 7.3 (1) 16-bit timer mode control register 0n (TMC0n). 3. n = 0, 1 User's Manual U17397E4V0UD 175 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Table 7-2. Capture Operation of CR00n and CR01n External Input Signal Capture Operation Capture operation of CR00n CRC0n1 = 1 TI00n pin input (reverse phase) Set values of ES0n1 and ES0n0 Position of edge to be captured 01: Rising CRC0n1 bit = 0 TI01n pin input Set values of ES1n1 and ES1n0 Position of edge to be captured 01: Rising TI00n Pin Input TI01n Pin Input 00: Falling 00: Falling 11: Both edges (cannot be captured) Interrupt signal INTTM00n signal is not generated even if value is captured. Capture operation of CR01n TI00n pin input Note 11: Both edges Interrupt signal INTTM00n signal is generated each time value is captured. Set values of ES0n1 and ES0n0 Position of edge to be captured 01: Rising 00: Falling 11: Both edges Interrupt signal INTTM01n signal is generated each time value is captured. Note The capture operation of CR01n is not affected by the setting of the CRC0n1 bit. Caution To capture the count value of the TM0n register to the CR00n register by using the phase reverse to that input to the TI00n pin, the interrupt request signal (INTTM00n) is not generated after the value has been captured. If the valid edge is detected on the TI01n pin during this operation, the capture operation is not performed but the INTTM00n signal is generated as an external interrupt signal. To not use the external interrupt, mask the INTTM00n signal. Remarks 1. CRC0n1: See 7.3 (2) Capture/compare control register 0n (CRC0n). ES1n1, ES1n0, ES0n1, ES0n0: See 7.3 (4) Prescaler mode register 0n (PRM0n). 2. n = 0, 1 176 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com 7.3 Registers Controlling 16-Bit Timer/Event Counters 00 and 01 Registers used to control 16-bit timer/event counters 00 and 01 are shown below. * 16-bit timer mode control register 0n (TMC0n) * Capture/compare control register 0n (CRC0n) * 16-bit timer output control register 0n (TOC0n) * Prescaler mode register 0n (PRM0n) * Port mode register 0 (PM0) * Port register 0 (P0) (1) 16-bit timer mode control register 0n (TMC0n) TMC0n is an 8-bit register that sets the 16-bit timer/event counter 0n operation mode, TM0n clear mode, and output timing, and detects an overflow. Rewriting TMC0n is prohibited during operation (when TMC0n3 and TMC0n2 = other than 00). However, it can be changed when TMC0n3 and TMC0n2 are cleared to 00 (stopping operation) and when OVF0n is cleared to 0. TMC0n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears TMC0n to 00H. Caution 16-bit timer/event counter 0n starts operation at the moment TMC0n2 and TMC0n3 are set to values other than 00 (operation stop mode), respectively. Set TMC0n2 and TMC0n3 to 00 to stop the operation. Remark n = 0, 1 User's Manual U17397E4V0UD 177 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-6. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address: FFBAH Symbol TMC00 After reset: 00H 7 0 6 0 R/W 5 0 4 0 3 TMC003 2 TMC002 1 TMC001 <0> OVF00 TMC003 0 TMC002 0 Operation enable of 16-bit timer/event counter 00 Disables 16-bit timer/event counter 00 operation. Stops supplying operating clock. Clears 16-bit timer counter 00 (TM00). 0 1 1 1 0 1 Free-running timer mode Clear & start mode entered by TI000 pin valid edge input Note Clear & start mode entered upon a match between TM00 and CR000 TMC001 0 1 Condition to reverse timer output (TO00) * Match between TM00 and CR000 or match between TM00 and CR010 * Match between TM00 and CR000 or match between TM00 and CR010 * Trigger input of TI000 pin valid edge OVF00 Clear (0) Set (1) TM00 overflow flag Clears OVF00 to 0 or TMC003 and TMC002 = 00 Overflow occurs. OVF00 is set to 1 when the value of TM00 changes from FFFFH to 0000H in all the operation modes (free-running timer mode, clear & start mode entered by TI000 pin valid edge input, and clear & start mode entered upon a match between TM00 and CR000). It can also be set to 1 by writing 1 to OVF00. Note The TI000 pin valid edge is set by bits 5 and 4 (ES001, ES000) of prescaler mode register 00 (PRM00). 178 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-7. Format of 16-Bit Timer Mode Control Register 01 (TMC01) Address: FFB6H Symbol TMC01 After reset: 00H 7 0 6 0 R/W 5 0 4 0 3 TMC013 2 TMC012 1 TMC011 <0> OVF01 TMC013 0 TMC012 0 Operation enable of 16-bit timer/event counter 01 Disables 16-bit timer/event counter 01 operation. Stops supplying operating clock. Clears 16-bit timer counter 01 (TM01). 0 1 1 1 0 1 Free-running timer mode Clear & start mode entered by TI001 pin valid edge input Note Clear & start mode entered upon a match between TM01 and CR001 TMC011 0 1 Condition to reverse timer output (TO01) * Match between TM01 and CR001 or match between TM01 and CR011 * Match between TM01 and CR001 or match between TM01 and CR011 * Trigger input of TI001 pin valid edge OVF01 Clear (0) Set (1) TM01 overflow flag Clears OVF01 to 0 or TMC013 and TMC012 = 00 Overflow occurs. OVF01 is set to 1 when the value of TM01 changes from FFFFH to 0000H in all the operation modes (free-running timer mode, clear & start mode entered by TI001 pin valid edge input, and clear & start mode entered upon a match between TM01 and CR001). It can also be set to 1 by writing 1 to OVF01. Note The TI001 pin valid edge is set by bits 5 and 4 (ES011, ES010) of prescaler mode register 01 (PRM01). User's Manual U17397E4V0UD 179 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com (2) Capture/compare control register 0n (CRC0n) CRC0n is the register that controls the operation of CR00n and CR01n. Changing the value of CRC0n is prohibited during operation (when TMC0n3 and TMC0n2 = other than 00). CRC0n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears CRC0n to 00H. Figure 7-8. Format of Capture/Compare Control Register 00 (CRC00) Address: FFBCH Symbol CRC00 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 CRC002 1 CRC001 0 CRC000 CRC002 0 1 CR010 operating mode selection Operates as compare register Operates as capture register CRC001 0 1 CR000 capture trigger selection Captures on valid edge of TI010 pin Captures on valid edge of TI000 pin by reverse phase Note The valid edge of the TI010 and TI000 pin is set by PRM00. If ES001 and ES000 are set to 11 (both edges) when CRC001 is 1, the valid edge of the TI000 pin cannot be detected. CRC000 0 1 CR000 operating mode selection Operates as compare register Operates as capture register If TMC003 and TMC002 are set to 11 (clear & start mode entered upon a match between TM00 and CR000), be sure to set CRC000 to 0. Note When the valid edge is detected from the TI010 pin, the capture operation is not performed but the INTTM000 signal is generated as an external interrupt signal. Caution To ensure that the capture operation is performed properly, the capture trigger requires a pulse two cycles longer than the count clock selected by prescaler mode register 00 (PRM00). Remark n = 0, 1 180 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-9. Example of CR01n Capture Operation (When Rising Edge Is Specified) Valid edge Count clock TM0n TI00n Rising edge detection CR01n INTTM01n N N-3 N-2 N-1 N N+1 Remark n = 0, 1 Figure 7-10. Format of Capture/Compare Control Register 01 (CRC01) Address: FFB8H Symbol CRC01 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 CRC012 1 CRC011 0 CRC010 CRC012 0 1 CR011 operating mode selection Operates as compare register Operates as capture register CRC011 0 1 CR001 capture trigger selection Captures on valid edge of TI011 pin Captures on valid edge of TI001 pin by reverse phase Note The valid edge of the TI011 and TI001 pin is set by PRM01. If ES011 and ES010 are set to 11 (both edges) when CRC011 is 1, the valid edge of the TI001 pin cannot be detected. CRC010 0 1 CR001 operating mode selection Operates as compare register Operates as capture register If TMC013 and TMC012 are set to 11 (clear & start mode entered upon a match between TM01 and CR001), be sure to set CRC010 to 0. Note When the valid edge is detected from the TI011 pin, the capture operation is not performed but the INTTM001 signal is generated as an external interrupt signal. Caution To ensure that the capture operation is performed properly, the capture trigger requires a pulse two cycles longer than the count clock selected by prescaler mode register 01 (PRM01) (see Figure 7-9 Example of CR01n Capture Operation (When Rising Edge Is Specified). User's Manual U17397E4V0UD 181 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com (3) 16-bit timer output control register 0n (TOC0n) TOC0n is an 8-bit register that controls the TO0n pin output. TOC0n can be rewritten while only OSPT0n is operating (when TMC0n3 and TMC0n2 = other than 00). Rewriting the other bits is prohibited during operation. However, TOC0n4 can be rewritten during timer operation as a means to rewrite CR01n (see 7.5.1 Rewriting CR01n during TM0n operation). TOC0n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears TOC0n to 00H. Caution Be sure to set TOC0n using the following procedure. <1> Set TOC0n4 and TOC0n1 to 1. <2> Set only TOE0n to 1. <3> Set either of LVS0n or LVR0n to 1. Remark n = 0, 1 182 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-11. Format of 16-Bit Timer Output Control Register 00 (TOC00) Address: FFBDH Symbol TOC00 7 0 After reset: 00H <6> OSPT00 R/W <5> OSPE00 4 TOC004 <3> LVS00 <2> LVR00 1 TOC001 <0> TOE00 OSPT00 0 1 One-shot pulse output One-shot pulse output trigger via software - The value of this bit is always "0" when it is read. Do not set this bit to 1 in a mode other than the oneshot pulse output mode. If it is set to 1, TM00 is cleared and started. OSPE00 0 1 Successive pulse output One-shot pulse output One-shot pulse output operation control One-shot pulse output operates correctly in the free-running timer mode or clear & start mode entered by TI000 pin valid edge input. The one-shot pulse cannot be output in the clear & start mode entered upon a match between TM00 and CR000. TOC004 0 1 TO00 pin output control on match between CR010 and TM00 Disables inversion operation Enables inversion operation The interrupt signal (INTTM010) is generated even when TOC004 = 0. LVS00 0 0 1 1 LVR00 0 1 0 1 No change Setting of TO00 pin output status Initial value of TO00 pin output is low level (TO00 pin output is cleared to 0). Initial value of TO00 pin output is high level (TO00 pin output is set to 1). Setting prohibited * LVS00 and LVR00 can be used to set the initial value of the output level of the TO00 pin. If the initial value does not have to be set, leave LVS00 and LVR00 as 00. * Be sure to set LVS00 and LVR00 when TOE00 = 1. LVS00, LVR00, and TOE00 being simultaneously set to 1 is prohibited. * LVS00 and LVR00 are trigger bits. By setting these bits to 1, the initial value of the output level of the TO00 pin can be set. Even if these bits are cleared to 0, output of the TO00 pin is not affected. * The values of LVS00 and LVR00 are always 0 when they are read. * For how to set LVS00 and LVR00, see 7.5.2 Setting LVS0n and LVR0n. TOC001 0 1 TO00 pin output control on match between CR000 and TM00 Disables inversion operation Enables inversion operation The interrupt signal (INTTM000) is generated even when TOC001 = 0. TOE00 0 1 TO00 pin output control Disables output (TO00 pin output fixed to low level) Enables output User's Manual U17397E4V0UD 183 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-12. Format of 16-Bit Timer Output Control Register 01 (TOC01) Address: FFB9H Symbol TOC01 7 0 After reset: 00H <6> OSPT01 R/W <5> OSPE01 4 TOC014 <3> LVS01 <2> LVR01 1 TOC011 <0> TOE01 OSPT01 0 1 One-shot pulse output One-shot pulse output trigger via software - The value of this bit is always 0 when it is read. Do not set this bit to 1 in a mode other than the one-shot pulse output mode. If it is set to 1, TM01 is cleared and started. OSPE01 0 1 Successive pulse output One-shot pulse output One-shot pulse output operation control One-shot pulse output operates correctly in the free-running timer mode or clear & start mode entered by TI001 pin valid edge input. The one-shot pulse cannot be output in the clear & start mode entered upon a match between TM01 and CR001. TOC014 0 1 TO01 pin output control on match between CR011 and TM01 Disables inversion operation Enables inversion operation The interrupt signal (INTTM011) is generated even when TOC014 = 0. LVS01 0 0 1 1 LVR01 0 1 0 1 No change Setting of TO01 pin output status Initial value of TO01 pin output is low level (TO01 pin output is cleared to 0). Initial value of TO01 pin output is high level (TO01 pin output is set to 1). Setting prohibited * LVS01 and LVR01 can be used to set the initial value of the output level of the TO01 pin. If the initial value does not have to be set, leave LVS01 and LVR01 as 00. * Be sure to set LVS01 and LVR01 when TOE01 = 1. LVS01, LVR01, and TOE01 being simultaneously set to 1 is prohibited. * LVS01 and LVR01 are trigger bits. By setting these bits to 1, the initial value of the output level of the TO01 pin can be set. Even if these bits are cleared to 0, output of the TO01 pin is not affected. * The values of LVS01 and LVR01 are always 0 when they are read. * For how to set LVS01 and LVR01, see 7.5.2 Setting LVS0n and LVR0n. TOC011 0 1 TO01 pin output control on match between CR001 and TM01 Disables inversion operation Enables inversion operation The interrupt signal (INTTM001) is generated even when TOC011 = 0. TOE01 0 1 TO01 pin output control Disables output (TO01 pin output is fixed to low level) Enables output User's Manual U17397E4V0UD 184 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com (4) Prescaler mode register 0n (PRM0n) PRM0n is the register that sets the TM0n count clock and TI00n and TI01n pin input valid edges. Rewriting PRM0n is prohibited during operation (when TMC0n3 and TMC0n2 = other than 00). PRM0n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears PRM0n to 00H. Cautions 1. Do not apply the following setting when setting the PRM0n1 and PRM0n0 bits to 11 (to specify the valid edge of the TI00n pin as a count clock). * Clear & start mode entered by the TI00n pin valid edge * Setting the TI00n pin as a capture trigger 2. If the operation of the 16-bit timer/event counter 0n is enabled when the TI00n or TI01n pin is at high level and when the valid edge of the TI00n or TI01n pin is specified to be the rising edge or both edges, the high level of the TI00n or TI01n pin is detected as a rising edge. Note this when the TI00n or TI01n pin is pulled up. However, the rising edge is not detected when the timer operation has been once stopped and then is enabled again. 3. The valid edge of TI010 and timer output (TO00) cannot be used for the P01 pin at the same time, and the valid edge of TI011 and timer output (TO01) cannot be used for the P06 pin at the same time. Select either of the functions. Remark n = 0, 1 User's Manual U17397E4V0UD 185 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-13. Format of Prescaler Mode Register 00 (PRM00) Address: FFBBH Symbol PRM00 7 ES101 After reset: 00H 6 ES100 R/W 5 ES001 4 ES000 3 0 2 0 1 PRM001 0 PRM000 ES101 0 0 1 1 ES100 0 1 0 1 Falling edge Rising edge Setting prohibited TI010 pin valid edge selection Both falling and rising edges ES001 0 0 1 1 ES000 0 1 0 1 Falling edge Rising edge Setting prohibited TI000 pin valid edge selection Both falling and rising edges PRM001 PRM000 Count clock selection fPRS = 2 MHz fPRS = 5 MHz 5 MHz 1.25 MHz 19.53 kHz fPRS = 10 MHz 10 MHz 2.5 MHz 39.06 kHz fPRS = 20 MHz 20 MHz 5 MHz 78.12 kHz 0 0 1 1 0 1 0 1 fPRS fPRS/2 fPRS/2 2 2 MHz 500 kHz 7.81 kHz Note 8 TI000 valid edge Note The external clock requires a pulse two cycles longer than internal clock (fPRS). Remark fPRS: Peripheral hardware clock frequency 186 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-14. Format of Prescaler Mode Register 01 (PRM01) Address: FFB7H Symbol PRM01 7 ES111 After reset: 00H 6 ES110 R/W 5 ES011 4 ES010 3 0 2 0 1 PRM011 0 PRM010 ES111 0 0 1 1 ES110 0 1 0 1 Falling edge Rising edge Setting prohibited TI011 pin valid edge selection Both falling and rising edges ES011 0 0 1 1 ES010 0 1 0 1 Falling edge Rising edge Setting prohibited TI001 pin valid edge selection Both falling and rising edges PRM011 PRM010 Count clock selection fPRS = 2 MHz fPRS = 5 MHz 5 MHz 312.5 kHz 78.125 kHz fPRS = 10 MHz 10 MHz 625 kHz 156.25 kHz fPRS = 20 MHz 20 MHz 1.25 MHz 312.5 kHz 0 0 1 1 0 1 0 1 fPRS fPRS/2 fPRS/2 4 2 MHz 125 kHz 31.25 kHz Note 6 TI001 valid edge Note The external clock requires a pulse two cycles longer than internal clock (fPRS). Remark fPRS: Peripheral hardware clock frequency User's Manual U17397E4V0UD 187 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com (5) Port mode register 0 (PM0) This register sets port 0 input/output in 1-bit units. When using the P01/TO00/TI010 and P06/TO01/TI011 pins for timer output, set PM01 and PM06 and the output latches of P01 and P06 to 0. When using the P00/TI000, P01/TO00/TI010, P05/TI001/SSI11, and P06/TO01/TI011 pins for timer input, set PM00, PM01, PM05, and PM06 to 1. At this time, the output latches of P00, P01, P05, and P06 may be 0 or 1. PM0 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PM0 to FFH. Figure 7-15. Format of Port Mode Register 0 (PM0) Address: FF20H Symbol PM0 7 1 6 After reset: FFH 5 4 R/W 3 2 1 0 PM06 PM05 PM04 PM03 PM02 PM01 PM00 PM0n 0 1 P0n pin I/O mode selection (n = 0 to 6) Output mode (output buffer on) Input mode (output buffer off) 188 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com 7.4 Operation of 16-Bit Timer/Event Counters 00 and 01 7.4.1 Interval timer operation If bits 3 and 2 (TMC0n3 and TMC0n2) of the 16-bit timer mode control register (TMC0n) are set to 11 (clear & start mode entered upon a match between TM0n and CR00n), the count operation is started in synchronization with the count clock. When the value of TM0n later matches the value of CR00n, TM0n is cleared to 0000H and a match interrupt signal (INTTM00n) is generated. This INTTM00n signal enables TM0n to operate as an interval timer. Remarks 1. For the setting of I/O pins, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS. Figure 7-16. Block Diagram of Interval Timer Operation Clear Count clock 16-bit counter (TM0n) Match signal Operable bits TMC0n3, TMC0n2 CR00n register INTTM00n signal Figure 7-17. Basic Timing Example of Interval Timer Operation N TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Compare register (CR00n) Compare match interrupt (INTTM00n) Interval (N + 1) Interval (N + 1) Interval (N + 1) Interval (N + 1) 00 11 N N N N Remark n = 0, 1 User's Manual U17397E4V0UD 189 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-18. Example of Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 0 0 0 0 1 1 0 OVF0n 0 Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 0 0 0 0 0 0 0 0 CR00n used as compare register (c) 16-bit timer output control register 0n (TOC0n) OSPT0n OSPE0n TOC0n4 0 0 0 0 LVS0n 0 LVR0n 0 TOC0n1 0 TOE0n 0 (d) Prescaler mode register 0n (PRM0n) ES1n1 0 ES1n0 0 ES0n1 0 ES0n0 0 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock (e) 16-bit timer counter 0n (TM0n) By reading TM0n, the count value can be read. (f) 16-bit capture/compare register 00n (CR00n) If M is set to CR00n, the interval time is as follows. * Interval time = (M + 1) x Count clock cycle Setting CR00n to 0000H is prohibited. (g) 16-bit capture/compare register 01n (CR01n) Usually, CR01n is not used for the interval timer function. However, a compare match interrupt (INTTM01n) is generated when the set value of CR01n matches the value of TM0n. Therefore, mask the interrupt request by using the interrupt mask flag (TMMK01n). Remark n = 0, 1 190 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-19. Example of Software Processing for Interval Timer Function N TM0n register 0000H Operable bits (TMC0n3, TMC0n2) N N 00 11 N CR00n register INTTM00n signal <1> <2> <1> Count operation start flow START Register initial setting PRM0n register, CRC0n register, CR00n register, port setting Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits to 11. TMC0n3, TMC0n2 bits = 11 Starts count operation <2> Count operation stop flow The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to 00. TMC0n3, TMC0n2 bits = 00 STOP Remark n = 0, 1 User's Manual U17397E4V0UD 191 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com 7.4.2 Square-wave output operation When 16-bit timer/event counter 0n operates as an interval timer (see 7.4.1), a square wave can be output from the TO0n pin by setting the 16-bit timer output control register 0n (TOC0n) to 03H. When TMC0n3 and TMC0n2 are set to 11 (count clear & start mode entered upon a match between TM0n and CR00n), the counting operation is started in synchronization with the count clock. When the value of TM0n later matches the value of CR00n, TM0n is cleared to 0000H, an interrupt signal (INTTM00n) is generated, and output of the TO0n pin is inverted. This TO0n pin output that is inverted at fixed intervals enables TO0n to output a square wave. Remarks 1. For the setting of I/O pins, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS. Figure 7-20. Block Diagram of Square-Wave Output Operation Clear Count clock 16-bit counter (TM0n) Match signal Operable bits TMC0n3, TMC0n2 CR00n register Output controller TO0n pin INTTM00n signal Figure 7-21. Basic Timing Example of Square-Wave Output Operation N TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Compare register (CR00n) TO0n pin output Compare match interrupt (INTTM00n) Interval (N + 1) Interval (N + 1) Interval (N + 1) Interval (N + 1) 00 11 N N N N Remark n = 0, 1 192 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-22. Example of Register Settings for Square-Wave Output Operation (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 0 0 0 0 1 1 0 OVF0n 0 Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 0 0 0 0 0 0 0 0 CR00n used as compare register (c) 16-bit timer output control register 0n (TOC0n) OSPT0n OSPE0n TOC0n4 0 0 0 0 LVS0n 0/1 LVR0n 0/1 TOC0n1 1 TOE0n 1 Enables TO0n pin output. Inverts TO0n pin output on match between TM0n and CR00n. Specifies initial value of TO0n output F/F (d) Prescaler mode register 0n (PRM0n) ES1n1 0 ES1n0 0 ES0n1 0 ES0n0 0 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock (e) 16-bit timer counter 0n (TM0n) By reading TM0n, the count value can be read. (f) 16-bit capture/compare register 00n (CR00n) If M is set to CR00n, the interval time is as follows. * Square wave frequency = 1 / [2 x (M + 1) x Count clock cycle] Setting CR00n to 0000H is prohibited. (g) 16-bit capture/compare register 01n (CR01n) Usually, CR01n is not used for the square-wave output function. However, a compare match interrupt (INTTM01n) is generated when the set value of CR01n matches the value of TM0n. Therefore, mask the interrupt request by using the interrupt mask flag (TMMK01n). Remark n = 0, 1 User's Manual U17397E4V0UD 193 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-23. Example of Software Processing for Square-Wave Output Function N TM0n register 0000H Operable bits (TMC0n3, TMC0n2) N N 00 11 N 00 CR00n register TO0n pin output INTTM00n signal TO0n output control bit (TOC0n1, TOE0n) <1> <2> <1> Count operation start flow START Register initial setting PRM0n register, CRC0n register, TOC0n registerNote, CR00n register, port setting Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits to 11. TMC0n3, TMC0n2 bits = 11 Starts count operation <2> Count operation stop flow The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to 00. TMC0n3, TMC0n2 bits = 00 STOP Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control register 0n (TOC0n). Remark n = 0, 1 194 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com 7.4.3 External event counter operation When bits 1 and 0 (PRM0n1 and PRM0n0) of the prescaler mode register 0n (PRM0n) are set to 11 (for counting up with the valid edge of the TI00n pin) and bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n (TMC0n) are set to 11, the valid edge of an external event input is counted, and a match interrupt signal indicating matching between TM0n and CR00n (INTTM00n) is generated. To input the external event, the TI00n pin is used. Therefore, the timer/event counter cannot be used as an external event counter in the clear & start mode entered by the TI00n pin valid edge input (when TMC0n3 and TMC0n2 = 10). The INTTM00n signal is generated with the following timing. * Timing of generation of INTTM00n signal (second time or later) = Number of times of detection of valid edge of external event x (Set value of CR00n + 1) However, the first match interrupt immediately after the timer/event counter has started operating is generated with the following timing. * Timing of generation of INTTM00n signal (first time only) = Number of times of detection of valid edge of external event input x (Set value of CR00n + 2) To detect the valid edge, the signal input to the TI00n pin is sampled during the clock cycle of fPRS. The valid edge is not detected until it is detected two times in a row. Therefore, a noise with a short pulse width can be eliminated. Remarks 1. For the setting of I/O pins, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS. Figure 7-24. Block Diagram of External Event Counter Operation fPRS Clear TI00n pin Edge detection Output controller TO0n pin 16-bit counter (TM0n) Match signal Operable bits TMC0n3, TMC0n2 CR00n register INTTM00n signal Remark n = 0, 1 User's Manual U17397E4V0UD 195 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-25. Example of Register Settings in External Event Counter Mode (1/2) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 0 0 0 0 1 1 0 OVF0n 0 Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 0 0 0 0 0 0 0 0 CR00n used as compare register (c) 16-bit timer output control register 0n (TOC0n) OSPT0n OSPE0n TOC0n4 0 0 0 0/1 LVS0n 0/1 LVR0n 0/1 TOC0n1 0/1 TOE0n 0/1 0: Disables TO0n output 1: Enables TO0n output Specifies initial value of TO0n output F/F 00: Does not invert TO0n output on match between TM0n and CR00n/CR01n. 01: Inverts TO0n output on match between TM0n and CR00n. 10: Inverts TO0n output on match between TM0n and CR01n. 11: Inverts TO0n output on match between TM0n and CR00n/CR01n. (d) Prescaler mode register 0n (PRM0n) ES1n1 0 ES1n0 0 ES0n1 0/1 ES0n0 0/1 3 0 2 0 PRM0n1 PRM0n0 1 1 Selects count clock (specifies valid edge of TI00n). 00: Falling edge detection 01: Rising edge detection 10: Setting prohibited 11: Both edges detection Remark n = 0, 1 196 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-25. Example of Register Settings in External Event Counter Mode (2/2) (e) 16-bit timer counter 0n (TM0n) By reading TM0n, the count value can be read. (f) 16-bit capture/compare register 00n (CR00n) If M is set to CR00n, the interrupt signal (INTTM00n) is generated when the number of external events reaches (M + 1). Setting CR00n to 0000H is prohibited. (g) 16-bit capture/compare register 01n (CR01n) Usually, CR01n is not used in the external event counter mode. However, a compare match interrupt (INTTM01n) is generated when the set value of CR01n matches the value of TM0n. Therefore, mask the interrupt request by using the interrupt mask flag (TMMK01n). Remark n = 0, 1 User's Manual U17397E4V0UD 197 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-26. Example of Software Processing in External Event Counter Mode N TM0n register 0000H Operable bits (TMC0n3, TMC0n2) N N 00 11 N 00 Compare register (CR00n) TO0n pin output Compare match interrupt (INTTM00n) TO0n output control bits (TOC0n4, TOC0n1, TOE0n) <1> <2> <1> Count operation start flow START Register initial setting PRM0n register, CRC0n register, TOC0n registerNote, CR00n register, port setting Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits to 11. TMC0n3, TMC0n2 bits = 11 Starts count operation <2> Count operation stop flow TMC0n3, TMC0n2 bits = 00 The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to 00. STOP Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control register 0n (TOC0n). Remark n = 0, 1 198 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com 7.4.4 Operation in clear & start mode entered by TI00n pin valid edge input When bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n (TMC0n) are set to 10 (clear & start mode entered by the TI00n pin valid edge input) and the count clock (set by PRM0n) is supplied to the timer/event counter, TM0n starts counting up. When the valid edge of the TI00n pin is detected during the counting operation, TM0n is cleared to 0000H and starts counting up again. If the valid edge of the TI00n pin is not detected, TM0n overflows and continues counting. The valid edge of the TI00n pin is a cause to clear TM0n. Starting the counter is not controlled immediately after the start of the operation. CR00n and CR01n are used as compare registers and capture registers. (a) When CR00n and CR01n are used as compare registers Signals INTTM00n and INTTM01n are generated when the value of TM0n matches the value of CR00n and CR01n. (b) When CR00n and CR01n are used as capture registers The count value of TM0n is captured to CR00n and the INTTM00n signal is generated when the valid edge is input to the TI01n pin (or when the phase reverse to that of the valid edge is input to the TI00n pin). When the valid edge is input to the TI00n pin, the count value of TM0n is captured to CR01n and the INTTM01n signal is generated. As soon as the count value has been captured, the counter is cleared to 0000H. Caution Do not set the count clock as the valid edge of the TI00n pin (PRM0n1 and PRM0n0 = 11). When PRM0n1 and PRM0n0 = 11, TM0n is cleared. Remarks 1. For the setting of the I/O pins, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS. 3. n = 0, 1 (1) Operation in clear & start mode entered by TI00n pin valid edge input (CR00n: compare register, CR01n: compare register) Figure 7-27. Block Diagram of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Compare Register, CR01n: Compare Register) Edge detection Clear Count clock Timer counter (TM0n) Match signal Operable bits TMC0n3, TMC0n2 Compare register (CR00n) Match signal Output controller Interrupt signal (INTTM00n) TO0n pin Interrupt signal (INTTM01n) TI00n pin Compare register (CR01n) Remark n = 0, 1 User's Manual U17397E4V0UD 199 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-28. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Compare Register, CR01n: Compare Register) (a) TOC0n = 13H, PRM0n = 10H, CRC0n, = 00H, TMC0n = 08H TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Count clear input (TI00n pin input) Compare register (CR00n) Compare match interrupt (INTTM00n) Compare register (CR01n) Compare match interrupt (INTTM01n) TO0n pin output M 00 10 M N N M N M N M N (b) TOC0n = 13H, PRM0n = 10H, CRC0n, = 00H, TMC0n = 0AH TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Count clear input (TI00n pin input) Compare register (CR00n) Compare match interrupt (INTTM00n) Compare register (CR01n) Compare match interrupt (INTTM01n) TO0n pin output M 00 10 M N N M N M N M N (a) and (b) differ as follows depending on the setting of bit 1 (TMC0n1) of the 16-bit timer mode control register 0n (TMC0n). (a) The output level of the TO0n pin is inverted when TM0n matches a compare register. (b) The output level of the TO0n pin is inverted when TM0n matches a compare register or when the valid edge of the TI00n pin is detected. Remark n = 0, 1 200 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com (2) Operation in clear & start mode entered by TI00n pin valid edge input (CR00n: compare register, CR01n: capture register) Figure 7-29. Block Diagram of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Compare Register, CR01n: Capture Register) Edge detector Clear Count clock Timer counter (TM0n) Match signal Operable bits TMC0n3, TMC0n2 Compare register (CR00n) Output controller Interrupt signal (INTTM00n) TO0n pin TI00n pin Capture signal Capture register (CR01n) Interrupt signal (INTTM01n) Figure 7-30. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Compare Register, CR01n: Capture Register) (1/2) (a) TOC0n = 13H, PRM0n = 10H, CRC0n, = 04H, TMC0n = 08H, CR00n = 0001H M TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Capture & count clear input (TI00n pin input) Compare register (CR00n) Compare match interrupt (INTTM00n) Capture register (CR01n) Capture interrupt (INTTM01n) TO0n pin output N S P Q 00 10 0001H 0000H M N S P Q This is an application example where the output level of the TO0n pin is inverted when the count value has been captured & cleared. The count value is captured to CR01n and TM0n is cleared (to 0000H) when the valid edge of the TI00n pin is detected. When the count value of TM0n is 0001H, a compare match interrupt signal (INTTM00n) is generated, and the output level of the TO0n pin is inverted. Remark n = 0, 1 User's Manual U17397E4V0UD 201 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-30. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Compare Register, CR01n: Capture Register) (2/2) (b) TOC0n = 13H, PRM0n = 10H, CRC0n, = 04H, TMC0n = 0AH, CR00n = 0003H M TM0n register 0003H 0000H Operable bits (TMC0n3, TMC0n2) Capture & count clear input (TI00n pin input) Compare register (CR00n) Compare match interrupt (INTTM00n) Capture register (CR01n) Capture interrupt (INTTM01n) TO0n pin output 0000H M N S P Q 0003H 00 10 N S P Q 4 4 4 4 This is an application example where the width set to CR00n (4 clocks in this example) is to be output from the TO0n pin when the count value has been captured & cleared. The count value is captured to CR01n, a capture interrupt signal (INTTM01n) is generated, TM0n is cleared (to 0000H), and the output level of the TO0n pin is inverted when the valid edge of the TI00n pin is detected. When the count value of TM0n is 0003H (four clocks have been counted), a compare match interrupt signal (INTTM00n) is generated and the output level of the TO0n pin is inverted. Remark n = 0, 1 202 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com (3) Operation in clear & start mode by entered TI00n pin valid edge input (CR00n: capture register, CR01n: compare register) Figure 7-31. Block Diagram of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Capture Register, CR01n: Compare Register) TI00n pin Edge detection Clear Count clock Timer counter (TM0n) Match signal Interrupt signal (INTTM01n) Output controller TO0n pin Operable bits TMC0n3, TMC0n2 Compare register (CR01n) Capture signal Capture register (CR00n) Interrupt signal (INTTM00n) Remark n = 0, 1 User's Manual U17397E4V0UD 203 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-32. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Capture Register, CR01n: Compare Register) (1/2) (a) TOC0n = 13H, PRM0n = 10H, CRC0n, = 03H, TMC0n = 08H, CR01n = 0001H TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Capture & count clear input (TI00n pin input) Capture register (CR00n) Capture interrupt (INTTM00n) Compare register (CR01n) Compare match interrupt (INTTM01n) TO0n pin output M N S P 00 10 0000H L 0001H M N S P This is an application example where the output level of the TO0n pin is to be inverted when the count value has been captured & cleared. TM0n is cleared at the rising edge detection of the TI00n pin and it is captured to CR00n at the falling edge detection of the TI00n pin. When bit 1 (CRC0n1) of capture/compare control register 0n (CRC0n) is set to 1, the count value of TM0n is captured to CR00n in the phase reverse to that of the signal input to the TI00n pin, but the capture interrupt signal (INTTM00n) is not generated. However, the INTTM00n signal is generated when the valid edge of the TI01n pin is detected. Mask the INTTM00n signal when it is not used. Remark n = 0, 1 204 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-32. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Capture Register, CR01n: Compare Register) (2/2) (b) TOC0n = 13H, PRM0n = 10H, CRC0n, = 03H, TMC0n = 0AH, CR01n = 0003H TM0n register 0003H 0000H Operable bits (TMC0n3, TMC0n2) Capture & count clear input (TI00n pin input) Capture register (CR00n) Capture interrupt (INTTM00n) Compare register (CR01n) Compare match interrupt (INTTM01n) TO0n pin output M N S P 00 10 0000H L 0003H M N S P 4 4 4 4 This is an application example where the width set to CR01n (4 clocks in this example) is to be output from the TO0n pin when the count value has been captured & cleared. TM0n is cleared (to 0000H) at the rising edge detection of the TI00n pin and captured to CR00n at the falling edge detection of the TI00n pin. The output level of the TO0n pin is inverted when TM0n is cleared (to 0000H) because the rising edge of the TI00n pin has been detected or when the value of TM0n matches that of a compare register (CR01n). When bit 1 (CRC0n1) of capture/compare control register 0n (CRC0n) is 1, the count value of TM0n is captured to CR00n in the phase reverse to that of the input signal of the TI00n pin, but the capture interrupt signal (INTTM00n) is not generated. However, the INTTM00n interrupt is generated when the valid edge of the TI01n pin is detected. Mask the INTTM00n signal when it is not used. Remark n = 0, 1 User's Manual U17397E4V0UD 205 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com (4) Operation in clear & start mode entered by TI00n pin valid edge input (CR00n: capture register, CR01n: capture register) Figure 7-33. Block Diagram of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Capture Register, CR01n: Capture Register) Operable bits TMC0n3, TMC0n2 Clear Timer counter (TM0n) Count clock Capture signal Capture register (CR01n) Output controller Interrupt signal (INTTM01n) TO0n pinNote Interrupt signal (INTTM00n) Selector TI00n pin TI01n pin Note Edge detection Edge detection Capture signal Capture register (CR00n) Note The timer output (TO0n) cannot be used when detecting the valid edge of the TI01n pin is used. Remark n = 0, 1 Figure 7-34. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Capture Register, CR01n: Capture Register) (1/3) (a) TOC0n = 13H, PRM0n = 30H, CRC0n = 05H, TMC0n = 0AH L TM0n register M 0000H Operable bits (TMC0n3, TMC0n2) Capture & count clear input (TI00n pin input) Capture register (CR00n) Capture interrupt (INTTM00n) Capture register (CR01n) Capture interrupt (INTTM01n) TO0n pin output N O P Q R S T 00 10 0000H L 0000H L M N O P Q R S T This is an application example where the count value is captured to CR01n, TM0n is cleared, and the TO0n pin output is inverted when the rising or falling edge of the TI00n pin is detected. When the edge of the TI01n pin is detected, an interrupt signal (INTTM00n) is generated. Mask the INTTM00n signal when it is not used. Remark n = 0, 1 User's Manual U17397E4V0UD 206 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-34. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Capture Register, CR01n: Capture Register) (2/3) (b) TOC0n = 13H, PRM0n = C0H, CRC0n = 05H, TMC0n = 0AH FFFFH TM0n register M 0000H Operable bits (TMC0n3, TMC0n2) Capture trigger input (TI01n pin input) Capture register (CR00n) Capture interrupt (INTTM00n) Capture & count clear input (TI00n) Capture register (CR01n) Capture interrupt (INTTM01n) O N P Q S R L T 00 10 0000H L M N O P Q R S T L 0000H L This is a timing example where an edge is not input to the TI00n pin, in an application where the count value is captured to CR00n when the rising or falling edge of the TI01n pin is detected. Remark n = 0, 1 User's Manual U17397E4V0UD 207 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-34. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Capture Register, CR01n: Capture Register) (3/3) (c) TOC0n = 13H, PRM0n = 00H, CRC0n = 07H, TMC0n = 0AH M TM0n register L 0000H Operable bits (TMC0n3, TMC0n2) Capture & count clear input (TI00n pin input) Capture register (CR00n) Capture register (CR01n) Capture interrupt (INTTM01n) Capture input (TI01n) Capture interrupt (INTTM00n) N P O Q R S T W 00 10 0000H 0000H L M N O P Q R S T W L L This is an application example where the pulse width of the signal input to the TI00n pin is measured. By setting CRC0n, the count value can be captured to CR00n in the phase reverse to the falling edge of the TI00n pin (i.e., rising edge) and to CR01n at the falling edge of the TI00n pin. The high- and low-level widths of the input pulse can be calculated by the following expressions. * High-level width = [CR01n value] - [CR00n value] x [Count clock cycle] * Low-level width = [CR00n value] x [Count clock cycle] If the reverse phase of the TI00n pin is selected as a trigger to capture the count value to CR00n, the INTTM00n signal is not generated. Read the values of CR00n and CR01n to measure the pulse width immediately after the INTTM01n signal is generated. However, if the valid edge specified by bits 6 and 5 (ES1n1 and ES1n0) of prescaler mode register 0n (PRM0n) is input to the TI01n pin, the count value is not captured but the INTTM00n signal is generated. To measure the pulse width of the TI00n pin, mask the INTTM00n signal when it is not used. Remark n = 0, 1 208 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-35. Example of Register Settings in Clear & Start Mode Entered by TI00n Pin Valid Edge Input (1/2) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 0 0 0 0 1 0 0/1 OVF0n 0 0: Inverts TO0n output on match between TM0n and CR00n/CR01n. 1: Inverts TO0n output on match between TM0n and CR00n/CR01n and valid edge of TI00n pin. Clears and starts at valid edge input of TI00n pin. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 0 0 0 0 0 0/1 0/1 0/1 0: CR00n used as compare register 1: CR00n used as capture register 0: TI01n pin is used as capture trigger of CR00n. 1: Reverse phase of TI00n pin is used as capture trigger of CR00n. 0: CR01n used as compare register 1: CR01n used as capture register (c) 16-bit timer output control register 0n (TOC0n) OSPT0n OSPE0n TOC0n4 0 0 0 0/1 LVS0n 0/1 LVR0n 0/1 TOC0n1 0/1 TOE0n 0/1 0: Disables TO0n outputNote 1: Enables TO0n output Specifies initial value of TO0n output F/F 00: Does not invert TO0n output on match between TM0n and CR00n/CR01n. 01: Inverts TO0n output on match between TM0n and CR00n. 10: Inverts TO0n output on match between TM0n and CR01n. 11: Inverts TO0n output on match between TM0n and CR00n/CR01n. Note The timer output (TO0n) cannot be used when detecting the valid edge of the TI01n pin is used. Remark n = 0, 1 User's Manual U17397E4V0UD 209 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-35. Example of Register Settings in Clear & Start Mode Entered by TI00n Pin Valid Edge Input (2/2) (d) Prescaler mode register 0n (PRM0n) ES1n1 0/1 ES1n0 0/1 ES0n1 0/1 ES0n0 0/1 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Count clock selection (setting TI00n valid edge is prohibited) 00: 01: 10: 11: 00: 01: 10: 11: Falling edge detection Rising edge detection Setting prohibited Both edges detection (setting prohibited when CRC0n1 = 1) Falling edge detection Rising edge detection Setting prohibited Both edges detection (e) 16-bit timer counter 0n (TM0n) By reading TM0n, the count value can be read. (f) 16-bit capture/compare register 00n (CR00n) When this register is used as a compare register and when its value matches the count value of TM0n, an interrupt signal (INTTM00n) is generated. The count value of TM0n is not cleared. To use this register as a capture register, select either the TI00n or TI01n pinNote input as a capture trigger. When the valid edge of the capture trigger is detected, the count value of TM0n is stored in CR00n. Note The timer output (TO0n) cannot be used when detection of the valid edge of the TI01n pin is used. (g) 16-bit capture/compare register 01n (CR01n) When this register is used as a compare register and when its value matches the count value of TM0n, an interrupt signal (INTTM01n) is generated. The count value of TM0n is not cleared. When this register is used as a capture register, the TI00n pin input is used as a capture trigger. When the valid edge of the capture trigger is detected, the count value of TM0n is stored in CR01n. Remark n = 0, 1 210 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-36. Example of Software Processing in Clear & Start Mode Entered by TI00n Pin Valid Edge Input TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Count clear input (TI00n pin input) Compare register (CR00n) Compare match interrupt (INTTM00n) Compare register (CR01n) Compare match interrupt (INTTM01n) TO0n pin output M N N M N M N M 00 10 00 M N <1> <2> <2> <2> <2> <3> <1> Count operation start flow <3> Count operation stop flow The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to 00. START TMC0n3, TMC0n2 bits = 00 Register initial setting PRM0n register, CRC0n register, TOC0n registerNote, CR00n, CR01n registers, TMC0n.TMC0n1 bit, port setting Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits to 10. STOP TMC0n3, TMC0n2 bits = 10 Starts count operation <2> TM0n register clear & start flow Edge input to TI00n pin When the valid edge is input to the TI00n pin, the value of the TM0n register is cleared. Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control register 0n (TOC0n). Remark n = 0, 1 User's Manual U17397E4V0UD 211 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com 7.4.5 Free-running timer operation When bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n (TMC0n) are set to 01 (freerunning timer mode), 16-bit timer/event counter 0n continues counting up in synchronization with the count clock. When it has counted up to FFFFH, the overflow flag (OVF0n) is set to 1 at the next clock, and TM0n is cleared (to 0000H) and continues counting. Clear OVF0n to 0 by executing the CLR instruction via software. The following three types of free-running timer operations are available. * Both CR00n and CR01n are used as compare registers. * One of CR00n or CR01n is used as a compare register and the other is used as a capture register. * Both CR00n and CR01n are used as capture registers. Remarks 1. For the setting of the I/O pins, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS. (1) Free-running timer mode operation (CR00n: compare register, CR01n: compare register) Figure 7-37. Block Diagram of Free-Running Timer Mode (CR00n: Compare Register, CR01n: Compare Register) Count clock Timer counter (TM0n) Match signal Operable bits TMC0n3, TMC0n2 Compare register (CR00n) Match signal Output controller Interrupt signal (INTTM00n) TO0n pin Interrupt signal (INTTM01n) Compare register (CR01n) Remark n = 0, 1 212 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-38. Timing Example of Free-Running Timer Mode (CR00n: Compare Register, CR01n: Compare Register) * TOC0n = 13H, PRM0n = 00H, CRC0n = 00H, TMC0n = 04H FFFFH TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Compare register (CR00n) Compare match interrupt (INTTM00n) Compare register (CR01n) Compare match interrupt (INTTM01n) TO0n pin output OVF0n bit N M N M N M N M 00 01 M 00 N 0 write clear 0 write clear 0 write clear 0 write clear This is an application example where two compare registers are used in the free-running timer mode. The output level of the TO0n pin is reversed each time the count value of TM0n matches the set value of CR00n or CR01n. When the count value matches the register value, the INTTM00n or INTTM01n signal is generated. Remark n = 0, 1 (2) Free-running timer mode operation (CR00n: compare register, CR01n: capture register) Figure 7-39. Block Diagram of Free-Running Timer Mode (CR00n: Compare Register, CR01n: Capture Register) Count clock Timer counter (TM0n) Match signal Operable bits TMC0n3, TMC0n2 Compare register (CR00n) Output controller Interrupt signal (INTTM00n) TO0n pin TI00n pin Edge detection Capture signal Capture register (CR01n) Interrupt signal (INTTM01n) Remark n = 0, 1 User's Manual U17397E4V0UD 213 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-40. Timing Example of Free-Running Timer Mode (CR00n: Compare Register, CR01n: Capture Register) * TOC0n = 13H, PRM0n = 10H, CRC0n = 04H, TMC0n = 04H FFFFH M TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Capture trigger input (TI00n) Compare register (CR00n) Compare match interrupt (INTTM00n) Capture register (CR01n) Capture interrupt (INTTM01n) TO0n pin output Overflow flag (OVF0n) N S P Q 00 01 0000H 0000H M N S P Q 0 write clear 0 write clear 0 write clear 0 write clear This is an application example where a compare register and a capture register are used at the same time in the free-running timer mode. In this example, the INTTM00n signal is generated and the output level of the TO0n pin is reversed each time the count value of TM0n matches the set value of CR00n (compare register). In addition, the INTTM01n signal is generated and the count value of TM0n is captured to CR01n each time the valid edge of the TI00n pin is detected. Remark n = 0, 1 214 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com (3) Free-running timer mode operation (CR00n: capture register, CR01n: capture register) Figure 7-41. Block Diagram of Free-Running Timer Mode (CR00n: Capture Register, CR01n: Capture Register) Operable bits TMC0n3, TMC0n2 Timer counter (TM0n) Count clock Capture signal Capture register (CR01n) Interrupt signal (INTTM01n) Selector TI00n pin TI01n pin Edge detection Edge detection Capture signal Capture register (CR00n) Interrupt signal (INTTM00n) Remarks 1. If both CR00n and CR01n are used as capture registers in the free-running timer mode, the output level of the TO0n pin is not inverted. However, it can be inverted each time the valid edge of the TI00n pin is detected if bit 1 (TMC0n1) of 16-bit timer mode control register 0n (TMC0n) is set to 1. 2. n = 0, 1 User's Manual U17397E4V0UD 215 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-42. Timing Example of Free-Running Timer Mode (CR00n: Capture Register, CR01n: Capture Register) (1/2) (a) TOC0n = 13H, PRM0n = 50H, CRC0n = 05H, TMC0n = 04H FFFFH M TM0n register A 0000H Operable bits (TMC0n3, TMC0n2) Capture trigger input (TI00n) Capture register (CR01n) Capture interrupt (INTTM01n) Capture trigger input (TI01n) Capture register (CR00n) Capture interrupt (INTTM00n) Overflow flag (OVF0n) 0 write clear 0 write clear 0 write clear 0 write clear B N C S D P E Q 00 01 0000H M N S P Q 0000H A B C D E This is an application example where the count values that have been captured at the valid edges of separate capture trigger signals are stored in separate capture registers in the free-running timer mode. The count value is captured to CR01n when the valid edge of the TI00n pin input is detected and to CR00n when the valid edge of the TI01n pin input is detected. Remark n = 0, 1 216 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-42. Timing Example of Free-Running Timer Mode (CR00n: Capture Register, CR01n: Capture Register) (2/2) (b) TOC0n = 13H, PRM0n = C0H, CRC0n = 05H, TMC0n = 04H FFFFH TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Capture trigger input (TI01n) Capture register (CR00n) Capture interrupt (INTTM00n) Capture trigger input (TI00n) Capture register (CR01n) Capture interrupt (INTTM01n) M O N P Q S R L T 00 01 0000H L M N O P Q R S T L 0000H L This is an application example where both the edges of the TI01n pin are detected and the count value is captured to CR00n in the free-running timer mode. When both CR00n and CR01n are used as capture registers and when the valid edge of only the TI01n pin is to be detected, the count value cannot be captured to CR01n. Remark n = 0, 1 User's Manual U17397E4V0UD 217 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-43. Example of Register Settings in Free-Running Timer Mode (1/2) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 0 0 0 0 0 1 0/1 OVF0n 0 0: Inverts TO0n pin output on match between TM0n and CR00n/CR01n. 1: Inverts TO0n pin output on match between TM0n and CR00n/CR01n valid edge of TI00n pin. Free-running timer mode (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 0 0 0 0 0 0/1 0/1 0/1 0: CR00n used as compare register 1: CR00n used as capture register 0: TI01n pin is used as capture trigger of CR00n. 1: Reverse phase of TI00n pin is used as capture trigger of CR00n. 0: CR01n used as compare register 1: CR01n used as capture register (c) 16-bit timer output control register 0n (TOC0n) OSPT0n OSPE0n TOC0n4 0 0 0 0/1 LVS0n 0/1 LVR0n 0/1 TOC0n1 0/1 TOE0n 0/1 0: Disables TO0n output 1: Enables TO0n output Specifies initial value of TO0n output F/F 00: Does not invert TO0n output on match between TM0n and CR00n/CR01n. 01: Inverts TO0n output on match between TM0n and CR00n. 10: Inverts TO0n output on match between TM0n and CR01n. 11: Inverts TO0n output on match between TM0n and CR00n/CR01n. Remark n = 0, 1 218 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-43. Example of Register Settings in Free-Running Timer Mode (2/2) (d) Prescaler mode register 0n (PRM0n) ES1n1 0/1 ES1n0 0/1 ES0n1 0/1 ES0n0 0/1 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Count clock selection (setting TI00n valid edge is prohibited) 00: 01: 10: 11: Falling edge detection Rising edge detection Setting prohibited Both edges detection (setting prohibited when CRC0n1 = 1) Falling edge detection Rising edge detection Setting prohibited Both edges detection 00: 01: 10: 11: (e) 16-bit timer counter 0n (TM0n) By reading TM0n, the count value can be read. (f) 16-bit capture/compare register 00n (CR00n) When this register is used as a compare register and when its value matches the count value of TM0n, an interrupt signal (INTTM00n) is generated. The count value of TM0n is not cleared. To use this register as a capture register, select either the TI00n or TI01n pin input as a capture trigger. When the valid edge of the capture trigger is detected, the count value of TM0n is stored in CR00n. (g) 16-bit capture/compare register 01n (CR01n) When this register is used as a compare register and when its value matches the count value of TM0n, an interrupt signal (INTTM01n) is generated. The count value of TM0n is not cleared. When this register is used as a capture register, the TI00n pin input is used as a capture trigger. When the valid edge of the capture trigger is detected, the count value of TM0n is stored in CR01n. Remark n = 0, 1 User's Manual U17397E4V0UD 219 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-44. Example of Software Processing in Free-Running Timer Mode FFFFH M TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Compare register (CR00n) Compare match interrupt (INTTM00n) Compare register (CR01n) Compare match interrupt (INTTM01n) Timer output control bits (TOE0n, TOC0n4, TOC0n1) TO0n pin output N N M N M N 00 01 M 00 N <1> <1> Count operation start flow START <2> Register initial setting PRM0n register, CRC0n register, TOC0n registerNote, CR00n/CR01n register, TMC0n.TMC0n1 bit, port setting Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits to 01. TMC0n3, TMC0n2 bits = 0, 1 Starts count operation <2> Count operation stop flow TMC0n3, TMC0n2 bits = 0, 0 The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to 00. STOP Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control register 0n (TOC0n). Remark n = 0, 1 220 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com 7.4.6 PPG output operation A square wave having a pulse width set in advance by CR01n is output from the TO0n pin as a PPG (Programmable Pulse Generator) signal during a cycle set by CR00n when bits 3 and 2 (TMC0n3 and TMC0n2) of 16bit timer mode control register 0n (TMC0n) are set to 11 (clear & start upon a match between TM0n and CR00n). The pulse cycle and duty factor of the pulse generated as the PPG output are as follows. * Pulse cycle = (Set value of CR00n + 1) x Count clock cycle * Duty = (Set value of CR01n + 1) / (Set value of CR00n + 1) Caution To change the duty factor (value of CR01n) during operation, see 7.5.1 Rewriting CR01n during TM0n operation. Remarks 1. For the setting of I/O pins, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS. Figure 7-45. Block Diagram of PPG Output Operation Clear Count clock Timer counter (TM0n) Match signal Operable bits TMC0n3, TMC0n2 Compare register (CR00n) Match signal Output controller Interrupt signal (INTTM00n) TO0n pin Interrupt signal (INTTM01n) Compare register (CR01n) Remark n = 0, 1 User's Manual U17397E4V0UD 221 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-46. Example of Register Settings for PPG Output Operation (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 0 0 0 0 1 1 0 OVF0n 0 Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 0 0 0 0 0 0 0 0 CR00n used as compare register CR01n used as compare register (c) 16-bit timer output control register 0n (TOC0n) OSPT0n OSPE0n TOC0n4 0 0 0 1 LVS0n 0/1 LVR0n 0/1 TOC0n1 1 TOE0n 1 Enables TO0n output Specifies initial value of TO0n output F/F 11: Inverts TO0n output on match between TM0n and CR00n/CR01n. 00: Disables one-shot pulse output (d) Prescaler mode register 0n (PRM0n) ES1n1 0 ES1n0 0 ES0n1 0 ES0n0 0 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock (e) 16-bit timer counter 0n (TM0n) By reading TM0n, the count value can be read. (f) 16-bit capture/compare register 00n (CR00n) An interrupt signal (INTTM00n) is generated when the value of this register matches the count value of TM0n. The count value of TM0n is not cleared. (g) 16-bit capture/compare register 01n (CR01n) An interrupt signal (INTTM01n) is generated when the value of this register matches the count value of TM0n. The count value of TM0n is not cleared. Caution Set values to CR00n and CR01n such that the condition 0000H CR01n < CR00n FFFFH is satisfied. Remark n = 0, 1 User's Manual U17397E4V0UD 222 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-47. Example of Software Processing for PPG Output Operation M TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Compare register (CR00n) Compare match interrupt (INTTM00n) Compare register (CR01n) Compare match interrupt (INTTM01n) Timer output control bits (TOE0n, TOC0n4, TOC0n1) TO0n pin output N+1 M+1 N+1 M+1 N+1 M+1 N N M N M 00 11 M 00 N <1> <1> Count operation start flow <2> Count operation stop flow <2> START TMC0n3, TMC0n2 bits = 00 The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to 00. Register initial setting PRM0n register, CRC0n register, TOC0n registerNote, CR00n, CR01n registers, port setting Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits. STOP TMC0n3, TMC0n2 bits = 11 Starts count operation Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control register 0n (TOC0n). Remarks 1. PPG pulse cycle = (M + 1) x Count clock cycle PPG duty = (N + 1)/(M + 1) 2. n = 0, 1 User's Manual U17397E4V0UD 223 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com 7.4.7 One-shot pulse output operation A one-shot pulse can be output by setting bits 3 and 2 (TMC0n3 and TMC0n2) of the 16-bit timer mode control register 0n (TMC0n) to 01 (free-running timer mode) or to 10 (clear & start mode entered by the TI00n pin valid edge) and setting bit 5 (OSPE0n) of 16-bit timer output control register 0n (TOC0n) to 1. When bit 6 (OSPT0n) of TOC0n is set to 1 or when the valid edge is input to the TI00n pin during timer operation, clearing & starting of TM0n is triggered, and a pulse of the difference between the values of CR00n and CR01n is output only once from the TO0n pin. Cautions 1. Do not input the trigger again (setting OSPT0n to 1 or detecting the valid edge of the TI00n pin) while the one-shot pulse is output. To output the one-shot pulse again, generate the trigger after the current one-shot pulse output has completed. 2. To use only the setting of OSPT0n to 1 as the trigger of one-shot pulse output, do not change the level of the TI00n pin or its alternate function port pin. Otherwise, the pulse will be unexpectedly output. Remarks 1. For the setting of the I/O pins, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS. Figure 7-48. Block Diagram of One-Shot Pulse Output Operation TI00n edge detection OSPT0n bit OSPE0n bit Count clock Timer counter (TM0n) Match signal Operable bits TMC0n3, TMC0n2 Compare register (CR00n) Match signal Output controller Interrupt signal (INTTM00n) TO0n pin Interrupt signal (INTTM01n) Clear Compare register (CR01n) Remark n = 0, 1 224 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-49. Example of Register Settings for One-Shot Pulse Output Operation (1/2) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 0 0 0 0 0/1 0/1 0 OVF0n 0 01: Free running timer mode 10: Clear and start mode by valid edge of TI00n pin. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 0 0 0 0 0 0 0 0 CR00n used as compare register CR01n used as compare register (c) 16-bit timer output control register 0n (TOC0n) OSPT0n OSPE0n TOC0n4 0 0/1 1 1 LVS0n 0/1 LVR0n 0/1 TOC0n1 1 TOE0n 1 Enables TO0n pin output Specifies initial value of TO0n pin output Inverts TO0n output on match between TM0n and CR00n/CR01n. Enables one-shot pulse output Software trigger is generated by writing 1 to this bit (operation is not affected even if 0 is written to it). (d) Prescaler mode register 0n (PRM0n) ES1n1 0 ES1n0 0 ES0n1 0 ES0n0 0 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock Remark n = 0, 1 User's Manual U17397E4V0UD 225 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-49. Example of Register Settings for One-Shot Pulse Output Operation (2/2) (e) 16-bit timer counter 0n (TM0n) By reading TM0n, the count value can be read. (f) 16-bit capture/compare register 00n (CR00n) This register is used as a compare register when a one-shot pulse is output. When the value of TM0n matches that of CR00n, an interrupt signal (INTTM00n) is generated and the output level of the TO0n pin is inverted. (g) 16-bit capture/compare register 01n (CR01n) This register is used as a compare register when a one-shot pulse is output. When the value of TM0n matches that of CR01n, an interrupt signal (INTTM01n) is generated and the output level of the TO0n pin is inverted. Caution Do not set the same value to CR0n0 and CR0n1. Remark n = 0, 1 226 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-50. Example of Software Processing for One-Shot Pulse Output Operation (1/2) FFFFH N TM0n register 0000H Operable bits (TMC0n3, TMC0n2) N M M N M 00 01 or 10 00 One-shot pulse enable bit (OSPEn) One-shot pulse trigger bit (OSPTn) One-shot pulse trigger input (TI00n pin) Overflow plug (OVF0n) Compare register (CR00n) Compare match interrupt (INTTM00n) Compare register (CR01n) Compare match interrupt (INTTM01n) TO0n pin output M+1 TO0n output control bits (TOE0n, TOC0n4, TOC0n1) <1> <2> N-M M+1 N-M M N TO0n output level is not inverted because no oneshot trigger is input. <2> <3> * Time from when the one-shot pulse trigger is input until the one-shot pulse is output = (M + 1) x Count clock cycle * One-shot pulse output active level width = (N - M) x Count clock cycle Remark n = 0, 1 User's Manual U17397E4V0UD 227 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-50. Example of Software Processing for One-Shot Pulse Output Operation (2/2) <1> Count operation start flow START Register initial setting PRM0n register, CRC0n register, TOC0n registerNote, CR00n, CR01n registers, port setting Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits. TMC0n3, TMC0n2 bits = 01 or 10 Starts count operation <2> One-shot trigger input flow TOC0n.OSPT0n bit = 1 or edge input to TI00n pin Write the same value to the bits other than the OSTP0n bit. <3> Count operation stop flow TMC0n3, TMC0n2 bits = 00 The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to 00. STOP Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control register 0n (TOC0n). Remark n = 0, 1 228 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com 7.4.8 Pulse width measurement operation TM0n can be used to measure the pulse width of the signal input to the TI00n and TI01n pins. Measurement can be accomplished by operating the 16-bit timer/event counter 0n in the free-running timer mode or by restarting the timer in synchronization with the signal input to the TI00n pin. When an interrupt is generated, read the value of the valid capture register and measure the pulse width. Check bit 0 (OVF0n) of 16-bit timer mode control register 0n (TMC0n). If it is set (to 1), clear it to 0 by software. Figure 7-51. Block Diagram of Pulse Width Measurement (Free-Running Timer Mode) Operable bits TMC0n3, TMC0n2 Timer counter (TM0n) Count clock Capture signal Capture register (CR01n) Interrupt signal (INTTM01n) Selector TI00n pin TI01n pin Edge detection Edge detection Capture signal Capture register (CR00n) Interrupt signal (INTTM00n) Remark n = 0, 1 Figure 7-52. Block Diagram of Pulse Width Measurement (Clear & Start Mode Entered by TI00n Pin Valid Edge Input) Operable bits TMC0n3, TMC0n2 Clear Timer counter (TM0n) Count clock Capture signal Capture register (CR01n) Interrupt signal (INTTM01n) Selector TI00n pin TI01n pin Edge detection Edge detection Capture signal Capture register (CR00n) Interrupt signal (INTTM00n) Remark n = 0, 1 User's Manual U17397E4V0UD 229 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com A pulse width can be measured in the following three ways. * Measuring the pulse width by using two input signals of the TI00n and TI01n pins (free-running timer mode) * Measuring the pulse width by using one input signal of the TI00n pin (free-running timer mode) * Measuring the pulse width by using one input signal of the TI00n pin (clear & start mode entered by the TI00n pin valid edge input) Remarks 1. For the setting of the I/O pins, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS. 3. n = 0, 1 (1) Measuring the pulse width by using two input signals of the TI00n and TI01n pins (free-running timer mode) Set the free-running timer mode (TMC0n3 and TMC0n2 = 01). When the valid edge of the TI00n pin is detected, the count value of TM0n is captured to CR01n. When the valid edge of the TI01n pin is detected, the count value of TM0n is captured to CR00n. Specify detection of both the edges of the TI00n and TI01n pins. By this measurement method, the previous count value is subtracted from the count value captured by the edge of each input signal. Therefore, save the previously captured value to a separate register in advance. If an overflow occurs, the value becomes negative if the previously captured value is simply subtracted from the current captured value and, therefore, a borrow occurs (bit 0 (CY) of the program status word (PSW) is set to 1). If this happens, ignore CY and take the calculated value as the pulse width. In addition, clear bit 0 (OVF0n) of 16-bit timer mode control register 0n (TMC0n) to 0. Figure 7-53. Timing Example of Pulse Width Measurement (1) * TMC0n = 04H, PRM0n = F0H, CRC0n = 05H FFFFH TM0n register A 0000H Operable bits (TMC0n3, TMC0n2) Capture trigger input (TI00n) Capture register (CR01n) Capture interrupt (INTTM01n) Capture trigger input (TI01n) Capture register (CR00n) Capture interrupt (INTTM00n) Overflow flag (OVF0n) 0 write clear 0 write clear 0 write clear 0 write clear M B N C S D P E Q 00 01 0000H M N S P Q 0000H A B C D E Remark n = 0, 1 User's Manual U17397E4V0UD 230 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com (2) Measuring the pulse width by using one input signal of the TI00n pin (free-running mode) Set the free-running timer mode (TMC0n3 and TMC0n2 = 01). The count value of TM0n is captured to CR00n in the phase reverse to the valid edge detected on the TI00n pin. When the valid edge of the TI00n pin is detected, the count value of TM0n is captured to CR01n. By this measurement method, values are stored in separate capture registers when a width from one edge to another is measured. Therefore, the capture values do not have to be saved. By subtracting the value of one capture register from that of another, a high-level width, low-level width, and cycle are calculated. If an overflow occurs, the value becomes negative if one captured value is simply subtracted from another and, therefore, a borrow occurs (bit 0 (CY) of the program status word (PSW) is set to 1). If this happens, ignore CY and take the calculated value as the pulse width. In addition, clear bit 0 (OVF0n) of 16-bit timer mode control register 0n (TMC0n) to 0. Figure 7-54. Timing Example of Pulse Width Measurement (2) * TMC0n = 04H, PRM0n = 10H, CRC0n = 07H FFFFH TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Capture trigger input (TI00n) Capture register (CR00n) Capture register (CR01n) Capture interrupt (INTTM01n) Overflow flag (OVF0n) 0 write clear Capture trigger input (TI01n) Capture interrupt (INTTM00n) 0 write clear 0 write clear 0 write clear M A B N C S D P E Q 00 01 0000H 0000H A M B N C S D P E Q L L Remark n = 0, 1 User's Manual U17397E4V0UD 231 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com (3) Measuring the pulse width by using one input signal of the TI00n pin (clear & start mode entered by the TI00n pin valid edge input) Set the clear & start mode entered by the TI00n pin valid edge (TMC0n3 and TMC0n2 = 10). The count value of TM0n is captured to CR00n in the phase reverse to the valid edge of the TI00n pin, and the count value of TM0n is captured to CR01n and TM0n is cleared (0000H) when the valid edge of the TI00n pin is detected. Therefore, a cycle is stored in CR01n if TM0n does not overflow. If an overflow occurs, take the value that results from adding 10000H to the value stored in CR01n as a cycle. Clear bit 0 (OVF0n) of 16-bit timer mode control register 0n (TMC0n) to 0. Figure 7-55. Timing Example of Pulse Width Measurement (3) * TMC0n = 08H, PRM0n = 10H, CRC0n = 07H FFFFH TM0n register 0000H Operable bits 00 (TMC0n3, TMC0n2) Capture & count clear input (TI00n) <2> Capture register (CR00n) Capture register (CR01n) Capture interrupt (INTTM01n) Overflow flag (OVF0n) 0 write clear Capture trigger input (TI01n) L Capture interrupt (INTTM00n) L <3> <2> <3> <2> <3> <2> <3> M A N P C S D Q B 10 <1> <1> <1> <1> 00 0000H 0000H M A N B S C P D Q <1> <2> <3> Pulse cycle = (10000H x Number of times OVF0n bit is set to 1 + Captured value of CR01n) x Count clock cycle High-level pulse width = (10000H x Number of times OVF0n bit is set to 1 + Captured value of CR00n) x Count clock cycle Low-level pulse width = (Pulse cycle - High-level pulse width) n = 0, 1 Remark 232 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-56. Example of Register Settings for Pulse Width Measurement (1/2) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 0 0 0 0 0/1 0/1 0 OVF0n 0 01: Free running timer mode 10: Clear and start mode entered by valid edge of TI00n pin. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 0 0 0 0 0 1 0/1 1 1: CR00n used as capture register 0: TI01n pin is used as capture trigger of CR00n. 1: Reverse phase of TI00n pin is used as capture trigger of CR00n. 1: CR01n used as capture register (c) 16-bit timer output control register 0n (TOC0n) OSPT0n OSPE0n TOC0n4 0 0 0 0 LVS0n 0 LVR0n 0 TOC0n1 0 TOE0n 0 (d) Prescaler mode register 0n (PRM0n) ES1n1 0/1 ES1n0 0/1 ES0n1 0/1 ES0n0 0/1 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock (setting valid edge of TI00n is prohibited) 00: Falling edge detection 01: Rising edge detection 10: Setting prohibited 11: Both edges detection (setting when CRC0n1 = 1 is prohibited) 00: Falling edge detection 01: Rising edge detection 10: Setting prohibited 11: Both edges detection Remark n = 0, 1 User's Manual U17397E4V0UD 233 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-56. Example of Register Settings for Pulse Width Measurement (2/2) (e) 16-bit timer counter 0n (TM0n) By reading TM0n, the count value can be read. (f) 16-bit capture/compare register 00n (CR00n) This register is used as a capture register. Either the TI00n or TI01n pin is selected as a capture trigger. When a specified edge of the capture trigger is detected, the count value of TM0n is stored in CR00n. (g) 16-bit capture/compare register 01n (CR01n) This register is used as a capture register. The signal input to the TI00n pin is used as a capture trigger. When the capture trigger is detected, the count value of TM0n is stored in CR01n. Remark n = 0, 1 234 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-57. Example of Software Processing for Pulse Width Measurement (1/2) (a) Example of free-running timer mode FFFFH D10 TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Capture trigger input (TI00n) Capture register (CR01n) Capture interrupt (INTTM01n) Capture trigger input (TI01n) Capture register (CR00n) Capture interrupt (INTTM00n) D00 D01 D11 D02 D12 D03 D13 D04 00 01 00 0000H D10 D11 D12 D13 0000H D00 D01 D02 D03 D04 <1> <2> <2> <2> <2> <2> <2> <2> <2> <2><3> (b) Example of clear & start mode entered by TI00n pin valid edge FFFFH TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Capture & count clear input (TI00n) Capture register 0000H (CR00n) Capture interrupt (INTTM00n) L D0 D2 D4 D6 D8 D1 D3 D5 D7 D0 D1 D4 D2 D3 D6 D8 D7 D5 00 10 00 Capture register (CR01n) 0000H Capture interrupt (INTTM01n) <1> <2> <2> <2> <2> <2> <2> <2> <2> <2> <3> Remark n = 0, 1 User's Manual U17397E4V0UD 235 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com Figure 7-57. Example of Software Processing for Pulse Width Measurement (2/2) <1> Count operation start flow START Register initial setting PRM0n register, CRC0n register, port setting Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits. TMC0n3, TMC0n2 bits = 01 or 10 Starts count operation <2> Capture trigger input flow Edge detection of TI00n, TI01n pins Stores count value to CR00n, CR01n registers Generates capture interruptNote Calculated pulse width from capture value <3> Count operation stop flow TMC0n3, TMC0n2 bits = 00 The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to 00. STOP Note The capture interrupt signal (INTTM00n) is not generated when the reverse-phase edge of the TI00n pin input is selected to the valid edge of CR00n. Remark n = 0, 1 236 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com 7.5 Special Use of TM0n 7.5.1 Rewriting CR01n during TM0n operation In principle, rewriting CR00n and CR01n of the 78K0/KF2 when they are used as compare registers is prohibited while TM0n is operating (TMC0n3 and TMC0n2 = other than 00). However, the value of CR01n can be changed, even while TM0n is operating, using the following procedure if CR01n is used for PPG output and the duty factor is changed (change the value of CR01n immediately after its value matches the value of TM0n. If the value of CR01n is changed immediately before its value matches TM0n, an unexpected operation may be performed). Procedure for changing value of CR01n <1> Disable interrupt INTTM01n (TMMK01n = 1). <2> Disable reversal of the timer output when the value of TM0n matches that of CR01n (TOC0n4 = 0). <3> Change the value of CR01n. <4> Wait for one cycle of the count clock of TM0n. <5> Enable reversal of the timer output when the value of TM0n matches that of CR01n (TOC0n4 = 1). <6> Clear the interrupt flag of INTTM01n (TMIF01n = 0) to 0. <7> Enable interrupt INTTM01n (TMMK01n = 0). Remark For TMIF01n and TMMK01n, see CHAPTER 20 INTERRUPT FUNCTIONS. 7.5.2 Setting LVS0n and LVR0n (1) Usage of LVS0n and LVR0n LVS0n and LVR0n are used to set the default value of the TO0n pin output and to invert the timer output without enabling the timer operation (TMC0n3 and TMC0n2 = 00). Clear LVS0n and LVR0n to 00 (default value: lowlevel output) when software control is unnecessary. LVS0n 0 0 1 1 LVR0n 0 1 0 1 Timer Output Status Not changed (low-level output) Cleared (low-level output) Set (high-level output) Setting prohibited Remark n = 0, 1 User's Manual U17397E4V0UD 237 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com (2) Setting LVS0n and LVR0n Set LVS0n and LVR0n using the following procedure. Figure 7-58. Example of Flow for Setting LVS0n and LVR0n Bits Setting TOC0n.OSPE0n, TOC0n4, TOC0n1 bits <1> Setting of timer output operation Setting TOC0n.TOE0n bit Setting TOC0n.LVS0n, LVR0n bits Setting TMC0n.TMC0n3, TMC0n2 bits <2> Setting of timer output F/F <3> Enabling timer operation Caution Be sure to set LVS0n and LVR0n following steps <1>, <2>, and <3> above. Step <2> can be performed after <1> and before <3>. Figure 7-59. Timing Example of LVR0n and LVS0n TOC0n.LVS0n bit TOC0n.LVR0n bit Operable bits (TMC0n3, TMC0n2) TO0n pin output INTTM00n signal <1> <2> <1> <3> <4> <4> <4> 00 01, 10, or 11 <1> The TO0n pin output goes high when LVS0n and LVR0n = 10. <2> The TO0n pin output goes low when LVS0n and LVR0n = 01 (the pin output remains unchanged from the high level even if LVS0n and LVR0n are cleared to 00). <3> The timer starts operating when TMC0n3 and TMC0n2 are set to 01, 10, or 11. Because LVS0n and LVR0n were set to 10 before the operation was started, the TO0n pin output starts from the high level. After the timer starts operating, setting LVS0n and LVR0n is prohibited until TMC0n3 and TMC0n2 = 00 (disabling the timer operation). <4> The output level of the TO0n pin is inverted each time an interrupt signal (INTTM00n) is generated. Remark n = 0, 1 238 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com 7.6 Cautions for 16-Bit Timer/Event Counters 00 and 01 (1) Restrictions for each channel of 16-bit timer/event counter 0n Table 7-5 shows the restrictions for each channel. Table 7-5. Restrictions for Each Channel of 16-Bit Timer/Event Counter 0n Operation As interval timer As square-wave output As external event counter As clear & start mode entered by TI00n pin valid edge input As free-running timer As PPG output As one-shot pulse output As pulse width measurement 0000H CP01n < CR00n FFFFH Setting the same value to CR00n and CP01n is prohibited. Using timer output (TO0n) is prohibited (TOC0n = 00H) Using timer output (TO0n) is prohibited when detection of the valid edge of the TI01n pin is used. (TOC0n = 00H) - Restriction - (2) Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because counting TM0n is started asynchronously to the count pulse. Figure 7-60. Start Timing of TM0n Count Count pulse TM0n count value 0000H Timer start 0001H 0002H 0003H 0004H (3) Setting of CR00n and CR01n (clear & start mode entered upon a match between TM0n and CR00n) Set a value other than 0000H to CR00n and CR01n (TM0n cannot count one pulse when it is used as an external event counter). Remark n = 0, 1 User's Manual U17397E4V0UD 239 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com (4) Timing of holding data by capture register (a) When the valid edge is input to the TI00n/TI01n pin and the reverse phase of the TI00n pin is detected while CR00n/CR01n is read, CR01n performs a capture operation but the read value of CR00n/CR01n is not guaranteed. At this time, an interrupt signal (INTTM00n/INTTM01n) is generated when the valid edge of the TI00n/TI01n pin is detected (the interrupt signal is not generated when the reverse-phase edge of the TI00n pin is detected). When the count value is captured because the valid edge of the TI00n/TI01n pin was detected, read the value of CR00n/CR01n after INTTM00n/INTTM01n is generated. Figure 7-61. Timing of Holding Data by Capture Register Count pulse TM0n count value Edge input INTTM01n Capture read signal Value captured to CR01n X Capture operation N+1 Capture operation is performed but read value is not guaranteed. N N+1 N+2 M M+1 M+2 (b) The values of CR00n and CR01n are not guaranteed after 16-bit timer/event counter 0n stops. (5) Setting valid edge Set the valid edge of the TI00n pin while the timer operation is stopped (TMC0n3 and TMC0n2 = 00). Set the valid edge by using ES0n0 and ES0n1. (6) Re-triggering one-shot pulse Make sure that the trigger is not generated while an active level is being output in the one-shot pulse output mode. Be sure to input the next trigger after the current active level is output. Remark n = 0, 1 240 User's Manual U17397E4V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com (7) Operation of OVF0n flag (a) Setting OVF0n flag (1) The OVF0n flag is set to 1 in the following case, as well as when TM0n overflows. Select the clear & start mode entered upon a match between TM0n and CR00n. Set CR00n to FFFFH. When TM0n matches CR00n and TM0n is cleared from FFFFH to 0000H Figure 7-62. Operation Timing of OVF0n Flag Count pulse CR00n TM0n OVF0n INTTM00n FFFFH FFFEH FFFFH 0000H 0001H (b) Clearing OVF0n flag Even if the OVF0n flag is cleared to 0 after TM0n overflows and before the next count clock is counted (before the value of TM0n becomes 0001H), it is set to 1 again and clearing is invalid. (8) One-shot pulse output One-shot pulse output operates correctly in the free-running timer mode or the clear & start mode entered by the TI00n pin valid edge. The one-shot pulse cannot be output in the clear & start mode entered upon a match between TM0n and CR00n. Remark n = 0, 1 User's Manual U17397E4V0UD 241 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 www..com (9) Capture operation (a) When valid edge of TI00n is specified as count clock When the valid edge of TI00n is specified as the count clock, the capture register for which TI00n is specified as a trigger does not operate correctly. (b) Pulse width to accurately capture value by signals input to TI01n and TI00n pins To accurately capture the count value, the pulse input to the TI00n and TI01n pins as a capture trigger must be wider than two count clocks selected by PRM0n (see Figure 7-9). (c) Generation of interrupt signal The capture operation is performed at the falling edge of the count clock but the interrupt signals (INTTM00n and INTTM01n) are generated at the rising edge of the next count clock (see Figure 7-9). (d) Note when CRC0n1 (bit 1 of capture/compare control register 0n (CRC0n)) is set to 1 When the count value of the TM0n register is captured to the CR00n register in the phase reverse to the signal input to the TI00n pin, the interrupt signal (INTTM00n) is not generated after the count value is captured. If the valid edge is detected on the TI01n pin during this operation, the capture operation is not performed but the INTTM00n signal is generated as an external interrupt signal. Mask the INTTM00n signal when the external interrupt is not used. (10) Edge detection (a) Specifying valid edge after reset If the operation of the 16-bit timer/event counter 0n is enabled after reset and while the TI00n or TI01n pin is at high level and when the rising edge or both the edges are specified as the valid edge of the TI00n or TI01n pin, then the high level of the TI00n or TI01n pin is detected as the rising edge. Note this when the TI00n or TI01n pin is pulled up. However, the rising edge is not detected when the operation is once stopped and then enabled again. (b) Sampling clock for eliminating noise The sampling clock for eliminating noise differs depending on whether the valid edge of TI00n is used as the count clock or capture trigger. In the former case, the sampling clock is fixed to fPRS. In the latter, the count clock selected by PRM0n is used for sampling. When the signal input to the TI00n pin is sampled and the valid level is detected two times in a row, the valid edge is detected. Therefore, noise having a short pulse width can be eliminated (see Figure 7-9). (11) Timer operation The signal input to the TI00n/TI01n pin is not acknowledged while the timer is stopped, regardless of the operation mode of the CPU. Remarks 1. fPRS: Peripheral hardware clock frequency 2. n = 0, 1 242 User's Manual U17397E4V0UD www..com CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.1 Functions of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 have the following functions. * Interval timer * External event counter * Square-wave output * PWM output 8.2 Configuration of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 include the following hardware. Table 8-1. Configuration of 8-Bit Timer/Event Counters 50 and 51 Item Timer register Register Timer input Timer output Control registers 8-bit timer counter 5n (TM5n) 8-bit timer compare register 5n (CR5n) TI5n TO5n Timer clock selection register 5n (TCL5n) 8-bit timer mode control register 5n (TMC5n) Port mode register 1 (PM1) or port mode register 3 (PM3) Port register 1 (P1) or port register 3 (P3) Configuration Figures 8-1 and 8-2 show the block diagrams of 8-bit timer/event counters 50 and 51. User's Manual U17397E4V0UD 243 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 www..com Figure 8-1. Block Diagram of 8-Bit Timer/Event Counter 50 Internal bus Mask circuit 8-bit timer compare register 50 (CR50) TI50/TO50/P17 fPRS fPRS/2 fPRS/22 fPRS/26 fPRS/28 fPRS/213 Match Selector Selector Note 1 INTTM50 To TMH0 To UART0 To UART6 TO50/TI50/ P17 Output latch (P17) PM17 8-bit timer OVF counter 50 (TM50) R Note 2 3 Clear S R Invert level TCL502 TCL501 TCL500 Timer clock selection register 50 (TCL50) TCE50 TMC506 LVS50 LVR50 TMC501 TOE50 8-bit timer mode control register 50 (TMC50) Internal bus Figure 8-2. Block Diagram of 8-Bit Timer/Event Counter 51 Internal bus Mask circuit 8-bit timer compare register 51 (CR51) TI51/TO51/ P33/INTP4 fPRS fPRS/2 fPRS/24 fPRS/26 fPRS/28 fPRS/212 Match Selector Selector Note 1 INTTM51 8-bit timer OVF counter 51 (TM51) Selector S Q INV R Note 2 Selector S Q INV TO51/TI51/ P33/INTP4 Output latch (P33) PM33 3 Clear S R Invert level TCL512 TCL511 TCL510 Timer clock selection register 51 (TCL51) TCE51 TMC516 LVS51 LVR51 TMC511 TOE51 8-bit timer mode control register 51 (TMC51) Internal bus Notes 1. 2. Timer output F/F PWM output F/F 244 User's Manual U17397E4V0UD CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 www..com (1) 8-bit timer counter 5n (TM5n) TM5n is an 8-bit register that counts the count pulses and is read-only. The counter is incremented in synchronization with the rising edge of the count clock. Figure 8-3. Format of 8-Bit Timer Counter 5n (TM5n) Address: FF16H (TM50), FF1FH (TM51) Symbol TM5n (n = 0, 1) After reset: 00H R In the following situations, the count value is cleared to 00H. <1> Reset signal generation <2> When TCE5n is cleared <3> When TM5n and CR5n match in the mode in which clear & start occurs upon a match of the TM5n and CR5n. (2) 8-bit timer compare register 5n (CR5n) CR5n can be read and written by an 8-bit memory manipulation instruction. Except in PWM mode, the value set in CR5n is constantly compared with the 8-bit timer counter 5n (TM5n) count value, and an interrupt request (INTTM5n) is generated if they match. In the PWM mode, the TO5n pin becomes inactive when the values of TM5n and CR5n match, but no interrupt is generated. The value of CR5n can be set within 00H to FFH. Reset signal generation clears CR5n to 00H. Figure 8-4. Format of 8-Bit Timer Compare Register 5n (CR5n) Address: FF17H (CR50), FF41H (CR51) Symbol CR5n (n = 0, 1) After reset: 00H R/W Cautions 1. In the mode in which clear & start occurs on a match of TM5n and CR5n (TMC5n6 = 0), do not write other values to CR5n during operation. 2. In PWM mode, make the CR5n rewrite period 3 count clocks of the count clock (clock selected by TCL5n) or more. Remark n = 0, 1 User's Manual U17397E4V0UD 245 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 www..com 8.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 The following four registers are used to control 8-bit timer/event counters 50 and 51. * Timer clock selection register 5n (TCL5n) * 8-bit timer mode control register 5n (TMC5n) * Port mode register 1 (PM1) or port mode register 3 (PM3) * Port register 1 (P1) or port register 3 (P3) (1) Timer clock selection register 5n (TCL5n) This register sets the count clock of 8-bit timer/event counter 5n and the valid edge of the TI5n pin input. TCL5n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears TCL5n to 00H. Remark n = 0, 1 Figure 8-5. Format of Timer Clock Selection Register 50 (TCL50) Address: FF6AH Symbol TCL50 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 TCL502 1 TCL501 0 TCL500 TCL502 TCL501 TCL500 fPRS = Count clock selection fPRS = 5 MHz fPRS = 10 MHz fPRS = 20 MHz 2 MHz 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 TI50 pin falling edge TI50 pin rising edge fPRS fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 2 2 MHz 1 MHz 500 kHz 31.25 kHz 7.81 kHz 0.24 kHz 5 MHz 2.5 MHz 1.25 MHz 78.13 kHz 19.53 kHz 0.61 kHz 10 MHz 5 MHz 2.5 MHz 20 MHz 10 MHz 5 MHz 6 156.25 kHz 312.5 kHz 39.06 kHz 1.22 kHz 78.13 kHz 2.44 kHz 8 13 Cautions 1. When rewriting TCL50 to other data, stop the timer operation beforehand. 2. Be sure to clear bits 3 to 7 to "0". Remark fPRS: Peripheral hardware clock frequency 246 User's Manual U17397E4V0UD CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 www..com Figure 8-6. Format of Timer Clock Selection Register 51 (TCL51) Address: FF8CH Symbol TCL51 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 TCL512 1 TCL511 0 TCL510 TCL512 TCL511 TCL510 fPRS = Count clock selection fPRS = 5 MHz fPRS = 10 MHz fPRS = 20 MHz 2 MHz 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 TI51 pin falling edge TI51 pin rising edge fPRS fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 4 2 MHz 1 MHz 125 kHz 31.25 kHz 7.81 kHz 0.49 kHz 5 MHz 2.5 MHz 312.5 kHz 78.13 kHz 19.53 kHz 1.22 kHz 10 MHz 5 MHz 625 kHz 20 MHz 10 MHz 1.25 MHz 6 156.25 kHz 312.5 kHz 39.06 kHz 2.44 kHz 78.13 kHz 4.88 kHz 8 12 Cautions 1. When rewriting TCL51 to other data, stop the timer operation beforehand. 2. Be sure to clear bits 3 to 7 to "0". Remark fPRS: Peripheral hardware clock frequency User's Manual U17397E4V0UD 247 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 www..com (2) 8-bit timer mode control register 5n (TMC5n) TMC5n is a register that performs the following five types of settings. <1> 8-bit timer counter 5n (TM5n) count operation control <2> 8-bit timer counter 5n (TM5n) operating mode selection <3> Timer output F/F (flip flop) status setting <4> Active level selection in timer F/F control or PWM (free-running) mode. <5> Timer output control TMC5n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Remark n = 0, 1 Figure 8-7. Format of 8-Bit Timer Mode Control Register 50 (TMC50) Address: FF6BH Symbol TMC50 After reset: 00H <7> TCE50 6 TMC506 R/W Note 5 0 4 0 <3> LVS50 <2> LVR50 1 TMC501 <0> TOE50 TCE50 0 1 TM50 count operation control After clearing to 0, count operation disabled (counter stopped) Count operation start TMC506 0 1 TM50 operating mode selection Mode in which clear & start occurs on a match between TM50 and CR50 PWM (free-running) mode LVS50 0 0 1 1 LVR50 0 1 0 1 No change Timer output F/F status setting Timer output F/F clear (0) (default output value of TO50 pin: low level) Timer output F/F set (1) (default output value of TO50 pin: high level) Setting prohibited TMC501 In other modes (TMC506 = 0) Timer F/F control In PWM mode (TMC506 = 1) Active level selection Active-high Active-low 0 1 Inversion operation disabled Inversion operation enabled TOE50 0 1 Timer output control Output disabled (TM50 output is low level) Output enabled Note Bits 2 and 3 are write-only. (Cautions and Remarks are listed on the next page.) 248 User's Manual U17397E4V0UD CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 www..com Figure 8-8. Format of 8-Bit Timer Mode Control Register 51 (TMC51) Address: FF43H Symbol TMC51 After reset: 00H <7> TCE51 6 TMC516 R/W Note 5 0 4 0 <3> LVS51 <2> LVR51 1 TMC511 <0> TOE51 TCE51 0 1 TM51 count operation control After clearing to 0, count operation disabled (counter stopped) Count operation start TMC516 0 1 TM51 operating mode selection Mode in which clear & start occurs on a match between TM51 and CR51 PWM (free-running) mode LVS51 0 0 1 1 LVR51 0 1 0 1 No change Timer output F/F status setting Timer output F/F clear (0) (default output value of TO51 pin: low) Timer output F/F set (1) (default output value of TO51 pin: high) Setting prohibited TMC511 In other modes (TMC516 = 0) Timer F/F control In PWM mode (TMC516 = 1) Active level selection Active-high Active-low 0 1 Inversion operation disabled Inversion operation enabled TOE51 0 1 Timer output control Output disabled (TM51 output is low level) Output enabled Note Bits 2 and 3 are write-only. Cautions 1. The settings of LVS5n and LVR5n are valid in other than PWM mode. 2. Perform <1> to <4> below in the following order, not at the same time. <1> Set TMC5n1, TMC5n6: <2> Set TOE5n to enable output: <4> Set TCE5n 3. When TCE5n = 1, setting the other bits of TMC5n is prohibited. Remarks 1. In PWM mode, PWM output is made inactive by clearing TCE5n to 0. 2. If LVS5n and LVR5n are read, the value is 0. 3. The values of the TMC5n6, LVS5n, LVR5n, TMC5n1, and TOE5n bits are reflected at the TO5n pin regardless of the value of TCE5n. 4. n = 0, 1 Operation mode setting Timer output enable <3> Set LVS5n, LVR5n (see Caution 1): Timer F/F setting User's Manual U17397E4V0UD 249 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 www..com (3) Port mode registers 1 and 3 (PM1, PM3) These registers set port 1 and 3 input/output in 1-bit units. When using the P17/TO50/TI50 and P33/TO51/TI51/INTP4 pins for timer output, clear PM17 and PM33 and the output latches of P17 and P33 to 0. When using the P17/TO50/TI50 and P33/TO51/TI51/INTP4 pins for timer input, set PM17 and PM33 to 1. The output latches of P17 and P33 at this time may be 0 or 1. PM1 and PM3 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Figure 8-9. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol PM1 7 PM17 After reset: FFH 6 PM16 R/W 5 PM15 4 PM14 3 PM13 2 PM12 1 PM11 0 PM10 PM1n 0 1 P1n pin I/O mode selection (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off) Figure 8-10. Format of Port Mode Register 3 (PM3) Address: FF23H Symbol PM3 7 1 After reset: FFH 6 1 R/W 5 1 4 1 3 PM33 2 PM32 1 PM31 0 PM30 PM3n 0 1 P3n pin I/O mode selection (n = 0 to 3) Output mode (output buffer on) Input mode (output buffer off) 250 User's Manual U17397E4V0UD CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 www..com 8.4 Operations of 8-Bit Timer/Event Counters 50 and 51 8.4.1 Operation as interval timer 8-bit timer/event counter 5n operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 5n (CR5n). When the count value of 8-bit timer counter 5n (TM5n) matches the value set to CR5n, counting continues with the TM5n value cleared to 0 and an interrupt request signal (INTTM5n) is generated. The count clock of TM5n can be selected with bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock selection register 5n (TCL5n). Setting <1> Set the registers. * TCL5n: * CR5n: * TMC5n: Select the count clock. Compare value Stop the count operation, select the mode in which clear & start occurs on a match of TM5n and CR5n. (TMC5n = 0000xxx0B x = Don't care) <2> After TCE5n = 1 is set, the count operation starts. <3> If the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H). <4> INTTM5n is generated repeatedly at the same interval. Set TCE5n to 0 to stop the count operation. Caution Do not write other values to CR5n during operation. Remarks 1. For how to enable the INTTM5n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS. 2. n = 0, 1 Figure 8-11. Interval Timer Operation Timing (1/2) (a) Basic operation t Count clock TM5n count value 00H 01H N 00H 01H N 00H 01H N Count start CR5n TCE5n INTTM5n N Clear N Clear N N Interrupt acknowledged Interval time Interrupt acknowledged Interval time Remark Interval time = (N + 1) x t N = 01H to FFH n = 0, 1 User's Manual U17397E4V0UD 251 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 www..com Figure 8-11. Interval Timer Operation Timing (2/2) (b) When CR5n = 00H t Count clock TM5n 00H CR5n TCE5n INTTM5n Interval time 00H 00H 00H 00H (c) When CR5n = FFH t Count clock TM5n CR5n TCE5n INTTM5n Interrupt acknowledged Interval time Interrupt acknowledged FFH 01H FEH FFH FFH 00H FEH FFH FFH 00H Remark n = 0, 1 252 User's Manual U17397E4V0UD CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 www..com 8.4.2 Operation as external event counter The external event counter counts the number of external clock pulses to be input to the TI5n pin by 8-bit timer counter 5n (TM5n). TM5n is incremented each time the valid edge specified by timer clock selection register 5n (TCL5n) is input. Either the rising or falling edge can be selected. When the TM5n count value matches the value of 8-bit timer compare register 5n (CR5n), TM5n is cleared to 0 and an interrupt request signal (INTTM5n) is generated. Whenever the TM5n value matches the value of CR5n, INTTM5n is generated. Setting <1> Set each register. * Set the port mode register (PM17 or PM33)Note to 1. * TCL5n: Select TI5n pin input edge. TI5n pin falling edge TCL5n = 00H TI5n pin rising edge TCL5n = 01H * CR5n: Compare value CR5n, disable the timer F/F inversion operation, disable timer output. (TMC5n = 00000000B) <2> When TCE5n = 1 is set, the number of pulses input from the TI5n pin is counted. <3> When the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H). <4> After these settings, INTTM5n is generated each time the values of TM5n and CR5n match. Note 8-bit timer/event counter 50: PM17 8-bit timer/event counter 51: PM33 Remark For how to enable the INTTM5n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS. Figure 8-12. External Event Counter Operation Timing (with Rising Edge Specified) TI5n Count start TM5n count value CR5n INTTM5n 00H 01H 02H 03H 04H 05H N-1 N N 00H 01H 02H 03H * TMC5n: Stop the count operation, select the mode in which clear & start occurs on match of TM5n and Remark N = 00H to FFH n = 0, 1 User's Manual U17397E4V0UD 253 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 www..com 8.4.3 Square-wave output operation A square wave with any selected frequency is output at intervals determined by the value preset to 8-bit timer compare register 5n (CR5n). The TO5n pin output status is inverted at intervals determined by the count value preset to CR5n by setting bit 0 (TOE5n) of 8-bit timer mode control register 5n (TMC5n) to 1. This enables a square wave with any selected frequency to be output (duty = 50%). Setting <1> Set each register. * Clear the port output latch (P17 or P33)Note and port mode register (PM17 or PM33)Note to 0. * TCL5n: Select the count clock. * CR5n: Compare value CR5n. LVS5n 1 0 LVR5n 0 1 Timer Output F/F Status Setting Timer output F/F clear (0) (default output value of TO50 pin: low level) Timer output F/F set (1) (default output value of TO5n pin: high level) * TMC5n: Stop the count operation, select the mode in which clear & start occurs on a match of TM5n and Timer output enabled (TMC5n = 00001011B or 00000111B) <2> After TCE5n = 1 is set, the count operation starts. <3> The timer output F/F is inverted by a match of TM5n and CR5n. After INTTM5n is generated, TM5n is cleared to 00H. <4> After these settings, the timer output F/F is inverted at the same interval and a square wave is output from TO5n. The frequency is as follows. * Frequency = 1/2t (N + 1) (N: 00H to FFH) Note 8-bit timer/event counter 50: P17, PM17 8-bit timer/event counter 51: P33, PM33 Caution Do not write other values to CR5n during operation. Remarks 1. For how to enable the INTTM5n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS. 2. n = 0, 1 254 User's Manual U17397E4V0UD CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 www..com Figure 8-13. Square-Wave Output Operation Timing t Count clock TM5n count value 00H 01H 02H N-1 N 00H 01H 02H N-1 N 00H Count start CR5n N TO5nNote Note The initial value of TO5n output can be set by bits 2 and 3 (LVR5n, LVS5n) of 8-bit timer mode control register 5n (TMC5n). 8.4.4 PWM output operation 8-bit timer/event counter 5n operates as a PWM output when bit 6 (TMC5n6) of 8-bit timer mode control register 5n (TMC5n) is set to 1. The duty pulse determined by the value set to 8-bit timer compare register 5n (CR5n) is output from TO5n. Set the active level width of the PWM pulse to CR5n; the active level can be selected with bit 1 (TMC5n1) of TMC5n. The count clock can be selected with bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock selection register 5n (TCL5n). PWM output can be enabled/disabled with bit 0 (TOE5n) of TMC5n. Caution In PWM mode, make the CR5n rewrite period 3 count clocks of the count clock (clock selected by TCL5n) or more. Remark n = 0, 1 User's Manual U17397E4V0UD 255 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 www..com (1) PWM output basic operation Setting <1> Set each register. * Clear the port output latch (P17 or P33)Note and port mode register (PM17 or PM33)Note to 0. * TCL5n: Select the count clock. * CR5n: Compare value The timer output F/F is not changed. TMC5n1 0 1 Active-high Active-low Active Level Selection * TMC5n: Stop the count operation, select PWM mode. Timer output enabled (TMC5n = 01000001B or 01000011B) <2> The count operation starts when TCE5n = 1. Clear TCE5n to 0 to stop the count operation. Note 8-bit timer/event counter 50: P17, PM17 8-bit timer/event counter 51: P33, PM33 PWM output operation <1> PWM output (output from TO5n) outputs an inactive level until an overflow occurs. <2> When an overflow occurs, the active level is output. The active level is output until CR5n matches the count value of 8-bit timer counter 5n (TM5n). <3> After the CR5n matches the count value, the inactive level is output until an overflow occurs again. <4> Operations <2> and <3> are repeated until the count operation stops. <5> When the count operation is stopped with TCE5n = 0, PWM output becomes inactive. For details of timing, see Figures 8-14 and 8-15. The cycle, active-level width, and duty are as follows. * Cycle = 28t * Active-level width = Nt * Duty = N/28 (N = 00H to FFH) Remark n = 0, 1 256 User's Manual U17397E4V0UD CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 www..com Figure 8-14. PWM Output Operation Timing (a) Basic operation (active level = H) t Count clock TM5n CR5n TCE5n INTTM5n TO5n <1> Inactive level <2> Active level <3> Inactive level <2> Active level <5> Inactive level 00H 01H N FFH 00H 01H 02H N N+1 FFH 00H 01H 02H M 00H (b) CR5n = 00H t Count clock TM5n CR5n TCE5n INTTM5n TO5n L (Inactive level) 00H 01H 00H FFH 00H 01H 02H FFH 00H 01H 02H M 00H (c) CR5n = FFH t TM5n CR5n TCE5n INTTM5n TO5n 00H 01H FFH FFH 00H 01H 02H FFH 00H 01H 02H M 00H <1> Inactive level <2> Active level <2> Active level <3> Inactive level <5> Inactive level Remarks 1. <1> to <3> and <5> in Figure 8-14 (a) and (c) correspond to <1> to <3> and <5> in PWM output operation in 8.4.4 (1) PWM output basic operation. 2. n = 0, 1 User's Manual U17397E4V0UD 257 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 www..com (2) Operation with CR5n changed Figure 8-15. Timing of Operation with CR5n Changed (a) CR5n value is changed from N to M before clock rising edge of FFH Value is transferred to CR5n at overflow immediately after change. t Count clock TM5n CR5n TCE5n INTTM5n TO5n <2> <1> CR5n change (N M) H N N+1 N+2 N FFH 00H 01H 02H M M M+1 M+2 FFH 00H 01H 02H M M+1 M+2 (b) CR5n value is changed from N to M after clock rising edge of FFH Value is transferred to CR5n at second overflow. t Count clock TM5n CR5n TCE5n INTTM5n TO5n <1> CR5n change (N M) <2> H N N+1 N+2 N FFH 00H 01H 02H N N N+1 N+2 FFH 00H 01H 02H M M M+1 M+2 Caution When reading from CR5n between <1> and <2> in Figure 8-15, the value read differs from the actual value (read value: M, actual value of CR5n: N). 258 User's Manual U17397E4V0UD CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 www..com 8.5 Cautions for 8-Bit Timer/Event Counters 50 and 51 (1) Timer start error An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 8-bit timer counters 50 and 51 (TM50, TM51) are started asynchronously to the count clock. Figure 8-16. 8-Bit Timer Counter 5n Start Timing Count clock TM5n count value 00H Timer start 01H 02H 03H 04H Remark n = 0, 1 User's Manual U17397E4V0UD 259 www..com CHAPTER 9 8-BIT TIMERS H0 AND H1 9.1 Functions of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 have the following functions. * Interval timer * Square-wave output * PWM output * Carrier generator (8-bit timer H1 only) 9.2 Configuration of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 include the following hardware. Table 9-1. Configuration of 8-Bit Timers H0 and H1 Item Timer register Registers 8-bit timer counter Hn 8-bit timer H compare register 0n (CMP0n) 8-bit timer H compare register 1n (CMP1n) Timer output Control registers TOHn, output controller 8-bit timer H mode register n (TMHMDn) 8-bit timer H carrier control register 1 (TMCYC1) Port mode register 1 (PM1) Port register 1 (P1) Note Configuration Note 8-bit timer H1 only Remark n = 0, 1 Figures 9-1 and 9-2 show the block diagrams. 260 User's Manual U17397E4V0UD Figure 9-1. Block Diagram of 8-Bit Timer H0 Internal bus 8-bit timer H mode register 0 (TMHMD0) TMHE0 CKS02 CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0 8-bit timer H compare register 10 (CMP10) 8-bit timer H compare register 00 (CMP00) 3 2 Decoder Selector Match fPRS fPRS/2 fPRS/22 fPRS/26 fPRS/210 8-bit timer/ event counter 50 output Interrupt generator F/F R Output controller Level inversion Output latch (P15) PM15 User's Manual U17397E4V0UD TOH0/P15 CHAPTER 9 8-BIT TIMERS H0 AND H1 Selector 8-bit timer counter H0 Clear PWM mode signal 1 0 INTTMH0 Timer H enable signal www..com 261 Selector 262 8-bit timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 3 2 Decoder User's Manual U17397E4V0UD Figure 9-2. Block Diagram of 8-Bit Timer H1 Internal bus 8-bit timer H carrier control register 1 RMC1 NRZB1 NRZ1 (TMCYC1) Reload/ interrupt control INTTM51 TOH1/ INTP5/ P16 CHAPTER 9 8-BIT TIMERS H0 AND H1 8-bit timer H compare register 1 1 (CMP11) 8-bit timer H compare register 0 1 (CMP01) Selector Match fPRS fPRS/22 fPRS/24 fPRS/26 fPRS/212 fRL fRL/27 fRL/29 Interrupt generator F/F R Output controller Level inversion Output latch (P16) PM16 8-bit timer counter H1 Carrier generator mode signal PWM mode signal 1 0 INTTMH1 Clear Timer H enable signal www..com CHAPTER 9 8-BIT TIMERS H0 AND H1 www..com (1) 8-bit timer H compare register 0n (CMP0n) This register can be read or written by an 8-bit memory manipulation instruction. This register is used in all of the timer operation modes. This register constantly compares the value set to CMP0n with the count value of the 8-bit timer counter Hn and, when the two values match, generates an interrupt request signal (INTTMHn) and inverts the output level of TOHn. Rewrite the value of CMP0n while the timer is stopped (TMHEn = 0). A reset signal generation clears this register to 00H. Figure 9-3. Format of 8-Bit Timer H Compare Register 0n (CMP0n) Address: FF18H (CMP00), FF1AH (CMP01) Symbol CMP0n (n = 0, 1) 7 6 5 4 After reset: 00H 3 R/W 2 1 0 Caution CMP0n cannot be rewritten during timer count operation. CMP0n can be refreshed (the same value is written) during timer count operation. (2) 8-bit timer H compare register 1n (CMP1n) This register can be read or written by an 8-bit memory manipulation instruction. This register is used in the PWM output mode and carrier generator mode. In the PWM output mode, this register constantly compares the value set to CMP1n with the count value of the 8bit timer counter Hn and, when the two values match, inverts the output level of TOHn. No interrupt request signal is generated. In the carrier generator mode, the CMP1n register always compares the value set to CMP1n with the count value of the 8-bit timer counter Hn and, when the two values match, generates an interrupt request signal (INTTMHn). At the same time, the count value is cleared. CMP1n can be refreshed (the same value is written) and rewritten during timer count operation. If the value of CMP1n is rewritten while the timer is operating, the new value is latched and transferred to CMP1n when the count value of the timer matches the old value of CMP1n, and then the value of CMP1n is changed to the new value. If matching of the count value and the CMP1n value and writing a value to CMP1n conflict, the value of CMP1n is not changed. A reset signal generation clears this register to 00H. Figure 9-4. Format of 8-Bit Timer H Compare Register 1n (CMP1n) Address: FF19H (CMP10), FF1BH (CMP11) Symbol CMP1n (n = 0, 1) 7 6 5 4 After reset: 00H 3 R/W 2 1 0 Caution In the PWM output mode and carrier generator mode, be sure to set CMP1n when starting the timer count operation (TMHEn = 1) after the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the same value to CMP1n). Remark n = 0, 1 User's Manual U17397E4V0UD 263 CHAPTER 9 8-BIT TIMERS H0 AND H1 www..com 9.3 Registers Controlling 8-Bit Timers H0 and H1 The following four registers are used to control 8-bit timers H0 and H1. * 8-bit timer H mode register n (TMHMDn) * 8-bit timer H carrier control register 1 (TMCYC1)Note * Port mode register 1 (PM1) * Port register 1 (P1) Note 8-bit timer H1 only (1) 8-bit timer H mode register n (TMHMDn) This register controls the mode of timer H. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Remark n = 0, 1 264 User's Manual U17397E4V0UD CHAPTER 9 8-BIT TIMERS H0 AND H1 www..com Figure 9-5. Format of 8-Bit Timer H Mode Register 0 (TMHMD0) Address: FF69H <7> TMHMD0 TMHE0 After reset: 00H 6 CKS02 R/W 5 CKS01 4 CKS00 3 2 <1> <0> TOEN0 TMMD01 TMMD00 TOLEV0 TMHE0 0 1 Timer operation enable Stops timer count operation (counter is cleared to 0) Enables timer count operation (count operation started by inputting clock) CKS02 CKS01 CKS00 fPRS = 2 MHz Count clock selection fPRS = 5 MHz 5 MHz 2.5 MHz 1.25 MHz fPRS = 10 MHz 10 MHz 5 MHz 2.5 MHz fPRS = 20 MHz 20 MHz 10 MHz 5 MHz 0 0 0 0 1 1 0 0 1 1 0 0 Other than above 0 1 0 1 0 1 fPRS fPRS/2 fPRS/2 fPRS/2 2 6 2 MHz 1 MHz 500 kHz 31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz 4.88 kHz 9.77 kHz 19.54 kHz fPRS/210 1.95 kHz TM50 output Note Setting prohibited TMMD01 TMMD00 0 1 0 0 Interval timer mode PWM output mode Setting prohibited Timer operation mode Other than above TOLEV0 0 1 Low level High level Timer output level control (in default mode) TOEN0 0 1 Disables output Enables output Timer output control Note Note the following points when selecting the TM50 output as the count clock. * Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0) Start the operation of the 8-bit timer/event counter 50 first and then enable the timer F/F inversion operation (TMC501 = 1). * PWM mode (TMC506 = 1) Start the operation of the 8-bit timer/event counter 50 first and then set the count clock to make the duty = 50%. It is not necessary to enable the TO50 pin as a timer output pin in any mode. User's Manual U17397E4V0UD 265 CHAPTER 9 8-BIT TIMERS H0 AND H1 www..com Cautions 1. When TMHE0 = 1, setting the other bits of TMHMD0 is prohibited. However, TMHMD0 can be refreshed (the same value is written). 2. In the PWM output mode, be sure to set the 8-bit timer H compare register 10 (CMP10) when starting the timer count operation (TMHE0 = 1) after the timer count operation was stopped (TMHE0 = 0) (be sure to set again even if setting the same value to CMP10). Remarks 1. fPRS: Peripheral hardware clock frequency 2. TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50) TMC501: Bit 1 of TMC50 266 User's Manual U17397E4V0UD CHAPTER 9 8-BIT TIMERS H0 AND H1 www..com Figure 9-6. Format of 8-Bit Timer H Mode Register 1 (TMHMD1) Address: FF6CH <7> TMHMD1 TMHE1 After reset: 00H 6 CKS12 R/W 5 CKS11 4 CKS10 3 2 <1> <0> TOEN1 TMMD11 TMMD10 TOLEV1 TMHE1 0 1 Timer operation enable Stops timer count operation (counter is cleared to 0) Enables timer count operation (count operation started by inputting clock) CKS12 CKS11 CKS10 fPRS = 2 MHz Count clock selection fPRS = 5 MHz 5 MHz fPRS = 10 MHz 10 MHz fPRS = 20 MHz 20 MHz 5 MHz 1.25 MHz 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fPRS fPRS/2 2 2 MHz 500 kHz 1.25 MHz 2.5 MHz 312.5 kHz 625 kHz fPRS/24 125 kHz fPRS/26 31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz fPRS/212 0.49 kHz fRL/27 fRL/29 fRL 1.22 kHz 2.44 kHz 4.88 kHz 1.88 kHz (TYP.) 0.47 kHz (TYP.) 240 kHz (TYP.) TMMD11 TMMD10 0 0 1 1 0 1 0 1 Interval timer mode Timer operation mode Carrier generator mode PWM output mode Setting prohibited TOLEV1 0 1 Low level High level Timer output level control (in default mode) TOEN1 0 1 Disables output Enables output Timer output control Cautions 1. When TMHE1 = 1, setting the other bits of TMHMD1 is prohibited. However, TMHMD1 can be refreshed (the same value is written). 2. In the PWM output mode and carrier generator mode, be sure to set the 8-bit timer H compare register 11 (CMP11) when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to CMP11). 3. When the carrier generator mode is used, set so that the count clock frequency of TMH1 becomes more than 6 times the count clock frequency of TM51. Remarks 1. fPRS: Peripheral hardware clock frequency 2. fRL: Internal low-speed oscillation clock frequency User's Manual U17397E4V0UD 267 CHAPTER 9 8-BIT TIMERS H0 AND H1 www..com (2) 8-bit timer H carrier control register 1 (TMCYC1) This register controls the remote control output and carrier pulse output status of 8-bit timer H1. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 9-7. Format of 8-Bit Timer H Carrier Control Register 1 (TMCYC1) Address: FF6DH After reset: 00H R/WNote <0> TMCYC1 0 0 0 0 0 RMC1 NRZB1 NRZ1 RMC1 0 0 1 1 NRZB1 0 1 0 1 Low-level output Remote control output High-level output at rising edge of INTTM51 signal input Low-level output Carrier pulse output at rising edge of INTTM51 signal input NRZ1 0 1 Carrier pulse output status flag Carrier output disabled status (low-level status) Carrier output enabled status (RMC1 = 1: Carrier pulse output, RMC1 = 0: High-level status) Note Bit 0 is read-only. Caution Do not rewrite RMC1 when TMHE = 1. However, TMCYC1 can be refreshed (the same value is written). (3) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using the P15/TOH0 and P16/TOH1/INTP5 pins for timer output, clear PM15 and PM16 and the output latches of P15 and P16 to 0. PM1 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Figure 9-8. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol PM1 7 PM17 After reset: FFH 6 PM16 R/W 5 PM15 4 PM14 3 PM13 2 PM12 1 PM11 0 PM10 PM1n 0 1 P1n pin I/O mode selection (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off) 268 User's Manual U17397E4V0UD CHAPTER 9 8-BIT TIMERS H0 AND H1 www..com 9.4 Operation of 8-Bit Timers H0 and H1 9.4.1 Operation as interval timer/square-wave output When the 8-bit timer counter Hn and compare register 0n (CMP0n) match, an interrupt request signal (INTTMHn) is generated and the 8-bit timer counter Hn is cleared to 00H. Compare register 1n (CMP1n) is not used in interval timer mode. Since a match of the 8-bit timer counter Hn and the CMP1n register is not detected even if the CMP1n register is set, timer output is not affected. By setting bit 0 (TOENn) of timer H mode register n (TMHMDn) to 1, a square wave of any frequency (duty = 50%) is output from TOHn. Setting <1> Set each register. Figure 9-9. Register Setting During Interval Timer/Square-Wave Output Operation (i) Setting timer H mode register n (TMHMDn) TMHEn TMHMDn 0 CKSn2 0/1 CKSn1 0/1 CKSn0 0/1 TMMDn1 TMMDn0 TOLEVn 0 0 0/1 TOENn 0/1 Timer output setting Default setting of timer output level Interval timer mode setting Count clock (fCNT) selection Count operation stopped (ii) CMP0n register setting The interval time is as follows if N is set as a comparison value. * Interval time = (N +1)/fCNT <2> Count operation starts when TMHEn = 1. <3> When the values of the 8-bit timer counter Hn and the CMP0n register match, the INTTMHn signal is generated and the 8-bit timer counter Hn is cleared to 00H. <4> Subsequently, the INTTMHn signal is generated at the same interval. To stop the count operation, clear TMHEn to 0. Remarks 1. For the setting of the output pin, see 9.3 (3) Port mode register 1 (PM1). 2. For how to enable the INTTMHn signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS. 3. n = 0, 1 User's Manual U17397E4V0UD 269 CHAPTER 9 8-BIT TIMERS H0 AND H1 www..com Figure 9-10. Timing of Interval Timer/Square-Wave Output Operation (1/2) (a) Basic operation (Operation When 01H CMP0n FEH) Count clock Count start 8-bit timer counter Hn 00H 01H N 00H Clear 01H N 00H Clear 01H 00H CMP0n N TMHEn INTTMHn Interval time TOHn <1> <2> Level inversion, match interrupt occurrence, 8-bit timer counter Hn clear <3> <2> Level inversion, match interrupt occurrence, 8-bit timer counter Hn clear <1> The count operation is enabled by setting the TMHEn bit to 1. The count clock starts counting no more than 1 clock after the operation is enabled. <2> When the value of the 8-bit timer counter Hn matches the value of the CMP0n register, the value of the timer counter is cleared, and the level of the TOHn output is inverted. In addition, the INTTMHn signal is output at the rising edge of the count clock. <3> If the TMHEn bit is cleared to 0 while timer H is operating, the INTTMHn signal and TOHn output are set to the default level. If they are already at the default level before the TMHEn bit is cleared to 0, then that level is maintained. Remark n = 0, 1 01H N FEH 270 User's Manual U17397E4V0UD CHAPTER 9 8-BIT TIMERS H0 AND H1 www..com Figure 9-10. Timing of Interval Timer/Square-Wave Output Operation (2/2) (b) Operation when CMP0n = FFH Count clock Count start 8-bit timer counter Hn 00H 01H FEH FFH 00H Clear FEH FFH 00H Clear CMP0n FFH TMHEn INTTMHn TOHn Interval time (c) Operation when CMP0n = 00H Count clock Count start 8-bit timer counter Hn 00H CMP0n 00H TMHEn INTTMHn TOHn Interval time Remark n = 0, 1 User's Manual U17397E4V0UD 271 CHAPTER 9 8-BIT TIMERS H0 AND H1 www..com 9.4.2 Operation as PWM output In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. The 8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n register during timer operation is prohibited. The 8-bit timer compare register 1n (CMP1n) controls the duty of timer output (TOHn). Rewriting the CMP1n register during timer operation is possible. The operation in PWM output mode is as follows. The TOHn output level is inverted and the 8-bit timer counter Hn is cleared to 0 when the 8-bit timer counter Hn and the CMP0n register match after the timer count is started. The TOHn output level is inverted when the 8-bit timer counter Hn and the CMP1n register match. Setting <1> Set each register. Figure 9-11. Register Setting in PWM Output Mode (i) Setting timer H mode register n (TMHMDn) TMHEn TMHMDn 0 CKSn2 0/1 CKSn1 0/1 CKSn0 0/1 TMMDn1 TMMDn0 TOLEVn 1 0 0/1 TOENn 1 Timer output enabled Default setting of timer output level PWM output mode selection Count clock (fCNT) selection Count operation stopped (ii) Setting CMP0n register * Compare value (N): Cycle setting (iii) Setting CMP1n register * Compare value (M): Duty setting Remarks 1. n = 0, 1 2. 00H CMP1n (M) < CMP0n (N) FFH <2> The count operation starts when TMHEn = 1. <3> The CMP0n register is the compare register that is to be compared first after counter operation is enabled. When the values of the 8-bit timer counter Hn and the CMP0n register match, the 8-bit timer counter Hn is cleared, an interrupt request signal (INTTMHn) is generated, and TOHn output is inverted. At the same time, the compare register to be compared with the 8-bit timer counter Hn is changed from the CMP0n register to the CMP1n register. <4> When the 8-bit timer counter Hn and the CMP1n register match, TOHn output is inverted and the compare register to be compared with the 8-bit timer counter Hn is changed from the CMP1n register to the CMP0n register. At this time, the 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated. 272 User's Manual U17397E4V0UD CHAPTER 9 8-BIT TIMERS H0 AND H1 www..com <5> By performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty can be obtained. <6> To stop the count operation, set TMHEn = 0. If the setting value of the CMP0n register is N, the setting value of the CMP1n register is M, and the count clock frequency is fCNT, the PWM pulse output cycle and duty are as follows. * PWM pulse output cycle = (N + 1)/fCNT * Duty = (M + 1)/(N + 1) Cautions 1. The set value of the CMP1n register can be changed while the timer counter is operating. However, this takes a duration of three operating clocks (signal selected by the CKSn2 to CKSn0 bits of the TMHMDn register) from when the value of the CMP1n register is changed until the value is transferred to the register. 2. Be sure to set the CMP1n register when starting the timer count operation (TMHEn = 1) after the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the same value to the CMP1n register). 3. Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N) are within the following range. 00H CMP1n (M) < CMP0n (N) FFH Remarks 1. For the setting of the output pin, see 9.3 (3) Port mode register 1 (PM1). 2. For details on how to enable the INTTMHn signal interrupt, see CHAPTER 20 FUNCTIONS. 3. n = 0, 1 INTERRUPT User's Manual U17397E4V0UD 273 CHAPTER 9 8-BIT TIMERS H0 AND H1 www..com Figure 9-12. Operation Timing in PWM Output Mode (1/4) (a) Basic operation Count clock 8-bit timer counter Hn 00H 01H A5H 00H 01H 02H A5H 00H 01H 02H A5H 00H CMP0n A5H CMP1n 01H TMHEn INTTMHn TOHn (TOLEVn = 0) <1> TOHn (TOLEVn = 1) <2> <3> <4> <1> The count operation is enabled by setting the TMHEn bit to 1. Start the 8-bit timer counter Hn by masking one count clock to count up. At this time, TOHn output remains the default. <2> When the values of the 8-bit timer counter Hn and the CMP0n register match, the TOHn output level is inverted, the value of the 8-bit timer counter Hn is cleared, and the INTTMHn signal is output. <3> When the values of the 8-bit timer counter Hn and the CMP1n register match, the TOHn output level is inverted. At this time, the 8-bit timer counter value is not cleared and the INTTMHn signal is not output. <4> Clearing the TMHEn bit to 0 during timer Hn operation sets the INTTMHn signal and TOHn output to the default. Remark n = 0, 1 274 User's Manual U17397E4V0UD CHAPTER 9 8-BIT TIMERS H0 AND H1 www..com Figure 9-12. Operation Timing in PWM Output Mode (2/4) (b) Operation when CMP0n = FFH, CMP1n = 00H Count clock 8-bit timer counter Hn 00H 01H FFH 00H 01H 02H FFH 00H 01H 02H FFH 00H CMP0n FFH CMP1n 00H TMHEn INTTMHn TOHn (TOLEVn = 0) (c) Operation when CMP0n = FFH, CMP1n = FEH Count clock 8-bit timer counter Hn 00H 01H FEH FFH 00H 01H FEH FFH 00H 01H FEH FFH 00H CMP0n FFH CMP1n FEH TMHEn INTTMHn TOHn (TOLEVn = 0) Remark n = 0, 1 User's Manual U17397E4V0UD 275 CHAPTER 9 8-BIT TIMERS H0 AND H1 www..com Figure 9-12. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP0n = 01H, CMP1n = 00H Count clock 8-bit timer counter Hn 00H 01H 00H 01H 00H 00H 01H 00H 01H CMP0n 01H CMP1n 00H TMHEn INTTMHn TOHn (TOLEVn = 0) Remark n = 0, 1 276 User's Manual U17397E4V0UD CHAPTER 9 8-BIT TIMERS H0 AND H1 www..com Figure 9-12. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP1n (CMP1n = 02H 03H, CMP0n = A5H) Count clock 8-bit timer counter Hn 00H 01H 02H 80H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H CMP01 A5H CMP11 02H <2> 02H (03H) <2>' 03H TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) <1> <3> <4> <5> <6> <1> The count operation is enabled by setting TMHEn = 1. Start the 8-bit timer counter Hn by masking one count clock to count up. At this time, the TOHn output remains default. <2> The CMP1n register value can be changed during timer counter operation. This operation is asynchronous to the count clock. <3> When the values of the 8-bit timer counter Hn and the CMP0n register match, the value of the 8-bit timer counter Hn is cleared, the TOHn output level is inverted, and the INTTMHn signal is output. <4> If the CMP1n register value is changed, the value is latched and not transferred to the register. When the values of the 8-bit timer counter Hn and the CMP1n register before the change match, the value is transferred to the CMP1n register and the CMP1n register value is changed (<2>'). However, three count clocks or more are required from when the CMP1n register value is changed to when the value is transferred to the register. If a match signal is generated within three count clocks, the changed value cannot be transferred to the register. <5> When the values of the 8-bit timer counter Hn and the CMP1n register after the change match, the TOHn output level is inverted. The 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated. <6> Clearing the TMHEn bit to 0 during timer Hn operation makes the INTTMHn signal and TOHn output default. Remark n = 0, 1 User's Manual U17397E4V0UD 277 CHAPTER 9 8-BIT TIMERS H0 AND H1 www..com 9.4.3 Carrier generator operation (8-bit timer H1 only) In the carrier generator mode, the 8-bit timer H1 is used to generate the carrier signal of an infrared remote controller, and the 8-bit timer/event counter 51 is used to generate an infrared remote control signal (time count). The carrier clock generated by the 8-bit timer H1 is output in the cycle set by the 8-bit timer/event counter 51. In carrier generator mode, the output of the 8-bit timer H1 carrier pulse is controlled by the 8-bit timer/event counter 51, and the carrier pulse is output from the TOH1 output. (1) Carrier generation In carrier generator mode, the 8-bit timer H compare register 01 (CMP01) generates a low-level width carrier pulse waveform and the 8-bit timer H compare register 11 (CMP11) generates a high-level width carrier pulse waveform. Rewriting the CMP11 register during the 8-bit timer H1 operation is possible but rewriting the CMP01 register is prohibited. (2) Carrier output control Carrier output is controlled by the interrupt request signal (INTTM51) of the 8-bit timer/event counter 51 and the NRZB1 and RMC1 bits of the 8-bit timer H carrier control register (TMCYC1). The relationship between the outputs is shown below. RMC1 Bit 0 0 NRZB1 Bit 0 1 Output Low-level output High-level output at rising edge of INTTM51 signal input 1 1 0 1 Low-level output Carrier pulse output at rising edge of INTTM51 signal input 278 User's Manual U17397E4V0UD CHAPTER 9 8-BIT TIMERS H0 AND H1 www..com To control the carrier pulse output during a count operation, the NRZ1 and NRZB1 bits of the TMCYC1 register have a master and slave bit configuration. The NRZ1 bit is read-only but the NRZB1 bit can be read and written. The INTTM51 signal is synchronized with the 8-bit timer H1 count clock and is output as the INTTM5H1 signal. The INTTM5H1 signal becomes the data transfer signal of the NRZ1 bit, and the NRZB1 bit value is transferred to the NRZ1 bit. The timing for transfer from the NRZB1 bit to the NRZ1 bit is as shown below. Figure 9-13. Transfer Timing TMHE1 8-bit timer H1 count clock INTTM51 INTTM5H1 <1> NRZ1 0 <2> NRZB1 1 <3> RMC1 0 1 1 0 <1> <2> <3> The INTTM51 signal is synchronized with the count clock of the 8-bit timer H1 and is output as the INTTM5H1 signal. The value of the NRZB1 bit is transferred to the NRZ1 bit at the second clock from the rising edge of the INTTM5H1 signal. Write the next value to the NRZB1 bit in the interrupt servicing program that has been started by the INTTM5H1 interrupt or after timing has been checked by polling the interrupt request flag. Write data to count the next time to the CR51 register. Cautions 1. Do not rewrite the NRZB1 bit again until at least the second clock after it has been rewritten, or else the transfer from the NRZB1 bit to the NRZ1 bit is not guaranteed. 2. When the 8-bit timer/event counter 51 is used in the carrier generator mode, an interrupt is generated at the timing of <1>. When the 8-bit timer/event counter 51 is used in a mode other than the carrier generator mode, the timing of the interrupt generation differs. User's Manual U17397E4V0UD 279 CHAPTER 9 8-BIT TIMERS H0 AND H1 www..com Setting <1> Set each register. Figure 9-14. Register Setting in Carrier Generator Mode (i) Setting 8-bit timer H mode register 1 (TMHMD1) CKS12 0/1 CKS11 0/1 CKS10 0/1 TMMD11 TMMD10 TOLEV1 0 1 0/1 TOEN1 1 TMHE1 TMHMD1 0 Timer output enabled Default setting of timer output level Carrier generator mode selection Count clock (fCNT) selection Count operation stopped (ii) CMP01 register setting * Compare value (iii) CMP11 register setting * Compare value (iv) TMCYC1 register setting * RMC1 = 1 ... Remote control output enable bit * NRZB1 = 0/1 ... carrier output enable bit (v) TCL51 and TMC51 register setting * See 8.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51. <2> When TMHE1 = 1, the 8-bit timer H1 starts counting. <3> When TCE51 of the 8-bit timer mode control register 51 (TMC51) is set to 1, the 8-bit timer/event counter 51 starts counting. <4> After the count operation is enabled, the first compare register to be compared is the CMP01 register. When the count value of the 8-bit timer counter H1 and the CMP01 register value match, the INTTMH1 signal is generated, the 8-bit timer counter H1 is cleared. At the same time, the compare register to be compared with the 8-bit timer counter H1 is switched from the CMP01 register to the CMP11 register. <5> When the count value of the 8-bit timer counter H1 and the CMP11 register value match, the INTTMH1 signal is generated, the 8-bit timer counter H1 is cleared. At the same time, the compare register to be compared with the 8-bit timer counter H1 is switched from the CMP11 register to the CMP01 register. <6> By performing procedures <4> and <5> repeatedly, a carrier clock is generated. <7> The INTTM51 signal is synchronized with count clock of the 8-bit timer H1 and output as the INTTM5H1 signal. The INTTM5H1 signal becomes the data transfer signal for the NRZB1 bit, and the NRZB1 bit value is transferred to the NRZ1 bit. <8> Write the next value to the NRZB1 bit in the interrupt servicing program that has been started by the INTTM5H1 interrupt or after timing has been checked by polling the interrupt request flag. Write data to count the next time to the CR51 register. <9> When the NRZ1 bit is high level, a carrier clock is output from the TOH1 pin. 280 User's Manual U17397E4V0UD CHAPTER 9 8-BIT TIMERS H0 AND H1 www..com <10> By performing the procedures above, an arbitrary carrier clock is obtained. To stop the count operation, clear TMHE1 to 0. If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count clock frequency is fCNT, the carrier clock output cycle and duty are as follows. * Carrier clock output cycle = (N + M + 2)/fCNT * Duty = High-level width/carrier clock output width = (M + 1)/(N + M + 2) Cautions 1. Be sure to set the CMP11 register when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to the CMP11 register). 2. Set so that the count clock frequency of TMH1 becomes more than 6 times the count clock frequency of TM51. 3. Set the values of the CMP01 and CMP11 registers in a range of 01H to FFH. 4. The set value of the CMP11 register can be changed while the timer counter is operating. However, it takes the duration of three operating clocks (signal selected by the CKS12 to CKS10 bits of the TMHMD1 register) since the value of the CMP11 register has been changed until the value is transferred to the register. 5. Be sure to set the RMC1 bit before the count operation is started. Remarks 1. For the setting of the output pin, see 9.3 (3) Port mode register 1 (PM1). 2. For how to enable the INTTMH1 signal interrupt, see CHAPTER 20 FUNCTIONS. INTERRUPT User's Manual U17397E4V0UD 281 CHAPTER 9 8-BIT TIMERS H0 AND H1 www..com Figure 9-15. Carrier Generator Mode Operation Timing (1/3) (a) Operation when CMP01 = N, CMP11 = N 8-bit timer H1 count clock 8-bit timer counter H1 count value CMP01 CMP11 TMHE11 INTTMH1 <1><2> Carrier clock 8-bit timer 51 count clock TM51 count value CR51 TCE51 <5> INTTM5n1 INTTM5H1 NRZB1 NRZ1 Carrier clock TOH11 <7> 0 0 1 1 0 <6> 0 1 0 1 0 00H 01H K 00H 01H K L 00H 01H M 00H 01H N 00H 01H N 00H N 00H N 00H N 00H N N 00H N 00H N N <3> <4> L M <1> When TMHE1 = 0 and TCE51 = 0, the 8-bit timer counter H1 operation is stopped. <2> When TMHE1 = 1 is set, the 8-bit timer counter H1 starts a count operation. At that time, the carrier clock remains default. <3> When the count value of the 8-bit timer counter H1 matches the CMP01 register value, the first INTTMH1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8bit timer counter H1 is switched from the CMP01 register to the CMP11 register. The 8-bit timer counter H1 is cleared to 00H. <4> When the count value of the 8-bit timer counter H1 matches the CMP11 register value, the INTTMH1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8-bit timer counter H1 is switched from the CMP11 register to the CMP01 register. The 8-bit timer counter H1 is cleared to 00H. By performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to 50% is generated. <5> When the INTTM51 signal is generated, it is synchronized with the 8-bit timer H1 count clock and is output as the INTTM5H1 signal. <6> The INTTM5H1 signal becomes the data transfer signal for the NRZB1 bit, and the NRZB1 bit value is transferred to the NRZ1 bit. <7> When NRZ1 = 0 is set, the TOH1 output becomes low level. 282 User's Manual U17397E4V0UD CHAPTER 9 8-BIT TIMERS H0 AND H1 www..com Figure 9-15. Carrier Generator Mode Operation Timing (2/3) (b) Operation when CMP01 = N, CMP11 = M 8-bit timer H1 count clock 8-bit timer counter H1 count value CMP01 CMP11 TMHE1 INTTMH1 <1><2> Carrier clock 8-bit timer 51 count clock TM51 count value CR51 TCE51 <5> INTTM51 INTTM5H1 NRZB1 NRZ1 Carrier clock <6> TOH1 <7> 0 0 1 1 0 0 1 1 0 0 00H 01H K K 00H 01H L 00H 01H M 00H 01H M N 00H 01H 00H N 00H 01H M 00H N N 00H 01H M 00H N 00H M <3> <4> L N <1> When TMHE1 = 0 and TCE51 = 0, the 8-bit timer counter H1 operation is stopped. <2> When TMHE1 = 1 is set, the 8-bit timer counter H1 starts a count operation. At that time, the carrier clock remains default. <3> When the count value of the 8-bit timer counter H1 matches the CMP01 register value, the first INTTMH1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8bit timer counter H1 is switched from the CMP01 register to the CMP11 register. The 8-bit timer counter H1 is cleared to 00H. <4> When the count value of the 8-bit timer counter H1 matches the CMP11 register value, the INTTMH1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8-bit timer counter H1 is switched from the CMP11 register to the CMP01 register. The 8-bit timer counter H1 is cleared to 00H. By performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to other than 50% is generated. <5> When the INTTM51 signal is generated, it is synchronized with the 8-bit timer H1 count clock and is output as the INTTM5H1 signal. <6> A carrier signal is output at the first rising edge of the carrier clock if NRZ1 is set to 1. <7> When NRZ1 = 0, the TOH1 output is held at the high level and is not changed to low level while the carrier clock is high level (from <6> and <7>, the high-level width of the carrier clock waveform is guaranteed). User's Manual U17397E4V0UD 283 CHAPTER 9 8-BIT TIMERS H0 AND H1 www..com Figure 9-15. Carrier Generator Mode Operation Timing (3/3) (c) Operation when CMP11 is changed 8-bit timer H1 count clock 8-bit timer counter H1 count value 00H 01H N 00H 01H M 00H N 00H 01H L 00H CMP01 <3> CMP11 M M (L) N <3>' L TMHE1 INTTMH1 <2> Carrier clock <1> <4> <5> <1> When TMHE1 = 1 is set, the 8-bit timer H1 starts a count operation. At that time, the carrier clock remains default. <2> When the count value of the 8-bit timer counter H1 matches the value of the CMP01 register, the INTTMH1 signal is output, the carrier signal is inverted, and the timer counter is cleared to 00H. At the same time, the compare register whose value is to be compared with that of the 8-bit timer counter H1 is changed from the CMP01 register to the CMP11 register. <3> The CMP11 register is asynchronous to the count clock, and its value can be changed while the 8-bit timer H1 is operating. The new value (L) to which the value of the register is to be changed is latched. When the count value of the 8-bit timer counter H1 matches the value (M) of the CMP11 register before the change, the CMP11 register is changed (<3>'). However, it takes three count clocks or more since the value of the CMP11 register has been changed until the value is transferred to the register. Even if a match signal is generated before the duration of three count clocks elapses, the new value is not transferred to the register. <4> When the count value of 8-bit timer counter H1 matches the value (M) of the CMP1 register before the change, the INTTMH1 signal is output, the carrier signal is inverted, and the timer counter is cleared to 00H. At the same time, the compare register whose value is to be compared with that of the 8-bit timer counter H1 is changed from the CMP11 register to the CMP01 register. <5> The timing at which the count value of the 8-bit timer counter H1 and the CMP11 register value match again is indicated by the value after the change (L). 284 User's Manual U17397E4V0UD www..com CHAPTER 10 WATCH TIMER 10.1 Functions of Watch Timer The watch timer has the following functions. * Watch timer * Interval timer The watch timer and the interval timer can be used simultaneously. Figure 10-1 shows the watch timer block diagram. Figure 10-1. Block Diagram of Watch Timer Selector Clear fWX 5-bit counter Clear fWX/25 Selector fWX/24 INTWT Selector fPRS/2 7 fW 11-bit prescaler fW/24 fW/25 fW/26 fW/27 fW/28 fW/210 fW/211 fW/29 fSUB Selector INTWTI WTM7 WTM6 WTM5 WTM4 WTM3 WTM2 WTM1 WTM0 Watch timer operation mode register (WTM) Internal bus Remark fPRS: Peripheral hardware clock frequency fSUB: Subsystem clock frequency fW: Watch timer clock frequency (fPRS/27 or fSUB) fWX: fW or fW/29 User's Manual U17397EJ4V0UD 285 CHAPTER 10 WATCH TIMER www..com (1) Watch timer When the peripheral hardware clock or subsystem clock is used, interrupt request signals (INTWT) are generated at preset intervals. Table 10-1. Watch Timer Interrupt Time Interrupt Time 4 When Operated at fSUB = 32.768 kHz 488 s 977 s 0.25 s 0.5 s When Operated at fPRS = 2 MHz 1.02 ms 2.05 ms 0.52 s 1.05 s When Operated at fPRS = 5 MHz 410 s 819 s 0.210 s 0.419 s When Operated at fPRS = 10 MHz 205 s 410 s 0.105 s 0.210 s When Operated at fPRS = 20 MHz 102 s 205 s 52.5 ms 0.105 s 2 /fW 2 /fW 2 /fW 2 /fW 14 13 5 Remark fPRS: Peripheral hardware clock frequency fSUB: Subsystem clock frequency fW: Watch timer clock frequency (fPRS/27 or fSUB) (2) Interval timer Interrupt request signals (INTWTI) are generated at preset time intervals. Table 10-2. Interval Timer Interval Time Interval Time 4 When Operated at fSUB = 32.768 kHz 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms 31.3 ms 62.5 ms When Operated at fPRS = 2 MHz 1.02 ms 2.05 ms 4.10 ms 8.20 ms 16.4 ms 32.8 ms 65.5 ms 131.1 ms When Operated at fPRS = 5 MHz 410 s 820 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms 26.2 ms 52.4 ms When Operated at fPRS = 10 MHz 205 s 410 s 820 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms 26.2 ms When Operated at fPRS = 20 MHz 102 s 205 s 410 s 820 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 11 10 9 8 7 6 5 Remark fPRS: Peripheral hardware clock frequency fSUB: Subsystem clock frequency fW: Watch timer clock frequency (fPRS/27 or fSUB) 10.2 Configuration of Watch Timer The watch timer includes the following hardware. Table 10-3. Watch Timer Configuration Item Counter Prescaler Control register 5 bits x 1 11 bits x 1 Watch timer operation mode register (WTM) Configuration 286 User's Manual U17397EJ4V0UD CHAPTER 10 WATCH TIMER www..com 10.3 Register Controlling Watch Timer The watch timer is controlled by the watch timer operation mode register (WTM). * Watch timer operation mode register (WTM) This register sets the watch timer count clock, enables/disables operation, prescaler interval time, and 5-bit counter operation control. WTM is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears WTM to 00H. Figure 10-2. Format of Watch Timer Operation Mode Register (WTM) Address: FF6FH Symbol WTM 7 WTM7 After reset: 00H 6 WTM6 R/W 5 WTM5 4 WTM4 3 WTM3 2 WTM2 <1> WTM1 <0> WTM0 WTM7 fSUB = 32.768 kHz 0 1 fPRS/2 fSUB 7 Watch timer count clock selection (fW) fPRS = 2 MHz 15.625 kHz fPRS = 5 MHz 39.062 kHz - fPRS = 10 MHz 78.125 kHz fPRS = 20 MHz 156.25 kHz - 32.768 kHz WTM6 0 0 0 0 1 1 1 1 WTM5 0 0 1 1 0 0 1 1 WTM4 0 1 0 1 0 1 0 1 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 11 10 9 8 7 6 5 4 Prescaler interval time selection WTM3 0 0 1 1 WTM2 0 1 0 1 2 /fW 2 /fW 2 /fW 2 /fW 4 5 13 14 Selection of watch timer interrupt time WTM1 0 1 Clear after operation stop Start 5-bit counter operation control WTM0 0 1 Watch timer operation enable Operation stop (clear both prescaler and 5-bit counter) Operation enable User's Manual U17397EJ4V0UD 287 CHAPTER 10 WATCH TIMER www..com Caution Do not change the count clock and interval time (by setting bits 4 to 7 (WTM4 to WTM7) of WTM) during watch timer operation. Remarks 1. fW: Watch timer clock frequency (fPRS/27 or fSUB) 2. fPRS: Peripheral hardware clock frequency 3. fSUB: Subsystem clock frequency 288 User's Manual U17397EJ4V0UD CHAPTER 10 WATCH TIMER www..com 10.4 Watch Timer Operations 10.4.1 Watch timer operation The watch timer generates an interrupt request signal (INTWT) at a specific time interval by using the peripheral hardware clock or subsystem clock. When bit 0 (WTM0) and bit 1 (WTM1) of the watch timer operation mode register (WTM) are set to 1, the count operation starts. When these bits are cleared to 0, the 5-bit counter is cleared and the count operation stops. When the interval timer is simultaneously operated, zero-second start can be achieved only for the watch timer by clearing WTM1 to 0. In this case, however, the 11-bit prescaler is not cleared. Therefore, an error up to 29 x 1/fW seconds occurs in the first overflow (INTWT) after zero-second start. The interrupt request is generated at the following time intervals. Table 10-4. Watch Timer Interrupt Time WTM3 WTM2 Interrupt Time When Operated at When Operated at When Operated at When Operated at When Operated at Selection 0 0 1 1 0 1 0 1 2 /fW 2 /fW 2 /fW 2 /fW 4 5 13 14 fSUB = 32.768 kHz (WTM7 = 1) 0.5 s 0.25 s 977 s 488 s fPRS = 2 MHz (WTM7 = 0) 1.05 s 0.52 s 2.05 ms 1.02 ms 7 fPRS = 5 MHz (WTM7 = 0) 0.419 s 0.210 s 819 s 410 s fPRS = 10 MHz (WTM7 = 0) 0.210 s 0.105 s 410 s 205 s fPRS = 20 MHz (WTM7 = 0) 0.105 s 52.5 ms 205 s 102 s Remarks 1. fW: Watch timer clock frequency (fPRS/2 or fSUB) 2. fPRS: Peripheral hardware clock frequency 3. fSUB: Subsystem clock frequency 10.4.2 Interval timer operation The watch timer operates as interval timer which generates interrupt request signals (INTWTI) repeatedly at an interval of the preset count value. The interval time can be selected with bits 4 to 6 (WTM4 to WTM6) of the watch timer operation mode register (WTM). When bit 0 (WTM0) of the WTM is set to 1, the count operation starts. When this bit is set to 0, the count operation stops. Table 10-5. Interval Timer Interval Time WTM6 WTM5 WTM4 Interval Time When Operated When Operated When Operated When Operated When Operated at fSUB = 32.768 kHz (WTM7 = 1) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 11 10 9 8 7 6 5 4 at fPRS = 2 MHz (WTM7 = 0) 1.02 ms 2.05 ms 4.10 ms 8.20 ms 16.4 ms 32.8 ms 65.5 ms 131.1 ms 7 at fPRS = 5 MHz at fPRS = 10 MHz at fPRS = 20 MHz (WTM7 = 0) 410 s 820 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms 26.2 ms 52.4 ms (WTM7 = 0) 205 s 410 s 820 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms 26.2 ms (WTM7 = 0) 102 s 205 s 410 s 820 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms 31.3 ms 62.5 ms Remarks 1. fW: Watch timer clock frequency (fPRS/2 or fSUB) 2. fPRS: Peripheral hardware clock frequency 3. fSUB: Subsystem clock frequency User's Manual U17397EJ4V0UD 289 CHAPTER 10 WATCH TIMER www..com Figure 10-3. Operation Timing of Watch Timer/Interval Timer 5-bit counter 0H Start Count clock Watch timer interrupt INTWT Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTI Interval time (T) T Overflow Overflow Remark fW: Watch timer clock frequency Figures in parentheses are for operation with fW = 32.768 kHz (WTM7 = 1, WTM3, WTM2 = 0, 0) 10.5 Cautions for Watch Timer When operation of the watch timer and 5-bit counter is enabled by the watch timer mode control register (WTM) (by setting bits 0 (WTM0) and 1 (WTM1) of WTM to 1), the interval until the first interrupt request signal (INTWT) is generated after the register is set does not exactly match the specification made with bits 2 and 3 (WTM2, WTM3) of WTM. Subsequently, however, the INTWT signal is generated at the specified intervals. Figure 10-4. Example of Generation of Watch Timer Interrupt Request Signal (INTWT) (When Interrupt Period = 0.5 s) It takes 0.515625 seconds for the first INTWT to be generated (29 x 1/32768 = 0.015625 s longer). INTWT is then generated every 0.5 seconds. WTM0, WTM1 0.515625 s 0.5 s 0.5 s INTWT 290 User's Manual U17397EJ4V0UD www..com CHAPTER 11 WATCHDOG TIMER 11.1 Functions of Watchdog Timer The watchdog timer operates on the internal low-speed oscillation clock. The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. Program loop is detected in the following cases. * If the watchdog timer counter overflows * If a 1-bit manipulation instruction is executed on the watchdog timer enable register (WDTE) * If data other than "ACH" is written to WDTE * If data is written to WDTE during a window close period * If the instruction is fetched from an area not set by the IMS and IXS registers (detection of an invalid check while the CPU hangs up) * If the CPU accesses an area that is not set by the IMS and IXS registers (excluding FB00H to FFFFH) by executing a read/write instruction (detection of an abnormal access during a CPU program loop) When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1. For details of RESF, see CHAPTER 23 RESET FUNCTION. User's Manual U17397EJ4V0UD 291 CHAPTER 11 WATCHDOG TIMER www..com 11.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 11-1. Configuration of Watchdog Timer Item Control register Configuration Watchdog timer enable register (WDTE) How the counter operation is controlled, overflow time, and window open period are set by the option byte. Table 11-2. Setting of Option Bytes and Watchdog Timer Setting of Watchdog Timer Window open period Controlling counter operation of watchdog timer Overflow time of watchdog timer Option Byte (0080H) Bits 6 and 5 (WINDOW1, WINDOW0) Bit 4 (WDTON) Bits 3 to 1 (WDCS2 to WDCS0) Remark For the option byte, see CHAPTER 26 OPTION BYTE. Figure 11-1. Block Diagram of Watchdog Timer CPU access error detector CPU access signal WDCS2 to WDCS0 of option byte (0080H) 210/fRL to 217/fRL Selector fRL/2 Clock input controller 17-bit counter Overflow signal Reset output controller Internal reset signal Count clear signal WINDOW1 and WINDOW0 of option byte (0080H) Clear, reset control Window size determination signal WDTON of option byte (0080H) Watchdog timer enable register (WDTE) Internal bus 292 User's Manual U17397EJ4V0UD CHAPTER 11 WATCHDOG TIMER www..com 11.3 Register Controlling Watchdog Timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). (1) Watchdog timer enable register (WDTE) Writing ACH to WDTE clears the watchdog timer counter and starts counting again. This register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 9AH or 1AHNote. Figure 11-2. Format of Watchdog Timer Enable Register (WDTE) Address: FF99H Symbol WDTE 7 After reset: 9AH/1AHNote 6 5 R/W 4 3 2 1 0 Note The WDTE reset value differs depending on the WDTON setting value of the option byte (0080H). To operate watchdog timer, set WDTON to 1. WDTON Setting Value 0 (watchdog timer count operation disabled) 1 (watchdog timer count operation enabled) 1AH 9AH WDTE Reset Value Cautions 1. If a value other than ACH is written to WDTE, an internal reset signal is generated. If the source clock to the watchdog timer is stopped, however, an internal reset signal is generated when the source clock to the watchdog timer resumes operation. 2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset signal is generated. If the source clock to the watchdog timer is stopped, however, an internal reset signal is generated when the source clock to the watchdog timer resumes operation. 3. The value read from WDTE is 9AH/1AH (this differs from the written value (ACH)). User's Manual U17397EJ4V0UD 293 CHAPTER 11 WATCHDOG TIMER www..com 11.4 Operation of Watchdog Timer 11.4.1 Controlling operation of watchdog timer 1. When the watchdog timer is used, its operation is specified by the option byte (0080H). * Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (0080H) to 1 (the counter starts operating after a reset release) (for details, see CHAPTER 26). WDTON 0 1 Operation Control of Watchdog Timer Counter/Illegal Access Detection Counter operation disabled (counting stopped after reset), illegal access detection operation disabled Counter operation enabled (counting started after reset), illegal access detection operation enabled * Set an overflow time by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (0080H) (for details, see 11.4.2 and CHAPTER 26). * Set a window open period by using bits 6 and 5 (WINDOW1 and WINDOW0) of the option byte (0080H) (for details, see 11.4.3 and CHAPTER 26). 2. 3. 4. 5. After a reset release, the watchdog timer starts counting. By writing "ACH" to WDTE after the watchdog timer starts counting and before the overflow time set by the option byte, the watchdog timer is cleared and starts counting again. After that, write WDTE the second time or later after a reset release during the window open period. If WDTE is written during a window close period, an internal reset signal is generated. If the overflow time expires without "ACH" written to WDTE, an internal reset signal is generated. A internal reset signal is generated in the following cases. * If a 1-bit manipulation instruction is executed on the watchdog timer enable register (WDTE) * If data other than "ACH" is written to WDTE * If the instruction is fetched from an area not set by the IMS and IXS registers (detection of an invalid check during a CPU program loop) * If the CPU accesses an area not set by the IMS and IXS registers (excluding FB00H to FFFFH) by executing a read/write instruction (detection of an abnormal access during a CPU program loop) Cautions 1. The first writing to WDTE after a reset release clears the watchdog timer, if it is made before the overflow time regardless of the timing of the writing, and the watchdog timer starts counting again. 2. If the watchdog timer is cleared by writing "ACH" to WDTE, the actual overflow time may be different from the overflow time set by the option byte by up to 2/fRL seconds. 3. The watchdog timer can be cleared immediately before the count value overflows (FFFFH). 294 User's Manual U17397EJ4V0UD CHAPTER 11 WATCHDOG TIMER www..com Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows depending on the set value of bit 0 (LSROSC) of the option byte. LSROSC = 0 (Internal Low-Speed Oscillator Can Be Stopped by Software) In HALT mode In STOP mode Watchdog timer operation stops. LSROSC = 1 (Internal Low-Speed Oscillator Cannot Be Stopped) Watchdog timer operation continues. If LSROSC = 0, the watchdog timer resumes counting after the HALT or STOP mode is released. At this time, the counter is not cleared to 0 but starts counting from the value at which it was stopped. If oscillation of the internal low-speed oscillator is stopped by setting LSRSTOP (bit 1 of the internal oscillation mode register (RCM) = 1) when LSROSC = 0, the watchdog timer stops operating. At this time, the counter is not cleared to 0. WDCS2 0 0 0 0 1 1 1 1 WDCS1 0 0 1 1 0 0 1 1 WDCS0 0 1 0 1 0 1 0 1 10 Overflow Time of Watchdog Timer 2 /fRL (3.88 ms) 2 /fRL (7.76 ms) 2 /fRL (15.52 ms) 2 /fRL (31.03 ms) 2 /fRL (62.06 ms) 2 /fRL (124.12 ms) 2 /fRL (248.24 ms) 2 /fRL (496.48 ms) 17 16 15 14 13 12 11 Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0 is prohibited. User's Manual U17397EJ4V0UD 295 CHAPTER 11 WATCHDOG TIMER www..com 11.4.3 Setting window open period of watchdog timer Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte (0080H). The outline of the window is as follows. * If "ACH" is written to WDTE during the window open period, the watchdog timer is cleared and starts counting again. * Even if "ACH" is written to WDTE during the window close period, an abnormality is detected and an internal reset signal is generated. Example: If the window open period is 25% Counting starts Window close period (75%) Overflow time Window open period (25%) Internal reset signal is generated if ACH is written to WDTE. Counting starts again when ACH is written to WDTE. Caution The first writing to WDTE after a reset release clears the watchdog timer, if it is made before the overflow time regardless of the timing of the writing, and the watchdog timer starts counting again. The window open period to be set is as follows. Table 11-4. Setting Window Open Period of Watchdog Timer WINDOW1 0 0 1 1 WINDOW0 0 1 0 1 25% 50% 75% 100% Window Open Period of Watchdog Timer Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0 is prohibited. 296 User's Manual U17397EJ4V0UD CHAPTER 11 WATCHDOG TIMER www..com Remark If the overflow time is set to 210/fRL, the window close time and open time are as follows. (when 2.7 V VDD 5.5 V) Setting of Window Open Period 25% Window close time Window open time 0 to 3.56 ms 3.56 to 3.88 ms 50% 0 to 2.37 ms 2.37 to 3.88 ms 75% 0 to 0.119 ms 0.119 to 3.88 ms None 0 to 3.88 ms 100% User's Manual U17397EJ4V0UD 297 www..com CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 12.1 Functions of Clock Output/Buzzer Output Controller The clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral ICs. The clock selected with the clock output selection register (CKS) is output. In addition, the buzzer output is intended for square-wave output of buzzer frequency selected with CKS. Figure 12-1 shows the block diagram of clock output/buzzer output controller. Figure 12-1. Block Diagram of Clock Output/Buzzer Output Controller fPRS Prescaler 8 4 Selector fPRS/210 to fPRS/213 BUZ/BUSY0/INTP7/P141 BZOE Output latch (P141) BCS0, BCS1 PM141 Selector fPRS to fPRS/27 fSUB Clock controller PCL/INTP6/P140 CLOE Output latch (P140) PM140 BZOE BCS1 BCS0 CLOE CCS3 CCS2 CCS1 CCS0 Clock output selection register (CKS) Internal bus 298 User's Manual U17397EJ4V0UD CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER www..com 12.2 Configuration of Clock Output/Buzzer Output Controller The clock output/buzzer output controller includes the following hardware. Table 12-1. Configuration of Clock Output/Buzzer Output Controller Item Control registers Configuration Clock output selection register (CKS) Port mode register 14 (PM14) Port register 14 (P14) 12.3 Registers Controlling Clock Output/Buzzer Output Controller The following two registers are used to control the clock output/buzzer output controller. * Clock output selection register (CKS) * Port mode register 14 (PM14) (1) Clock output selection register (CKS) This register sets output enable/disable for clock output (PCL) and for the buzzer frequency output (BUZ), and sets the output clock. CKS is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears CKS to 00H. User's Manual U17397EJ4V0UD 299 CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER www..com Figure 12-2. Format of Clock Output Selection Register (CKS) Address: FF40H Symbol CKS After reset: 00H <7> BZOE 6 BCS1 R/W 5 BCS0 <4> CLOE 3 CCS3 2 CCS2 1 CCS1 0 CCS0 BZOE 0 1 BUZ output enable/disable specification Clock division circuit operation stopped. BUZ fixed to low level. Clock division circuit operation enabled. BUZ output enabled. BCS1 BCS0 BUZ output clock selection fPRS = 10 MHz fPRS = 20 MHz 19.54 kHz 9.77 kHz 4.88 kHz 2.44 kHz 0 0 1 1 0 1 0 1 fPRS/2 fPRS/2 fPRS/2 fPRS/2 10 9.77 kHz 4.88 kHz 2.44 kHz 1.22 kHz 11 12 13 CLOE 0 1 PCL output enable/disable specification Clock division circuit operation stopped. PCL fixed to low level. Clock division circuit operation enabled. PCL output enabled. CCS3 CCS2 CCS1 CCS0 PCL output clock selection fSUB = 32.768 kHz Note 1 fPRS = 10 MHz 10 MHz fPRS = 20 MHz Setting prohibited Note 2 0 0 0 0 fPRS - 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fSUB 2 5 MHz 2.5 MHz 1.25 MHz 625 kHz 312.5 kHz 156.25 kHz 78.125 kHz 32.768 kHz - 10 MHz 5 MHz 2.5 MHz 1.25 MHz 625 kHz 312.5 kHz 156.25 kHz 3 4 5 6 7 Other than above Setting prohibited Notes 1. 2. If the peripheral hardware clock operates on the internal high-speed oscillation clock when 1.8 V VDD < 2.7 V, setting CCS3 = CCS2 = CCS1 = CCS0 = 0 (output clock of PCL: fPRS) is prohibited. The PCL output clock prohibits settings if they exceed 10 MHz. Cautions 1. Set BCS1 and BCS0 when the buzzer output operation is stopped (BZOE = 0). 2. Set CCS3 to CCS0 while the clock output operation is stopped (CLOE = 0). Remarks 1. fPRS: Peripheral hardware clock frequency 2. fSUB: Subsystem clock frequency 300 User's Manual U17397EJ4V0UD CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER www..com (2) Port mode register 14 (PM14) This register sets port 14 input/output in 1-bit units. When using the P140/INTP6/PCL pin for clock output and the P141/INTP7/BUSY0/BUZ pin for buzzer output, clear PM140 and PM141 and the output latches of P140 and P141 to 0. PM14 is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PM14 to FFH. Figure 12-3. Format of Port Mode Register 14 (PM14) Address: FF2EH Symbol PM14 7 1 After reset: FFH 6 1 5 PM145 R/W 4 PM144 3 PM143 2 PM142 1 PM141 0 PM140 PM14n 0 1 P14n pin I/O mode selection (n = 0 to 5) Output mode (output buffer on) Input mode (output buffer off) 12.4 Operations of Clock Output/Buzzer Output Controller 12.4.1 Operation as clock output The clock pulse is output as the following procedure. <1> Select the clock pulse output frequency with bits 0 to 3 (CCS0 to CCS3) of the clock output selection register (CKS) (clock pulse output in disabled status). <2> Set bit 4 (CLOE) of CKS to 1 to enable clock output. Remark The clock output controller is designed not to output pulses with a small width during output enable/disable switching of the clock output. As shown in Figure 12-4, be sure to start output from the low period of the clock (marked with * in the figure). When stopping output, do so after the high-level period of the clock. Figure 12-4. Remote Control Output Application Example CLOE * Clock output * 12.4.2 Operation as buzzer output The buzzer frequency is output as the following procedure. <1> Select the buzzer output frequency with bits 5 and 6 (BCS0, BCS1) of the clock output selection register (CKS) (buzzer output in disabled status). <2> Set bit 7 (BZOE) of CKS to 1 to enable buzzer output. User's Manual U17397EJ4V0UD 301 www..com CHAPTER 13 A/D CONVERTER 13.1 Function of A/D Converter The A/D converter converts an analog input signal into a digital value, and consists of up to eight channels (ANI0 to ANI7) with a resolution of 10 bits. The A/D converter has the following function. * 10-bit resolution A/D conversion 10-bit resolution A/D conversion is carried out repeatedly for one analog input channel selected from ANI0 to ANI7. Each time an A/D conversion operation ends, an interrupt request (INTAD) is generated. Figure 13-1. Block Diagram of A/D Converter AVREF ADCS bit ANI0/P20 ANI1/P21 ANI2/P22 ANI3/P23 ANI4/P24 ANI5/P25 ANI6/P26 ANI7/P27 Sample & hold circuit Selector AVSS Successive approximation register (SAR) Tap selector Voltage comparator AVSS Controller A/D conversion result register (ADCR) INTAD 3 4 5 ADS2 ADS1 ADS0 ADPC3 ADPC2 ADPC1 ADPC0 ADCS FR2 FR1 FR0 LV1 LV0 ADCE Analog input channel specification register (ADS) A/D port configuration register (ADPC) Internal bus A/D converter mode register (ADM) 302 User's Manual U17397EJ4V0UD CHAPTER 13 A/D CONVERTER www..com 13.2 Configuration of A/D Converter The A/D converter includes the following hardware. (1) ANI0 to ANI7 pins These are the analog input pins of the 8-channel A/D converter. They input analog signals to be converted into digital signals. Pins other than the one selected as the analog input pin can be used as I/O port pins. (2) Sample & hold circuit The sample & hold circuit samples the input voltage of the analog input pin selected by the selector when A/D conversion is started, and holds the sampled voltage value during A/D conversion. (3) Series resistor string The series resistor string is connected between AVREF and AVSS, and generates a voltage to be compared with the sampled voltage value. Figure 13-2. Circuit Configuration of Series Resistor String AVREF P-ch ADCS Series resistor string AVSS (4) Voltage comparator The voltage comparator compares the sampled voltage value and the output voltage of the series resistor string. (5) Successive approximation register (SAR) This register converts the result of comparison by the voltage comparator, starting from the most significant bit (MSB). When the voltage value is converted into a digital value down to the least significant bit (LSB) (end of A/D conversion), the contents of the SAR register are transferred to the A/D conversion result register (ADCR). (6) 10-bit A/D conversion result register (ADCR) The A/D conversion result is loaded from the successive approximation register to this register each time A/D conversion is completed, and the ADCR register holds the A/D conversion result in its higher 10 bits (the lower 6 bits are fixed to 0). User's Manual U17397EJ4V0UD 303 CHAPTER 13 A/D CONVERTER www..com (7) 8-bit A/D conversion result register (ADCRH) The A/D conversion result is loaded from the successive approximation register to this register each time A/D conversion is completed, and the ADCRH register stores the higher 8 bits of the A/D conversion result. Caution When data is read from ADCR and ADCRH, a wait cycle is generated. Do not read data from ADCR and ADCRH when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 34 CAUTIONS FOR WAIT. (8) Controller This circuit controls the conversion time of an input analog signal that is to be converted into a digital signal, as well as starting and stopping of the conversion operation. When A/D conversion has been completed, this controller generates INTAD. (9) AVREF pin This pin inputs an analog power/reference voltage to the A/D converter. Make this pin the same potential as the VDD pin when port 2 is used as a digital port. The signal input to ANI0 to ANI7 is converted into a digital signal, based on the voltage applied across AVREF and AVSS. (10) AVSS pin This is the ground potential pin of the A/D converter. Always use this pin at the same potential as that of the VSS pin even when the A/D converter is not used. (11) A/D converter mode register (ADM) This register is used to set the conversion time of the analog input signal to be converted, and to start or stop the conversion operation. (12) A/D port configuration register (ADPC) This register switches the ANI0/P20 to ANI7/P27 pins to analog input of A/D converter or digital I/O of port. (13) Analog input channel specification register (ADS) This register is used to specify the port that inputs the analog voltage to be converted into a digital signal. (14) Port mode register 2 (PM2) This register switches the ANI0/P20 to ANI7/P27 pins to input or output. 304 User's Manual U17397EJ4V0UD CHAPTER 13 A/D CONVERTER www..com 13.3 Registers Used in A/D Converter The A/D converter uses the following six registers. * A/D converter mode register (ADM) * A/D port configuration register (ADPC) * Analog input channel specification register (ADS) * Port mode register 2 (PM2) * 10-bit A/D conversion result register (ADCR) * 8-bit A/D conversion result register (ADCRH) (1) A/D converter mode register (ADM) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. ADM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 13-3. Format of A/D Converter Mode Register (ADM) Address: FF28H Symbol ADM <7> ADCS After reset: 00H 6 0 R/W 5 FR2 Note 1 4 FR1 Note 1 3 FR0 Note 1 2 LV1 Note 1 1 LV0 Note 1 <0> ADCE ADCS 0 1 A/D conversion operation control Stops conversion operation Enables conversion operation ADCE 0 1 Stops comparator operation Comparator operation controlNote 2 Enables comparator operation (comparator: 1/2 AVREF operation) Notes 1. 2. For details of FR2 to FR0, LV1, LV0, and A/D conversion, see Table 13-2 A/D Conversion Time Selection. The operation of the comparator is controlled by ADCS and ADCE, and it takes 1 s from operation start to operation stabilization. Therefore, when ADCS is set to 1 after 1 s or more has elapsed from the time ADCE is set to 1, the conversion result at that time has priority over the first conversion result. Otherwise, ignore data of the first conversion. Table 13-1. Settings of ADCS and ADCE ADCS 0 0 ADCE 0 1 A/D Conversion Operation Stop status (DC power consumption path does not exist) Conversion waiting mode (comparator: 1/2 AVREF operation, only comparator consumes power) 1 1 0 1 Conversion mode (comparator operation stopped Note ) Conversion mode (comparator: 1/2 AVREF operation) Note Ignore data of the first conversion because it is not guaranteed range. User's Manual U17397EJ4V0UD 305 CHAPTER 13 A/D CONVERTER www..com Figure 13-4. Timing Chart When Comparator Is Used Comparator: 1/2 AVREF operation ADCE Comparator Conversion operation ADCS Note Conversion waiting Conversion operation Conversion stopped Note To stabilize the internal circuit, the time from the rising of the ADCE bit to the falling of the ADCS bit must be 1 s or longer. Cautions 1. A/D conversion must be stopped before rewriting bits FR0 to FR2, LV1, and LV0 to values other than the identical data. 2. If data is written to ADM, a wait cycle is generated. Do not write data to ADM when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 34 CAUTIONS FOR WAIT. 306 User's Manual U17397EJ4V0UD CHAPTER 13 A/D CONVERTER www..com Table 13-2. A/D Conversion Time Selection (1) 2.7 V AVREF 5.5 V A/D Converter Mode Register (ADM) FR2 0 0 0 0 1 1 FR1 0 0 1 1 0 0 FR0 0 1 0 1 0 1 LV1 0 0 0 0 0 0 LV0 0 0 0 0 0 0 264/fPRS 176/fPRS 132/fPRS 88/fPRS 66/fPRS 44/fPRS Setting prohibited 33.0 s 22.0 s Conversion Time Selection fPRS = 2 MHz Setting prohibited Conversion Clock fPRS = 10 MHz 26.4 s 17.6 s 13.2 s 8.8 s 6.6 s Note fPRS = 20 MHz 13.2 s 8.8 s 6.6 s Note Note (fAD) fPRS/12 fPRS/8 fPRS/6 fPRS/4 fPRS/3 fPRS/2 Note Note Setting prohibited Note Setting prohibited Other than above Note This can be set only when 4.0 V AVREF 5.5 V. (2) 2.3 V AVREF < 2.7 V A/D Converter Mode Register (ADM) FR2 0 0 0 0 1 1 FR1 0 0 1 1 0 0 FR0 0 1 0 1 0 1 LV1 0 0 0 0 0 0 LV0 1 1 1 1 1 1 480/fPRS 320/fPRS 240/fPRS 160/fPRS 120/fPRS 80/fPRS Setting prohibited 60.0 s 40.0 s Conversion Time Selection fPRS = 2 MHz Setting prohibited fPRS = 5 MHz Setting prohibited 64.0 s 48.0 s 32.0 s Setting prohibited Setting prohibited fPRS/12 fPRS/8 fPRS/6 fPRS/4 fPRS/3 fPRS/2 Conversion Clock (fAD) Other than above Cautions 1. Set the conversion times with the following conditions. * 4.0 V AVREF 5.5 V: fAD = 0.6 to 3.6 MHz * 2.7 V AVREF < 4.0 V: fAD = 0.6 to 1.8 MHz * 2.3 V AVREF < 2.7 V: fAD = 0.6 to 1.48 MHz 2. When rewriting FR2 to FR0, LV1, and LV0 to other than the same data, stop A/D conversion once (ADCS = 0) beforehand. 3. Change LV1 and LV0 from the default value, when 2.3 V AVREF < 2.7 V. 4. The above conversion time does not include clock frequency errors. Select conversion time, taking clock frequency errors into consideration. Remark fPRS: Peripheral hardware clock frequency User's Manual U17397EJ4V0UD 307 CHAPTER 13 A/D CONVERTER www..com Figure 13-5. A/D Converter Sampling and A/D Conversion Timing ADCS 1 or ADS rewrite ADCS Sampling timing INTAD Wait periodNote SAR clear Sampling Successive conversion Transfer SAR to ADCR, clear INTAD generation Conversion time Sampling Conversion time Note For details of wait period, see CHAPTER 34 CAUTIONS FOR WAIT. (2) 10-bit A/D conversion result register (ADCR) This register is a 16-bit register that stores the A/D conversion result. The lower 6 bits are fixed to 0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register. The higher 8 bits of the conversion result are stored in FF09H and the lower 2 bits are stored in the higher 2 bits of FF08H. ADCR can be read by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H. Figure 13-6. Format of 10-Bit A/D Conversion Result Register (ADCR) Address: FF08H, FF09H Symbol ADCR After reset: 0000H FF09H R FF08H 0 0 0 0 0 0 Cautions 1. When writing to the A/D converter mode register (ADM), analog input channel specification register (ADS), and A/D port configuration register (ADPC), the contents of ADCR may become undefined. Read the conversion result following conversion completion before writing to ADM, ADS, and ADPC. Using timing other than the above may cause an incorrect conversion result to be read. 2. If data is read from ADCR, a wait cycle is generated. Do not read data from ADCR when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 34 CAUTIONS FOR WAIT. 308 User's Manual U17397EJ4V0UD CHAPTER 13 A/D CONVERTER www..com (3) 8-bit A/D conversion result register (ADCRH) This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 10-bit resolution are stored. ADCRH can be read by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 13-7. Format of 8-Bit A/D Conversion Result Register (ADCRH) Address: FF09H Symbol ADCRH 7 After reset: 00H 6 5 R 4 3 2 1 0 Cautions 1. When writing to the A/D converter mode register (ADM), analog input channel specification register (ADS), and A/D port configuration register (ADPC), the contents of ADCRH may become undefined. Read the conversion result following conversion completion before writing to ADM, ADS, and ADPC. Using timing other than the above may cause an incorrect conversion result to be read. 2. If data is read from ADCRH, a wait cycle is generated. Do not read data from ADCRH when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 34 CAUTIONS FOR WAIT. User's Manual U17397EJ4V0UD 309 CHAPTER 13 A/D CONVERTER www..com (4) Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted. ADS can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 13-8. Format of Analog Input Channel Specification Register (ADS) Address: FF29H Symbol ADS 7 0 After reset: 00H 6 0 5 0 R/W 4 0 3 0 2 ADS2 1 ADS1 0 ADS0 ADS2 0 0 0 0 1 1 1 1 ADS1 0 0 1 1 0 0 1 1 ADS0 0 1 0 1 0 1 0 1 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 Analog input channel specification Cautions 1. Be sure to clear bits 3 to 7 to "0". 2 Set a channel to be used for A/D conversion in the input mode by using port mode register 2 (PM2). 3. If data is written to ADS, a wait cycle is generated. Do not write data to ADS when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 34 CAUTIONS FOR WAIT. 310 User's Manual U17397EJ4V0UD CHAPTER 13 A/D CONVERTER www..com (5) A/D port configuration register (ADPC) This register switches the ANI0/P20 to ANI7/P27 pins to analog input of A/D converter or digital I/O of port. ADPC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 13-9. Format of A/D Port Configuration Register (ADPC) Address: FF2FH Symbol ADPC 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 ADPC3 2 ADPC2 1 ADPC1 0 ADPC0 ADPC3 ADPC2 ADPC1 ADPC0 Analog input (A)/digital I/O (D) switching ANI7/ ANI6/ ANI5/ ANI4/ ANI3/ ANI2/ ANI1/ ANI0/ P27 P26 P25 P24 P23 P22 P21 P20 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 A A A A A A A A D A A A A A A A D D A A A A A A D D D A A A A A D D D D A A A A D D D D D A A A D D D D D D A A D D D D D D D A D D D D D D D D Other than above Setting prohibited Cautions 1. Set a channel to be used for A/D conversion in the input mode by using port mode register 2 (PM2). 2. If data is written to ADPC, a wait cycle is generated. Do not write data to ADPC when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 34 CAUTIONS FOR WAIT. User's Manual U17397EJ4V0UD 311 CHAPTER 13 A/D CONVERTER www..com (6) Port mode register 2 (PM2) When using the ANI0/P20 to ANI7/P27 pins for analog input port, set PM20 to PM27 to 1. The output latches of P20 to P27 at this time may be 0 or 1. If PM20 to PM27 are set to 0, they cannot be used as analog input port pins. PM2 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Figure 13-10. Format of Port Mode Register 2 (PM2) Address: FF22H Symbol PM2 7 PM27 After reset: FFH 6 PM26 R/W 5 PM25 4 PM24 3 PM23 2 PM22 1 PM21 0 PM20 PM2n 0 1 P2n pin I/O mode selection (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off) ANI0/P20 to ANI7/P27 pins are as shown below depending on the settings of ADPC, ADS, and PM2. Table 13-3. Setting Functions of ANI0/P20 to ANI7/P27 Pins ADPC Analog input selection PM2 Input mode ADS Selects ANI. Does not select ANI. Output mode Selects ANI. Does not select ANI. Digital I/O selection Input mode Output mode - - Digital input Digital output ANI0/P20 to ANI7/P27 Pin Analog input (to be converted) Analog input (not to be converted) Setting prohibited 312 User's Manual U17397EJ4V0UD CHAPTER 13 A/D CONVERTER www..com 13.4 A/D Converter Operations 13.4.1 Basic operations of A/D converter <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1 to start the operation of the comparator. <2> Set channels for A/D conversion to analog input by using the A/D port configuration register (ADPC) and set to input mode by using port mode register 2 (PM2). <3> Set A/D conversion time by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of ADM. <4> Select one channel for A/D conversion using the analog input channel specification register (ADS). <5> Start the conversion operation by setting bit 7 (ADCS) of ADM to 1. (<6> to <12> are operations performed by hardware.) <6> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <7> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the sampled voltage is held until the A/D conversion operation has ended. <8> Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to (1/2) AVREF by the tap selector. <9> The voltage difference between the series resistor string voltage tap and sampled voltage is compared by the voltage comparator. If the analog input is greater than (1/2) AVREF, the MSB of SAR remains set to 1. If the analog input is smaller than (1/2) AVREF, the MSB is reset to 0. <10> Next, bit 8 of SAR is automatically set to 1, and the operation proceeds to the next comparison. The series resistor string voltage tap is selected according to the preset value of bit 9, as described below. * Bit 9 = 1: (3/4) AVREF * Bit 9 = 0: (1/4) AVREF The voltage tap and sampled voltage are compared and bit 8 of SAR is manipulated as follows. * Analog input voltage Voltage tap: Bit 8 = 1 * Analog input voltage < Voltage tap: Bit 8 = 0 <11> Comparison is continued in this way up to bit 0 of SAR. <12> Upon completion of the comparison of 10 bits, an effective digital result value remains in SAR, and the result value is transferred to the A/D conversion result register (ADCR, ADCRH) and then latched. At the same time, the A/D conversion end interrupt request (INTAD) can also be generated. <13> Repeat steps <6> to <12>, until ADCS is cleared to 0. To stop the A/D converter, clear ADCS to 0. To restart A/D conversion from the status of ADCE = 1, start from <5>. To start A/D conversion again when ADCE = 0, set ADCE to 1, wait for 1 s or longer, and start <5>. To change a channel of A/D conversion, start from <4>. Caution Make sure the period of <1> to <5> is 1 s or more. Remark Two types of A/D conversion result registers are available. * ADCR (16 bits): Store 10-bit A/D conversion value * ADCRH (8 bits): Store 8-bit A/D conversion value User's Manual U17397EJ4V0UD 313 CHAPTER 13 A/D CONVERTER www..com Figure 13-11. Basic Operation of A/D Converter Conversion time Sampling time A/D converter operation Sampling A/D conversion SAR Undefined Conversion result ADCR Conversion result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software. If a write operation is performed to the analog input channel specification register (ADS) during an A/D conversion operation, the conversion operation is initialized, and if the ADCS bit is set (1), conversion starts again from the beginning. Reset signal generation clears the A/D conversion result register (ADCR, ADCRH) to 0000H or 00H. 314 User's Manual U17397EJ4V0UD CHAPTER 13 A/D CONVERTER www..com 13.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following expression. SAR = INT ( VAIN AVREF x 1024 + 0.5) ADCR = SAR x 64 or ( ADCR 64 - 0.5) x AVREF 1024 VAIN < ( ADCR 64 + 0.5) x AVREF 1024 where, INT( ): VAIN: AVREF: SAR: Function which returns integer part of value in parentheses Analog input voltage AVREF pin voltage Successive approximation register ADCR: A/D conversion result register (ADCR) value Figure 13-12 shows the relationship between the analog input voltage and the A/D conversion result. Figure 13-12. Relationship Between Analog Input Voltage and A/D Conversion Result SAR ADCR 1023 FFC0H 1022 FF80H 1021 A/D conversion result 3 FF40H 00C0H 2 0080H 1 0040H 0 1 1 3 2 5 3 2048 1024 2048 1024 2048 1024 2043 1022 2045 1023 2047 1 2048 1024 2048 1024 2048 0000H Input voltage/AVREF User's Manual U17397EJ4V0UD 315 CHAPTER 13 A/D CONVERTER www..com 13.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to ANI7 by the analog input channel specification register (ADS) and A/D conversion is executed. (1) A/D conversion operation By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1, the A/D conversion operation of the voltage, which is applied to the analog input pin specified by the analog input channel specification register (ADS), is started. When A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result register (ADCR), and an interrupt request signal (INTAD) is generated. When one A/D conversion has been completed, the next A/D conversion operation is immediately started. If ADS is rewritten during A/D conversion, the A/D conversion operation under execution is stopped and restarted from the beginning. If 0 is written to ADCS during A/D conversion, A/D conversion is immediately stopped. conversion result immediately before is retained. Figure 13-13. A/D Conversion Operation Rewriting ADM ADCS = 1 At this time, the Rewriting ADS ADCS = 0 A/D conversion ANIn ANIn ANIn ANIm ANIm Stopped Conversion result immediately before is retained Conversion is stopped Conversion result immediately before is retained ADCR, ADCRH ANIn ANIn ANIm INTAD Remarks 1. n = 0 to 7 2. m = 0 to 7 316 User's Manual U17397EJ4V0UD CHAPTER 13 A/D CONVERTER www..com The setting methods are described below. <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1. <2> Set the channel to be used in the analog input mode by using bits 3 to 0 (ADPC3 to ADPC0) of the A/D port configuration register (ADPC) and bits 7 to 0 (PM27 to PM20) of port mode register 2 (PM2). <3> Select conversion time by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of ADM. <4> Select a channel to be used by using bits 2 to 0 (ADS2 to ADS0) of the analog input channel specification register (ADS). <5> Set bit 7 (ADCS) of ADM to 1 to start A/D conversion. <6> When one A/D conversion has been completed, an interrupt request signal (INTAD) is generated. <7> Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH). User's Manual U17397EJ4V0UD 317 CHAPTER 13 A/D CONVERTER www..com 13.5 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is expressed by %FSR (Full Scale Range). 1LSB is as follows when the resolution is 10 bits. 1LSB = 1/210 = 1/1024 = 0.098%FSR Accuracy has no relation to resolution, but is determined by overall error. (2) Overall error This shows the maximum error value between the actual measured value and the theoretical value. Zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of these express the overall error. Note that the quantization error is not included in the overall error in the characteristics table. (3) Quantization error When analog values are converted to digital values, a 1/2LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of 1/2LSB is converted to the same digital code, so a quantization error cannot be avoided. Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. Figure 13-14. Overall Error 1......1 Figure 13-15. Quantization Error 1......1 Ideal line Digital output Overall error Digital output 1/2LSB Quantization error 1/2LSB 0......0 0 Analog input AVREF 0......0 0 Analog input AVREF (4) Zero-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2LSB) when the digital output changes from 0......000 to 0......001. If the actual measurement value is greater than the theoretical value, it shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 0......001 to 0......010. 318 User's Manual U17397EJ4V0UD CHAPTER 13 A/D CONVERTER www..com (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale - 3/2LSB) when the digital output changes from 1......110 to 1......111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. (7) Differential linearity error While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value and the ideal value. Figure 13-16. Zero-Scale Error 111 Digital output (Lower 3 bits) Full-scale error Figure 13-17. Full-Scale Error Ideal line 011 Digital output (Lower 3 bits) 111 010 001 000 0 1 2 3 AVREF Analog input (LSB) 110 Zero-scale error 101 Ideal line 000 0 AVREF-3 AVREF-2 AVREF-1 AVREF Analog input (LSB) Figure 13-18. Integral Linearity Error 1......1 Ideal line Digital output Figure 13-19. Differential Linearity Error 1......1 Ideal 1LSB width Digital output 0......0 0 Integral linearity error Analog input AVREF Differential linearity error 0......0 0 Analog input AVREF (8) Conversion time This expresses the time from the start of sampling to when the digital output is obtained. The sampling time is included in the conversion time in the characteristics table. (9) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. Sampling time Conversion time User's Manual U17397EJ4V0UD 319 CHAPTER 13 A/D CONVERTER www..com 13.6 Cautions for A/D Converter (1) Operating current in STOP mode The A/D converter stops operating in the STOP mode. At this time, the operating current can be reduced by clearing bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0. To restart from the standby status, clear bit 0 (ADIF) of interrupt request flag register 1L (IF1L) to 0 and start operation. (2) Input range of ANI0 to ANI7 Observe the rated range of the ANI0 to ANI7 input voltage. If a voltage of AVREF or higher and AVSS or lower (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. In addition, the converted values of the other channels may also be affected. (3) Conflicting operations <1> Conflict between A/D conversion result register (ADCR, ADCRH) write and ADCR or ADCRH read by instruction upon the end of conversion ADCR or ADCRH read has priority. After the read operation, the new conversion result is written to ADCR or ADCRH. <2> Conflict between ADCR or ADCRH write and A/D converter mode register (ADM) write, analog input channel specification register (ADS), or A/D port configuration register (ADPC) write upon the end of conversion ADM, ADS, or ADPC write has priority. ADCR or ADCRH write is not performed, nor is the conversion end interrupt signal (INTAD) generated. (4) Noise countermeasures To maintain the 10-bit resolution, attention must be paid to noise input to the AVREF pin and pins ANI0 to ANI7. <1> Connect a capacitor with a low equivalent resistance and a good frequency response to the power supply. <2> The higher the output impedance of the analog input source, the greater the influence. To reduce the noise, connecting external C as shown in Figure 13-20 is recommended. <3> Do not switch these pins with other pins during conversion. <4> The accuracy is improved if the HALT mode is set immediately after the start of conversion. 320 User's Manual U17397EJ4V0UD CHAPTER 13 A/D CONVERTER www..com Figure 13-20. Analog Input Pin Connection If there is a possibility that noise equal to or higher than AVREF or equal to or lower than AVSS may enter, clamp with a diode with a small VF value (0.3 V or lower). Reference voltage input AVREF ANI0 to ANI7 C = 100 to 1,000 pF AVSS VSS (5) ANI0/P20 to ANI7/P27 <1> The analog input pins (ANI0 to ANI7) are also used as I/O port pins (P20 to P27). When A/D conversion is performed with any of ANI0 to ANI7 selected, do not access P20 to P27 while conversion is in progress; otherwise the conversion resolution may be degraded. It is recommended to select pins used as P20 to P27 starting with the ANI0/P20 that is the furthest from AVREF. <2> If a digital pulse is applied to the pins adjacent to the pins currently used for A/D conversion, the expected value of the A/D conversion may not be obtained due to coupling noise. Therefore, do not apply a pulse to the pins adjacent to the pin undergoing A/D conversion. (6) Input impedance of ANI0 to ANI7 pins This A/D converter charges a sampling capacitor for sampling during sampling time. Therefore, only a leakage current flows when sampling is not in progress, and a current that charges the capacitor flows during sampling. Consequently, the input impedance fluctuates depending on whether sampling is in progress, and on the other states. To make sure that sampling is effective, however, it is recommended to keep the output impedance of the analog input source to within 10 k, and to connect a capacitor of about 100 pF to the ANI0 to ANI7 pins (see Figure 1320). (7) AVREF pin input impedance A series resistor string of several tens of k is connected between the AVREF and AVSS pins. Therefore, if the output impedance of the reference voltage source is high, this will result in a series connection to the series resistor string between the AVREF and AVSS pins, resulting in a large reference voltage error. User's Manual U17397EJ4V0UD 321 CHAPTER 13 A/D CONVERTER www..com (8) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may be set just before the ADS rewrite. Caution is therefore required since, at this time, when ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the postchange analog input has not ended. When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed. Figure 13-21. Timing of A/D Conversion End Interrupt Request Generation ADS rewrite (start of ANIn conversion) ADS rewrite (start of ANIm conversion) ADIF is set but ANIm conversion has not ended. A/D conversion ANIn ANIn ANIm ANIm ADCR ANIn ANIn ANIm ANIm ADIF Remarks 1. n = 0 to 7 2. m = 0 to 7 (9) Conversion results just after A/D conversion start The first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the ADCS bit is set to 1 within 1 s after the ADCE bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit = 0. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first conversion result. (10) A/D conversion result register (ADCR, ADCRH) read operation When a write operation is performed to the A/D converter mode register (ADM), analog input channel specification register (ADS), and A/D port configuration register (ADPC), the contents of ADCR and ADCRH may become undefined. Read the conversion result following conversion completion before writing to ADM, ADS, and ADPC. Using a timing other than the above may cause an incorrect conversion result to be read. 322 User's Manual U17397EJ4V0UD CHAPTER 13 A/D CONVERTER www..com (11) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 13-22. Internal Equivalent Circuit of ANIn Pin R1 ANIn C1 C2 Table 13-4. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) AVREF 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 2.3 V AVREF < 2.7 V R1 8.1 k 31 k 381 k C1 8 pF 8 pF 8 pF C2 5 pF 5 pF 5 pF Remarks 1. The resistance and capacitance values shown in Table 13-4 are not guaranteed values. 2. n = 0 to 7 User's Manual U17397EJ4V0UD 323 www..com CHAPTER 14 SERIAL INTERFACE UART0 14.1 Functions of Serial Interface UART0 Serial interface UART0 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption. For details, see 14.4.1 Operation stop mode. (2) Asynchronous serial interface (UART) mode The functions of this mode are outlined below. For details, see 14.4.2 generator. * Maximum transfer rate: 625 kbps * Two-pin configuration TXD0: Transmit data output pin RXD0: Receive data input pin * Length of communication data can be selected from 7 or 8 bits. * Dedicated on-chip 5-bit baud rate generator allowing any baud rate to be set * Transmission and reception can be performed independently (full-duplex operation). * Fixed to LSB-first communication Cautions 1. If clock supply to serial interface UART0 is not stopped (e.g., in the HALT mode), normal operation continues. If clock supply to serial interface UART0 is stopped (e.g., in the STOP mode), each register stops operating, and holds the value immediately before clock supply was stopped. The TXD0 pin also holds the value immediately before clock supply was stopped and outputs it. However, the operation is not guaranteed after clock supply is resumed. Therefore, reset the circuit so that POWER0 = 0, RXE0 = 0, and TXE0 = 0. 2. Set POWER0 = 1 and then set TXE0 = 1 (transmission) or RXE0 = 1 (reception) to start communication. 3. TXE0 and RXE0 are synchronized by the base clock (fXCLK0) set by BRGC0. To enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base clock, the transmission circuit or reception circuit may not be initialized. 4. Set transmit data to TXS0 at least one base clock (fXCLK0) after setting TXE0 = 1. Asynchronous serial interface (UART) mode and 14.4.3 Dedicated baud rate 324 User's Manual U17397EJ4V0UD CHAPTER 14 SERIAL INTERFACE UART0 www..com 14.2 Configuration of Serial Interface UART0 Serial interface UART0 includes the following hardware. Table 14-1. Configuration of Serial Interface UART0 Item Registers Receive buffer register 0 (RXB0) Receive shift register 0 (RXS0) Transmit shift register 0 (TXS0) Control registers Asynchronous serial interface operation mode register 0 (ASIM0) Asynchronous serial interface reception error status register 0 (ASIS0) Baud rate generator control register 0 (BRGC0) Port mode register 1 (PM1) Port register 1 (P1) Configuration User's Manual U17397EJ4V0UD 325 Selector 326 fPRS/2 fPRS/23 fPRS/25 8-bit timer/ event counter 50 output Asynchronous serial interface operation mode register 0 (ASIM0) Figure 14-1. Block Diagram of Serial Interface UART0 Filter RXD0/ SI10/P11 Receive shift register 0 (RXS0) Asynchronous serial interface reception error status register 0 (ASIS0) Baud rate generator Reception unit INTSR0 Reception control Receive buffer register 0 (RXB0) CHAPTER 14 SERIAL INTERFACE UART0 Internal bus User's Manual U17397EJ4V0UD Baud rate generator control register 0 (BRGC0) 7 7 Baud rate generator INTST0 Transmission control Transmit shift register 0 (TXS0) Output latch (P10) PM10 TXD0/ SCK10/P10 Registers Transmission unit www..com CHAPTER 14 SERIAL INTERFACE UART0 www..com (1) Receive buffer register 0 (RXB0) This 8-bit register stores parallel data converted by receive shift register 0 (RXS0). Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 0 (RXS0). If the data length is set to 7 bits the receive data is transferred to bits 0 to 6 of RXB0 and the MSB of RXB0 is always 0. If an overrun error (OVE0) occurs, the receive data is not transferred to RXB0. RXB0 can be read by an 8-bit memory manipulation instruction. No data can be written to this register. Reset signal generation and POWER0 = 0 set this register to FFH. (2) Receive shift register 0 (RXS0) This register converts the serial data input to the RXD0 pin into parallel data. RXS0 cannot be directly manipulated by a program. (3) Transmit shift register 0 (TXS0) This register is used to set transmit data. Transmission is started when data is written to TXS0, and serial data is transmitted from the TXD0 pins. TXS0 can be written by an 8-bit memory manipulation instruction. This register cannot be read. Reset signal generation, POWER0 = 0, and TXE0 = 0 set this register to FFH. Cautions 1. Set transmit data to TXS0 at least one base clock (fXCLK0) after setting TXE0 = 1. 2. Do not write the next transmit data to TXS0 before the transmission completion interrupt signal (INTST0) is generated. User's Manual U17397EJ4V0UD 327 CHAPTER 14 SERIAL INTERFACE UART0 www..com 14.3 Registers Controlling Serial Interface UART0 Serial interface UART0 is controlled by the following five registers. * Asynchronous serial interface operation mode register 0 (ASIM0) * Asynchronous serial interface reception error status register 0 (ASIS0) * Baud rate generator control register 0 (BRGC0) * Port mode register 1 (PM1) * Port register 1 (P1) (1) Asynchronous serial interface operation mode register 0 (ASIM0) This 8-bit register controls the serial communication operations of serial interface UART0. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 01H. Figure 14-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (1/2) Address: FF70H After reset: 01H R/W Symbol ASIM0 <7> POWER0 <6> TXE0 <5> RXE0 4 PS01 3 PS00 2 CL0 1 SL0 0 1 POWER0 0 Note 1 Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit Note 2 . 1 Enables operation of the internal operation clock. TXE0 0 1 Enables/disables transmission Disables transmission (synchronously resets the transmission circuit). Enables transmission. RXE0 0 1 Enables/disables reception Disables reception (synchronously resets the reception circuit). Enables reception. Notes 1. 2. The input from the RXD0 pin is fixed to high level when POWER0 = 0. Asynchronous serial interface reception error status register 0 (ASIS0), transmit shift register 0 (TXS0), and receive buffer register 0 (RXB0) are reset. 328 User's Manual U17397EJ4V0UD CHAPTER 14 SERIAL INTERFACE UART0 www..com Figure 14-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (2/2) PS01 0 0 1 1 PS00 0 1 0 1 Transmission operation Does not output parity bit. Outputs 0 parity. Outputs odd parity. Outputs even parity. Reception operation Reception without parity Reception as 0 parity Note Judges as odd parity. Judges as even parity. CL0 0 1 Specifies character length of transmit/receive data Character length of data = 7 bits Character length of data = 8 bits SL0 0 1 Number of stop bits = 1 Number of stop bits = 2 Specifies number of stop bits of transmit data Note If "reception as 0 parity" is selected, the parity is not judged. Therefore, bit 2 (PE0) of asynchronous serial interface reception error status register 0 (ASIS0) is not set and the error interrupt does not occur. Cautions 1. To start the transmission, set POWER0 to 1 and then set TXE0 to 1. To stop the transmission, clear TXE0 to 0, and then clear POWER0 to 0. 2. To start the reception, set POWER0 to 1 and then set RXE0 to 1. To stop the reception, clear RXE0 to 0, and then clear POWER0 to 0. 3. Set POWER0 to 1 and then set RXE0 to 1 while a high level is input to the RxD0 pin. If POWER0 is set to 1 and RXE0 is set to 1 while a low level is input, reception is started. 4. TXE0 and RXE0 are synchronized by the base clock (fXCLK0) set by BRGC0. To enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base clock, the transmission circuit or reception circuit may not be initialized. 5. Set transmit data to TXS0 at least one base clock (fXCLK0) after setting TXE0 = 1. 6. Clear the TXE0 and RXE0 bits to 0 before rewriting the PS01, PS00, and CL0 bits. 7. Make sure that TXE0 = 0 when rewriting the SL0 bit. Reception is always performed with "number of stop bits = 1", and therefore, is not affected by the set value of the SL0 bit. 8. Be sure to set bit 0 to 1. User's Manual U17397EJ4V0UD 329 CHAPTER 14 SERIAL INTERFACE UART0 www..com (2) Asynchronous serial interface reception error status register 0 (ASIS0) This register indicates an error status on completion of reception by serial interface UART0. It includes three error flag bits (PE0, FE0, OVE0). This register is read-only by an 8-bit memory manipulation instruction. Reset signal generation, or clearing bit 7 (POWER0) or bit 5 (RXE0) of ASIM0 to 0 clears this register to 00H. 00H is read when this register is read. If a reception error occurs, read ASIS0 and then read receive buffer register 0 (RXB0) to clear the error flag. Figure 14-3. Format of Asynchronous Serial Interface Reception Error Status Register 0 (ASIS0) Address: FF73H After reset: 00H R Symbol ASIS0 7 0 6 0 5 0 4 0 3 0 2 PE0 1 FE0 0 OVE0 PE0 0 1 Status flag indicating parity error If POWER0 = 0 or RXE0 = 0, or if ASIS0 register is read. If the parity of transmit data does not match the parity bit on completion of reception. FE0 0 1 Status flag indicating framing error If POWER0 = 0 or RXE0 = 0, or if ASIS0 register is read. If the stop bit is not detected on completion of reception. OVE0 0 1 Status flag indicating overrun error If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read. If receive data is set to the RXB0 register and the next reception operation is completed before the data is read. Cautions 1. The operation of the PE0 bit differs depending on the set values of the PS01 and PS00 bits of asynchronous serial interface operation mode register 0 (ASIM0). 2. Only the first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. 3. If an overrun error occurs, the next receive data is not written to receive buffer register 0 (RXB0) but discarded. 4. If data is read from ASIS0, a wait cycle is generated. Do not read data from ASIS0 when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 34 CAUTIONS FOR WAIT. 330 User's Manual U17397EJ4V0UD CHAPTER 14 SERIAL INTERFACE UART0 www..com (3) Baud rate generator control register 0 (BRGC0) This register selects the base clock of serial interface UART0 and the division value of the 5-bit counter. BRGC0 can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 1FH. Figure 14-4. Format of Baud Rate Generator Control Register 0 (BRGC0) Address: FF71H After reset: 1FH R/W Symbol BRGC0 7 TPS01 6 TPS00 5 0 4 MDL04 3 MDL03 2 MDL02 1 MDL01 0 MDL00 TPS01 TPS00 Base clock (fXCLK0) selection fPRS = 2 MHz fPRS = 5 MHz fPRS = 10 MHz fPRS = 20 MHz 0 0 1 1 0 1 0 1 TM50 output fPRS/2 fPRS/2 fPRS/2 3 Note 1 MHz 250 kHz 62.5 kHz 2.5 MHz 625 kHz 156.25 kHz 5 MHz 1.25 MHz 312.5 kHz 10 MHz 2.5 MHz 625 kHz 5 MDL04 0 0 0 0 * * * * * 1 1 1 1 1 1 MDL03 0 1 1 1 * * * * * 1 1 1 1 1 1 MDL02 x 0 0 0 * * * * * 0 0 1 1 1 1 MDL01 x 0 0 1 * * * * * 1 1 0 0 1 1 MDL00 x 0 1 0 * * * * * 0 1 0 1 0 1 k x 8 9 10 * * * * * 26 27 28 29 30 31 Selection of 5-bit counter output clock Setting prohibited fXCLK0/8 fXCLK0/9 fXCLK0/10 * * * * * fXCLK0/26 fXCLK0/27 fXCLK0/28 fXCLK0/29 fXCLK0/30 fXCLK0/31 Note Note the following points when selecting the TM50 output as the base clock. * Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0) Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion operation (TMC501 = 1). * PWM mode (TMC506 = 1) Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty = 50%. It is not necessary to enable the TO50 pin as a timer output pin in any mode. User's Manual U17397EJ4V0UD 331 CHAPTER 14 SERIAL INTERFACE UART0 www..com Cautions 1. Make sure that bit 6 (TXE0) and bit 5 (RXE0) of the ASIM0 register = 0 when rewriting the MDL04 to MDL00 bits. 2. The baud rate value is the output clock of the 5-bit counter divided by 2. Remarks 1. fXCLK0: Frequency of base clock selected by the TPS01 and TPS00 bits 2. fPRS: 3. k: 4. x: Peripheral hardware clock frequency Value set by the MDL04 to MDL00 bits (k = 8, 9, 10, ..., 31) Don't care 5. TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50) TMC501: Bit 1 of TMC50 (4) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using the P10/TxD0/SCK10 pin for serial interface data output, clear PM10 to 0 and set the output latch of P10 to 1. When using the P11/RxD0/SI10 pin for serial interface data input, set PM11 to 1. The output latch of P11 at this time may be 0 or 1. PM1 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Figure 14-5. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol PM1 7 PM17 After reset: FFH 6 PM16 R/W 5 PM15 4 PM14 3 PM13 2 PM12 1 PM11 0 PM10 PM1n 0 1 P1n pin I/O mode selection (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off) 332 User's Manual U17397EJ4V0UD CHAPTER 14 SERIAL INTERFACE UART0 www..com 14.4 Operation of Serial Interface UART0 Serial interface UART0 has the following two modes. * Operation stop mode * Asynchronous serial interface (UART) mode 14.4.1 Operation stop mode In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the pins can be used as ordinary port pins in this mode. To set the operation stop mode, clear bits 7, 6, and 5 (POWER0, TXE0, and RXE0) of ASIM0 to 0. (1) Register used The operation stop mode is set by asynchronous serial interface operation mode register 0 (ASIM0). ASIM0 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 01H. Address: FF70H After reset: 01H R/W Symbol ASIM0 <7> POWER0 <6> TXE0 <5> RXE0 4 PS01 3 PS00 2 CL0 1 SL0 0 1 POWER0 0 Note 1 Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit Note 2 . TXE0 0 Enables/disables transmission Disables transmission (synchronously resets the transmission circuit). RXE0 0 Enables/disables reception Disables reception (synchronously resets the reception circuit). Notes 1. 2. The input from the RXD0 pin is fixed to high level when POWER0 = 0. Asynchronous serial interface reception error status register 0 (ASIS0), transmit shift register 0 (TXS0), and receive buffer register 0 (RXB0) are reset. Caution Clear POWER0 to 0 after clearing TXE0 and RXE0 to 0 to set the operation stop mode. To start the communication, set POWER0 to 1, and then set TXE0 or RXE0 to 1. Remark To use the RxD0/SI10/P11 and TxD0/SCK10/P10 pins as general-purpose port pins, see CHAPTER 5 PORT FUNCTIONS. User's Manual U17397EJ4V0UD 333 CHAPTER 14 SERIAL INTERFACE UART0 www..com 14.4.2 Asynchronous serial interface (UART) mode In this mode, 1-byte data is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) Registers used * Asynchronous serial interface operation mode register 0 (ASIM0) * Asynchronous serial interface reception error status register 0 (ASIS0) * Baud rate generator control register 0 (BRGC0) * Port mode register 1 (PM1) * Port register 1 (P1) The basic procedure of setting an operation in the UART mode is as follows. <1> Set the BRGC0 register (see Figure 14-4). <2> Set bits 1 to 4 (SL0, CL0, PS00, and PS01) of the ASIM0 register (see Figure 14-2). <3> Set bit 7 (POWER0) of the ASIM0 register to 1. <4> Set bit 6 (TXE0) of the ASIM0 register to 1. Transmission is enabled. Set bit 5 (RXE0) of the ASIM0 register to 1. Reception is enabled. <5> Write data to the TXS0 register. Data transmission is started. Caution Take relationship with the other party of communication when setting the port mode register and port register. The relationship between the register settings and pins is shown below. Table 14-2. Relationship Between Register Settings and Pins POWER0 TXE0 RXE0 PM10 P10 PM11 P11 UART0 Operation 0 1 0 0 1 1 0 1 0 1 x x Note Pin Function TxD0/SCK10/P10 SCK10/P10 SCK10/P10 TxD0 TxD0 RxD0/SI10/P11 SI10/P11 RxD0 SI10/P11 RxD0 x x Note x Note x Note Stop Reception Transmission Transmission/ reception Note Note 1 x Note x x Note 0 0 1 1 1 x Note Can be set as port function or serial interface CSI10. Remark x: TXE0: RXE0: PM1x: P1x: don't care Bit 6 of ASIM0 Bit 5 of ASIM0 Port mode register Port output latch POWER0: Bit 7 of asynchronous serial interface operation mode register 0 (ASIM0) 334 User's Manual U17397EJ4V0UD CHAPTER 14 SERIAL INTERFACE UART0 www..com (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 14-6 and 14-7 show the format and waveform example of the normal transmit/receive data. Figure 14-6. Format of Normal UART Transmit/Receive Data 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bit Character bits One data frame consists of the following bits. * Start bit ... 1 bit * Character bits ... 7 or 8 bits (LSB first) * Parity bit ... Even parity, odd parity, 0 parity, or no parity * Stop bit ... 1 or 2 bits The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface operation mode register 0 (ASIM0). Figure 14-7. Example of Normal UART Transmit/Receive Data Waveform 1. Data length: 8 bits, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop 2. Data length: 7 bits, Parity: Odd parity, Stop bit: 2 bits, Communication data: 36H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 Parity Stop Stop 3. Data length: 8 bits, Parity: None, Stop bit: 1 bit, Communication data: 87H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 D7 Stop User's Manual U17397EJ4V0UD 335 CHAPTER 14 SERIAL INTERFACE UART0 www..com (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected. With zero parity and no parity, an error cannot be detected. (i) Even parity * Transmission Transmit data, including the parity bit, is controlled so that the number of bits that are "1" is even. The value of the parity bit is as follows. If transmit data has an odd number of bits that are "1": 1 If transmit data has an even number of bits that are "1": 0 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is odd, a parity error occurs. (ii) Odd parity * Transmission Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are "1" is odd. If transmit data has an odd number of bits that are "1": 0 If transmit data has an even number of bits that are "1": 1 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is even, a parity error occurs. (iii) 0 parity The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. The parity bit is not detected when the data is received. Therefore, a parity error does not occur regardless of whether the parity bit is "0" or "1". (iv) No parity No parity bit is appended to the transmit data. Reception is performed assuming that there is no parity bit when data is received. Because there is no parity bit, a parity error does not occur. 336 User's Manual U17397EJ4V0UD CHAPTER 14 SERIAL INTERFACE UART0 www..com (c) Transmission If bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1 and bit 6 (TXE0) of ASIM0 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit shift register 0 (TXS0). The start bit, parity bit, and stop bit are automatically appended to the data. When transmission is started, the start bit is output from the TXD0 pin, and the transmit data is output followed by the rest of the data in order starting from the LSB. When transmission is completed, the parity and stop bits set by ASIM0 are appended and a transmission completion interrupt request (INTST0) is generated. Transmission is stopped until the data to be transmitted next is written to TXS0. Figure 14-8 shows the timing of the transmission completion interrupt request (INTST0). This interrupt occurs as soon as the last stop bit has been output. Caution After transmit data is written to TXS0, do not write the next transmit data before the transmission completion interrupt signal (INTST0) is generated. Figure 14-8. Transmission Completion Interrupt Request Timing 1. Stop bit length: 1 TXD0 (output) Start D0 D1 D2 D6 D7 Parity Stop INTST0 2. Stop bit length: 2 TXD0 (output) Start D0 D1 D2 D6 D7 Parity Stop INTST0 User's Manual U17397EJ4V0UD 337 CHAPTER 14 SERIAL INTERFACE UART0 www..com (d) Reception Reception is enabled and the RXD0 pin input is sampled when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1 and then bit 5 (RXE0) of ASIM0 is set to 1. The 5-bit counter of the baud rate generator starts counting when the falling edge of the RXD0 pin input is detected. When the set value of baud rate generator control register 0 (BRGC0) has been counted, the RXD0 pin input is sampled again ( as a start bit. When the start bit is detected, reception is started, and serial data is sequentially stored in receive shift register 0 (RXS0) at the set baud rate. When the stop bit has been received, the reception completion interrupt (INTSR0) is generated and the data of RXS0 is written to receive buffer register 0 (RXB0). If an overrun error (OVE0) occurs, however, the receive data is not written to RXB0. Even if a parity error (PE0) occurs while reception is in progress, reception continues to the reception position of the stop bit, and an reception error interrupt (INTSR0) is generated after completion of reception. INTSR0 occurs upon completion of reception and in case of a reception error. Figure 14-9. Reception Completion Interrupt Request Timing in Figure 14-9). If the RXD0 pin is low level at this time, it is recognized RXD0 (input) Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop INTSR0 RXB0 Cautions 1. If a reception error occurs, read asynchronous serial interface reception error status register 0 (ASIS0) and then read receive buffer register 0 (RXB0) to clear the error flag. Otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. 2. Reception is always performed with the "number of stop bits = 1". The second stop bit is ignored. 338 User's Manual U17397EJ4V0UD CHAPTER 14 SERIAL INTERFACE UART0 www..com (e) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 0 (ASIS0) is set as a result of data reception, a reception error interrupt (INTSR0) is generated. Which error has occurred during reception can be identified by reading the contents of ASIS0 in the reception error interrupt (INTSR0) servicing (see Figure 14-3). The contents of ASIS0 are cleared to 0 when ASIS0 is read. Table 14-3. Cause of Reception Error Reception Error Parity error Framing error Overrun error Cause The parity specified for transmission does not match the parity of the receive data. Stop bit is not detected. Reception of the next data is completed before data is read from receive buffer register 0 (RXB0). (f) Noise filter of receive data The RXD0 signal is sampled using the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data. Because the circuit is configured as shown in Figure 14-10, the internal processing of the reception operation is delayed by two clocks from the external signal status. Figure 14-10. Noise Filter Circuit Base clock RXD0/SI10/P11 In Q Internal signal A In Q Internal signal B Match detector LD_EN User's Manual U17397EJ4V0UD 339 CHAPTER 14 SERIAL INTERFACE UART0 www..com 14.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and a 5-bit programmable counter, and generates a serial clock for transmission/reception of UART0. Separate 5-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator * Base clock The clock selected by bits 7 and 6 (TPS01 and TPS00) of baud rate generator control register 0 (BRGC0) is supplied to each module when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is 1. This clock is called the base clock and its frequency is called fXCLK0. The base clock is fixed to low level when POWER0 = 0. * Transmission counter This counter stops operation, cleared to 0, when bit 7 (POWER0) or bit 6 (TXE0) of asynchronous serial interface operation mode register 0 (ASIM0) is 0. It starts counting when POWER0 = 1 and TXE0 = 1. The counter is cleared to 0 when the first data transmitted is written to transmit shift register 0 (TXS0). * Reception counter This counter stops operation, cleared to 0, when bit 7 (POWER0) or bit 5 (RXE0) of asynchronous serial interface operation mode register 0 (ASIM0) is 0. It starts counting when the start bit has been detected. The counter stops operation after one frame has been received, until the next start bit is detected. Figure 14-11. Configuration of Baud Rate Generator POWER0 Baud rate generator fPRS/2 POWER0, TXE0 (or RXE0) fPRS/23 Selector fPRS/25 8-bit timer/ event counter 50 output fXCLK0 5-bit counter Match detector 1/2 Baud rate BRGC0: TPS01, TPS00 BRGC0: MDL04 to MDL00 Remark POWER0: Bit 7 of asynchronous serial interface operation mode register 0 (ASIM0) TXE0: RXE0: BRGC0: Bit 6 of ASIM0 Bit 5 of ASIM0 Baud rate generator control register 0 User's Manual U17397EJ4V0UD 340 CHAPTER 14 SERIAL INTERFACE UART0 www..com (2) Generation of serial clock A serial clock to be generated can be specified by using baud rate generator control register 0 (BRGC0). Select the clock to be input to the 5-bit counter by using bits 7 and 6 (TPS01 and TPS00) of BRGC0. Bits 4 to 0 (MDL04 to MDL00) of BRGC0 can be used to select the division value (fXCLK0/8 to fXCLK0/31) of the 5-bit counter. 14.4.4 Calculation of baud rate (1) Baud rate calculation expression The baud rate can be calculated by the following expression. * Baud rate = fXCLK0 2xk [bps] fXCLK0: Frequency of base clock selected by the TPS01 and TPS00 bits of the BRGC0 register k: Value set by the MDL04 to MDL00 bits of the BRGC0 register (k = 8, 9, 10, ..., 31) Table 14-4. Set Value of TPS01 and TPS00 TPS01 TPS00 Base clock (fXCLK0) selection fPRS = 2 MHz 0 0 1 1 0 1 0 1 TM50 output fPRS/2 fPRS/2 fPRS/2 3 fPRS = 5 MHz fPRS = 10 MHz fPRS = 20 MHz 1 MHz 250 kHz 62.5 kHz 2.5 MHz 625 kHz 156.25 kHz 5 MHz 1.25 MHz 312.5 kHz 10 MHz 2.5 MHz 625 kHz 5 (2) Error of baud rate The baud rate error can be calculated by the following expression. * Error (%) = Actual baud rate (baud rate with error) Desired baud rate (correct baud rate) - 1 x 100 [%] Cautions 1. Keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. Make sure that the baud rate error during reception satisfies the range shown in (4) Permissible baud rate range during reception. Example: Frequency of base clock = 2.5 MHz = 2,500,000 Hz Set value of MDL04 to MDL00 bits of BRGC0 register = 10000B (k = 16) Target baud rate = 76,800 bps Baud rate = 2.5 M/(2 x 16) = 2,500,000/(2 x 16) = 78,125 [bps] Error = (78,125/76,800 - 1) x 100 = 1.725 [%] User's Manual U17397EJ4V0UD 341 CHAPTER 14 SERIAL INTERFACE UART0 www..com (3) Example of setting baud rate Table 14-5. Set Data of Baud Rate Generator Baud Rate [bps] 4800 9600 10400 19200 24000 31250 33660 38400 56000 62500 76800 115200 153600 312500 625000 TPS01, TPS00 fPRS = 2.0 MHz k Calculated ERR TPS01, Value fPRS = 5.0 MHz k Calculated ERR TPS01, Value fPRS = 10.0 MHz k - 16 15 8 26 20 18 16 11 10 8 22 16 8 - Calculated ERR TPS01, Value fPRS = 20.0 MHz k - - 30 16 13 10 9 8 22 20 16 11 8 16 8 Calculated ERR Value [%] 0.16 0.16 0.16 0.16 -0.79 0 -0.79 0.16 -0.79 0 - - - - - TPS00 [%] 1.73 1.73 0.16 1.73 0.16 0 3.34 1.73 1.46 0 1.73 TPS00 [%] - 1.73 0.16 1.73 0.16 0 3.34 1.73 1.46 0 1.73 TPS00 [%] - - 0.16 1.73 0.16 0 3.34 1.73 1.46 0 1.73 2H 2H 2H 1H 1H 1H 1H 1H 1H 1H - - - - - 26 13 12 26 21 16 15 13 9 8 - - - - - 4808 9615 10417 19231 23810 31250 33333 38462 55556 62500 - - - - - 3H 3H 2H 2H 2H 2H 2H 2H 1H 1H 1H 1H 1H - - 16 8 30 16 13 10 9 8 22 20 16 11 8 - - 4883 9766 10417 19531 24038 31250 34722 39063 56818 62500 78125 - 3H 3H 3H 2H 2H 2H 2H 2H 2H 2H 1H 1H 1H - - 9766 10417 19531 24038 31250 34722 39063 56818 62500 78125 - - 3H 3H 3H 3H 3H 3H 2H 2H 2H 2H 2H 1H 1H - - 10417 19531 24038 31250 34722 39063 56818 62500 78125 113636 -1.36 156250 - - 1.73 - - 113636 -1.36 156250 312500 - 1.73 0 - 113636 -1.36 156250 312500 625000 1.73 0 0 Remark TPS01, TPS00: Bits 7 and 6 of baud rate generator control register 0 (BRGC0) (setting of base clock (fXCLK0)) k: fPRS: ERR: Value set by the MDL04 to MDL00 bits of BRGC0 (k = 8, 9, 10, ..., 31) Peripheral hardware clock frequency Baud rate error 342 User's Manual U17397EJ4V0UD CHAPTER 14 SERIAL INTERFACE UART0 www..com (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. Figure 14-12. Permissible Baud Rate Range During Reception Latch timing Data frame length of UART0 Start bit Bit 0 FL Bit 1 Bit 7 Parity bit Stop bit 1 data frame (11 x FL) Minimum permissible data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmin Maximum permissible data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmax As shown in Figure 14-12, the latch timing of the receive data is determined by the counter set by baud rate generator control register 0 (BRGC0) after the start bit has been detected. If the last data (stop bit) meets this latch timing, the data can be correctly received. Assuming that 11-bit data is received, the theoretical values can be calculated as follows. FL = (Brate)-1 Brate: Baud rate of UART0 k: FL: Set value of BRGC0 1-bit data length Margin of latch timing: 2 clocks User's Manual U17397EJ4V0UD 343 CHAPTER 14 SERIAL INTERFACE UART0 www..com Minimum permissible data frame length: FLmin = 11 x FL - k-2 2k x FL = 21k + 2 2k FL Therefore, the maximum receivable baud rate at the transmission destination is as follows. BRmax = (FLmin/11)-1 = 22k 21k + 2 Brate Similarly, the maximum permissible data frame length can be calculated as follows. 10 11 k+2 2xk 21k - 2 2xk x FLmax = 11 x FL - 21k - 2 20k x FL = FL FLmax = FL x 11 Therefore, the minimum receivable baud rate at the transmission destination is as follows. BRmin = (FLmax/11)-1 = 20k 21k - 2 Brate The permissible baud rate error between UART0 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. Table 14-6. Maximum/Minimum Permissible Baud Rate Error Division Ratio (k) 8 16 24 31 Maximum Permissible Baud Rate Error +3.53% +4.14% +4.34% +4.44% Minimum Permissible Baud Rate Error -3.61% -4.19% -4.38% -4.47% Remarks 1. The permissible error of reception depends on the number of bits in one frame, input clock frequency, and division ratio (k). The higher the input clock frequency and the higher the division ratio (k), the higher the permissible error. 2. k: Set value of BRGC0 344 User's Manual U17397EJ4V0UD www..com CHAPTER 15 SERIAL INTERFACE UART6 15.1 Functions of Serial Interface UART6 Serial interface UART6 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption. For details, see 15.4.1 Operation stop mode. (2) Asynchronous serial interface (UART) mode This mode supports the LIN (Local Interconnect Network)-bus. The functions of this mode are outlined below. For details, see 15.4.2 generator. * Maximum transfer rate: 625 kbps * Two-pin configuration TXD6: Transmit data output pin RXD6: Receive data input pin * Data length of communication data can be selected from 7 or 8 bits. * Dedicated internal 8-bit baud rate generator allowing any baud rate to be set * Transmission and reception can be performed independently (full duplex operation). * MSB- or LSB-first communication selectable * Inverted transmission operation * Sync break field transmission from 13 to 20 bits * More than 11 bits can be identified for sync break field reception (SBF reception flag provided). Cautions 1. The TXD6 output inversion function inverts only the transmission side and not the reception side. To use this function, the reception side must be ready for reception of inverted data. 2. If clock supply to serial interface UART6 is not stopped (e.g., in the HALT mode), normal operation continues. If clock supply to serial interface UART6 is stopped (e.g., in the STOP mode), each register stops operating, and holds the value immediately before clock supply was stopped. The TXD6 pin also holds the value immediately before clock supply was stopped and outputs it. However, the operation is not guaranteed after clock supply is resumed. Therefore, reset the circuit so that POWER6 = 0, RXE6 = 0, and TXE6 = 0. 3. Set POWER6 = 1 and then set TXE6 = 1 (transmission) or RXE6 = 1 (reception) to start communication. 4. TXE6 and RXE6 are synchronized by the base clock (fXCLK6) set by CKSR6. To enable transmission or reception again, set TXE6 or RXE6 to 1 at least two clocks of the base clock after TXE6 or RXE6 has been cleared to 0. If TXE6 or RXE6 is set within two clocks of the base clock, the transmission circuit or reception circuit may not be initialized. 5. Set transmit data to TXB6 at least one base clock (fXCLK6) after setting TXE6 = 1. 6. If data is continuously transmitted, the communication timing from the stop bit to the next start bit is extended two operating clocks of the macro. However, this does not affect the result of communication because the reception side initializes the timing when it has detected a start bit. Do not use the continuous transmission function if the interface is used in LIN communication operation. Asynchronous serial interface (UART) mode and 15.4.3 Dedicated baud rate User's Manual U17397EJ4V0UD 345 CHAPTER 15 SERIAL INTERFACE UART6 www..com Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. LIN communication is single-master communication, and up to 15 slaves can be connected to one master. The LIN slaves are used to control the switches, actuators, and sensors, and these are connected to the LIN master via the LIN network. Normally, the LIN master is connected to a network such as CAN (Controller Area Network). In addition, the LIN bus uses a single-wire method and is connected to the nodes via a transceiver that complies with ISO9141. In the LIN protocol, the master transmits a frame with baud rate information and the slave receives it and corrects the baud rate error. Therefore, communication is possible when the baud rate error in the slave is 15% or less. Figures 15-1 and 15-2 outline the transmission and reception operations of LIN. Figure 15-1. LIN Transmission Operation Wakeup signal frame Sync break field Sync field Identifier field Data field Data field Checksum field LIN Bus 13-bitNote 2 SBF transmission 55H Data Data Data Data transmission transmission transmission transmission transmission 8 bits TX6 (output) Note 1 INTST6Note 3 Notes 1. 2. The wakeup signal frame is substituted by 80H transmission in the 8-bit mode. The sync break field is output by hardware. The output width is the bit length set by bits 4 to 2 (SBL62 to SBL60) of asynchronous serial interface control register 6 (ASICL6) (see 15.4.2 (2) (h) transmission). SBF 3. Remark INTST6 is output on completion of each transmission. It is also output when SBF is transmitted. The interval between each field is controlled by software. 346 User's Manual U17397EJ4V0UD CHAPTER 15 SERIAL INTERFACE UART6 www..com Figure 15-2. LIN Reception Operation Wakeup signal frame LIN Bus 13-bit SBF reception <2> RXD6 (input) Disable Enable SF reception ID reception Data reception Data reception Data reception <5> Sync break field Sync field Identifier field Data field Data field Checksum field <3> Reception interrupt (INTSR6) <1> Edge detection (INTP0) <4> Capture timer Disable Enable Reception processing is as follows. <1> The wakeup signal is detected at the edge of the pin, and enables UART6 and sets the SBF reception mode. <2> Reception continues until the STOP bit is detected. When an SBF with low-level data of 11 bits or more has been detected, it is assumed that SBF reception has been completed correctly, and an interrupt signal is output. If an SBF with low-level data of less than 11 bits has been detected, it is assumed that an SBF reception error has occurred. The interrupt signal is not output and the SBF reception mode is restored. <3> If SBF reception has been completed correctly, an interrupt signal is output. Start 16-bit timer/event counter 00 by the SBF reception end interrupt servicing and measure the bit interval (pulse width) of the sync field (see 7.4.8 Pulse width measurement operation). Detection of errors OVE6, PE6, and FE6 is suppressed, and error detection processing of UART communication and data transfer of the shift register and RXB6 is not performed. The shift register holds the reset value FFH. <4> Calculate the baud rate error from the bit interval of the sync field, disable UART6 after SF reception, and then re-set baud rate generator control register 6 (BRGC6). <5> Distinguish the checksum field by software. Also perform processing by software to initialize UART6 after reception of the checksum field and to set the SBF reception mode again. Figure 15-3 shows the port configuration for LIN reception operation. The wakeup signal transmitted from the LIN master is received by detecting the edge of the external interrupt (INTP0). The length of the sync field transmitted from the LIN master can be measured using the external event capture operation of 16-bit timer/event counter 00, and the baud rate error can be calculated. The input source of the reception port input (RXD6) can be input to the external interrupt (INTP0) and 16-bit timer/event counter 00 by port input switch control (ISC0/ISC1), without connecting RXD6 and INTP0/TI000 externally. User's Manual U17397EJ4V0UD 347 CHAPTER 15 SERIAL INTERFACE UART6 www..com Figure 15-3. Port Configuration for LIN Reception Operation Selector P14/RxD6 RXD6 input Port mode (PM14) Output latch (P14) Selector Selector P120/INTP0/EXLVI INTP0 input Port mode (PM120) Output latch (P120) Port input switch control (ISC0) Selector P00/TI000 TI000 input Port mode (PM00) Output latch (P00) Port input switch control (ISC1) Remark ISC0, ISC1: Bits 0 and 1 of the input switch control register (ISC) (see Figure 15-11) The peripheral functions used in the LIN communication operation are shown below. 348 User's Manual U17397EJ4V0UD CHAPTER 15 SERIAL INTERFACE UART6 www..com 15.2 Configuration of Serial Interface UART6 Serial interface UART6 includes the following hardware. Table 15-1. Configuration of Serial Interface UART6 Item Registers Receive buffer register 6 (RXB6) Receive shift register 6 (RXS6) Transmit buffer register 6 (TXB6) Transmit shift register 6 (TXS6) Control registers Asynchronous serial interface operation mode register 6 (ASIM6) Asynchronous serial interface reception error status register 6 (ASIS6) Asynchronous serial interface transmission status register 6 (ASIF6) Clock selection register 6 (CKSR6) Baud rate generator control register 6 (BRGC6) Asynchronous serial interface control register 6 (ASICL6) Input switch control register (ISC) Port mode register 1 (PM1) Port register 1 (P1) Configuration User's Manual U17397EJ4V0UD 349 Selector 350 fPRS fPRS/2 fPRS/22 fPRS/23 fPRS/24 fPRS/25 fPRS/26 fPRS/27 fPRS/28 fPRS/29 fPRS/210 8-bit timer/ event counter 50 output Asynchronous serial interface operation mode register 6 (ASIM6) Figure 15-4. Block Diagram of Serial Interface UART6 TI000, INTP0Note Filter INTSR6 INTSRE6 RXD6/ P14 Reception control Receive shift register 6 (RXS6) Asynchronous serial interface control register 6 (ASICL6) Receive buffer register 6 (RXB6) Asynchronous serial interface reception error status register 6 (ASIS6) Baud rate generator Reception unit Internal bus CHAPTER 15 SERIAL INTERFACE UART6 User's Manual U17397EJ4V0UD Baud rate generator control register 6 (BRGC6) 8 Asynchronous serial Clock selection interface transmission register 6 (CKSR6) status register 6 (ASIF6) 8 Baud rate generator Asynchronous serial interface control register 6 (ASICL6) Transmit buffer register 6 (TXB6) INTST6 Transmission control Transmit shift register 6 (TXS6) TXD6/ P13 Registers Output latch (P13) Transmission unit PM13 Note Selectable with input switch control register (ISC). www..com CHAPTER 15 SERIAL INTERFACE UART6 www..com (1) Receive buffer register 6 (RXB6) This 8-bit register stores parallel data converted by receive shift register 6 (RXS6). Each time 1 byte of data has been received, new receive data is transferred to this register from RXS6. If the data length is set to 7 bits, data is transferred as follows. * In LSB-first reception, the receive data is transferred to bits 0 to 6 of RXB6 and the MSB of RXB6 is always 0. * In MSB-first reception, the receive data is transferred to bits 1 to 7 of RXB6 and the LSB of RXB6 is always 0. If an overrun error (OVE6) occurs, the receive data is not transferred to RXB6. RXB6 can be read by an 8-bit memory manipulation instruction. No data can be written to this register. Reset signal generation sets this register to FFH. (2) Receive shift register 6 (RXS6) This register converts the serial data input to the RXD6 pin into parallel data. RXS6 cannot be directly manipulated by a program. (3) Transmit buffer register 6 (TXB6) This buffer register is used to set transmit data. Transmission is started when data is written to TXB6. This register can be read or written by an 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Cautions 1. Do not write data to TXB6 when bit 1 (TXBF6) of asynchronous serial interface transmission status register 6 (ASIF6) is 1. 2. Do not refresh (write the same value to) TXB6 by software during a communication operation (when bits 7 and 6 (POWER6, TXE6) of asynchronous serial interface operation mode register 6 (ASIM6) are 1 or when bits 7 and 5 (POWER6, RXE6) of ASIM6 are 1). 3. Set transmit data to TXB6 at least one base clock (fXCLK6) after setting TXE6 = 1. (4) Transmit shift register 6 (TXS6) This register transmits the data transferred from TXB6 from the TXD6 pin as serial data. Data is transferred from TXB6 immediately after TXB6 is written for the first transmission, or immediately before INTST6 occurs after one frame was transmitted for continuous transmission. Data is transferred from TXB6 and transmitted from the TXD6 pin at the falling edge of the base clock. TXS6 cannot be directly manipulated by a program. User's Manual U17397EJ4V0UD 351 CHAPTER 15 SERIAL INTERFACE UART6 www..com 15.3 Registers Controlling Serial Interface UART6 Serial interface UART6 is controlled by the following nine registers. * Asynchronous serial interface operation mode register 6 (ASIM6) * Asynchronous serial interface reception error status register 6 (ASIS6) * Asynchronous serial interface transmission status register 6 (ASIF6) * Clock selection register 6 (CKSR6) * Baud rate generator control register 6 (BRGC6) * Asynchronous serial interface control register 6 (ASICL6) * Input switch control register (ISC) * Port mode register 1 (PM1) * Port register 1 (P1) (1) Asynchronous serial interface operation mode register 6 (ASIM6) This 8-bit register controls the serial communication operations of serial interface UART6. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 01H. Remark ASIM6 can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (POWER6, TXE6) of ASIM6 = 1 or bits 7 and 5 (POWER6, RXE6) of ASIM6 = 1). Figure 15-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (1/2) Address: FF50H After reset: 01H R/W Symbol ASIM6 <7> POWER6 <6> TXE6 <5> RXE6 4 PS61 3 PS60 2 CL6 1 SL6 0 ISRM6 POWER6 0 Note 1 Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit Note 2 . 1 Enables operation of the internal operation clock TXE6 0 1 Enables/disables transmission Disables transmission (synchronously resets the transmission circuit). Enables transmission RXE6 0 1 Enables/disables reception Disables reception (synchronously resets the reception circuit). Enables reception Notes 1. 2. The output of the TXD6 pin goes high level and the input from the RXD6 pin is fixed to the high level when POWER6 = 0 during transmission. Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset. 352 User's Manual U17397EJ4V0UD CHAPTER 15 SERIAL INTERFACE UART6 www..com Figure 15-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2) PS61 0 0 1 1 PS60 0 1 0 1 Transmission operation Does not output parity bit. Outputs 0 parity. Outputs odd parity. Outputs even parity. Reception operation Reception without parity Reception as 0 parity Note Judges as odd parity. Judges as even parity. CL6 0 1 Specifies character length of transmit/receive data Character length of data = 7 bits Character length of data = 8 bits SL6 0 1 Number of stop bits = 1 Number of stop bits = 2 Specifies number of stop bits of transmit data ISRM6 0 1 Enables/disables occurrence of reception completion interrupt in case of error "INTSRE6" occurs in case of error (at this time, INTSR6 does not occur). "INTSR6" occurs in case of error (at this time, INTSRE6 does not occur). Note If "reception as 0 parity" is selected, the parity is not judged. Therefore, bit 2 (PE6) of asynchronous serial interface reception error status register 6 (ASIS6) is not set and the error interrupt does not occur. Cautions 1. To start the transmission, set POWER6 to 1 and then set TXE6 to 1. To stop the transmission, clear TXE6 to 0, and then clear POWER6 to 0. 2. To start the reception, set POWER6 to 1 and then set RXE6 to 1. To stop the reception, clear RXE6 to 0, and then clear POWER6 to 0. 3. Set POWER6 to 1 and then set RXE6 to 1 while a high level is input to the RXD6 pin. If POWER6 is set to 1 and RXE6 is set to 1 while a low level is input, reception is started. 4. TXE6 and RXE6 are synchronized by the base clock (fXCLK6) set by CKSR6. To enable transmission or reception again, set TXE6 or RXE6 to 1 at least two clocks of the base clock after TXE6 or RXE6 has been cleared to 0. If TXE6 or RXE6 is set within two clocks of the base clock, the transmission circuit or reception circuit may not be initialized. 5. Set transmit data to TXB6 at least one base clock (fXCLK6) after setting TXE6 = 1. 6. Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits. 7. Fix the PS61 and PS60 bits to 0 when used in LIN communication operation. 8. Clear TXE6 to 0 before rewriting the SL6 bit. Reception is always performed with "the number of stop bits = 1", and therefore, is not affected by the set value of the SL6 bit. 9. Make sure that RXE6 = 0 when rewriting the ISRM6 bit. User's Manual U17397EJ4V0UD 353 CHAPTER 15 SERIAL INTERFACE UART6 www..com (2) Asynchronous serial interface reception error status register 6 (ASIS6) This register indicates an error status on completion of reception by serial interface UART6. It includes three error flag bits (PE6, FE6, OVE6). This register is read-only by an 8-bit memory manipulation instruction. Reset signal generation, or clearing bit 7 (POWER6) or bit 5 (RXE6) of ASIM6 to 0 clears this register to 00H. 00H is read when this register is read. If a reception error occurs, read ASIS6 and then read receive buffer register 6 (RXB6) to clear the error flag. Figure 15-6. Format of Asynchronous Serial Interface Reception Error Status Register 6 (ASIS6) Address: FF53H After reset: 00H R Symbol ASIS6 7 0 6 0 5 0 4 0 3 0 2 PE6 1 FE6 0 OVE6 PE6 0 1 Status flag indicating parity error If POWER6 = 0 or RXE6 = 0, or if ASIS6 register is read If the parity of transmit data does not match the parity bit on completion of reception FE6 0 1 Status flag indicating framing error If POWER6 = 0 or RXE6 = 0, or if ASIS6 register is read If the stop bit is not detected on completion of reception OVE6 0 1 Status flag indicating overrun error If POWER6 = 0 or RXE6 = 0, or if ASIS6 register is read If receive data is set to the RXB6 register and the next reception operation is completed before the data is read. Cautions 1. The operation of the PE6 bit differs depending on the set values of the PS61 and PS60 bits of asynchronous serial interface operation mode register 6 (ASIM6). 2. For the stop bit of the receive data, only the first stop bit is checked regardless of the number of stop bits. 3. If an overrun error occurs, the next receive data is not written to receive buffer register 6 (RXB6) but discarded. 4. If data is read from ASIS6, a wait cycle is generated. Do not read data from ASIS6 when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 34 CAUTIONS FOR WAIT. 354 User's Manual U17397EJ4V0UD CHAPTER 15 SERIAL INTERFACE UART6 www..com (3) Asynchronous serial interface transmission status register 6 (ASIF6) This register indicates the status of transmission by serial interface UART6. It includes two status flag bits (TXBF6 and TXSF6). Transmission can be continued without disruption even during an interrupt period, by writing the next data to the TXB6 register after data has been transferred from the TXB6 register to the TXS6 register. This register is read-only by an 8-bit memory manipulation instruction. Reset signal generation, or clearing bit 7 (POWER6) or bit 6 (TXE6) of ASIM6 to 0 clears this register to 00H. Figure 15-7. Format of Asynchronous Serial Interface Transmission Status Register 6 (ASIF6) Address: FF55H After reset: 00H R Symbol ASIF6 7 0 6 0 5 0 4 0 3 0 2 0 1 TXBF6 0 TXSF6 TXBF6 0 1 Transmit buffer data flag If POWER6 = 0 or TXE6 = 0, or if data is transferred to transmit shift register 6 (TXS6) If data is written to transmit buffer register 6 (TXB6) (if data exists in TXB6) TXSF6 0 Transmit shift register data flag If POWER6 = 0 or TXE6 = 0, or if the next data is not transferred from transmit buffer register 6 (TXB6) after completion of transfer 1 If data is transferred from transmit buffer register 6 (TXB6) (if data transmission is in progress) Cautions 1. To transmit data continuously, write the first transmit data (first byte) to the TXB6 register. Be sure to check that the TXBF6 flag is "0". If so, write the next transmit data (second byte) to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is "1", the transmit data cannot be guaranteed. 2. To initialize the transmission unit upon completion of continuous transmission, be sure to check that the TXSF6 flag is "0" after generation of the transmission completion interrupt, and then execute initialization. If initialization is executed while the TXSF6 flag is "1", the transmit data cannot be guaranteed. User's Manual U17397EJ4V0UD 355 CHAPTER 15 SERIAL INTERFACE UART6 www..com (4) Clock selection register 6 (CKSR6) This register selects the base clock of serial interface UART6. CKSR6 can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (POWER6, TXE6) of ASIM6 = 1 or bits 7 and 5 (POWER6, RXE6) of ASIM6 = 1). Figure 15-8. Format of Clock Selection Register 6 (CKSR6) Address: FF56H After reset: 00H R/W Symbol CKSR6 7 0 6 0 5 0 4 0 3 TPS63 2 TPS62 1 TPS61 0 TPS60 TPS63 TPS62 TPS61 TPS60 Base clock (fXCLK6) selection fPRS = 2 MHz fPRS = 5 MHz 5 MHz 2.5 MHz 1.25 MHz 625 kHz fPRS = 10 MHz 10 MHz 5 MHz 2.5 MHz 1.25 MHz fPRS = 20 MHz 20 MHz 10 MHz 5 MHz 2.5 MHz 1.25 MHz 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 fPRS fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 2 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 3 4 312.5 kHz 625 kHz 5 156.25 kHz 312.5 kHz 625 kHz 6 31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz 15.625 kHz 39.06 kHz 78.13 kHz 156.25 kHz 7.813 kHz 19.53 kHz 39.06 kHz 78.13 kHz 3.906 kHz 9.77 kHz 1.953 kHz 4.88 kHz Note 7 8 9 19.53 kHz 39.06 kHz 9.77 kHz 19.53 kHz 10 TM50 output Other than above Setting prohibited Note Note the following points when selecting the TM50 output as the base clock. * Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0) Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion operation (TMC501 = 1). * PWM mode (TMC506 = 1) Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty = 50%. It is not necessary to enable the TO50 pin as a timer output pin in any mode. Caution Make sure POWER6 = 0 when rewriting TPS63 to TPS60. Remarks 1. fPRS: Peripheral hardware clock frequency 2. TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50) TMC501: Bit 1 of TMC50 356 User's Manual U17397EJ4V0UD CHAPTER 15 SERIAL INTERFACE UART6 www..com (5) Baud rate generator control register 6 (BRGC6) This register sets the division value of the 8-bit counter of serial interface UART6. BRGC6 can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (POWER6, TXE6) of ASIM6 = 1 or bits 7 and 5 (POWER6, RXE6) of ASIM6 = 1). Figure 15-9. Format of Baud Rate Generator Control Register 6 (BRGC6) Address: FF57H After reset: FFH R/W Symbol BRGC6 7 MDL67 6 MDL66 5 MDL65 4 MDL64 3 MDL63 2 MDL62 1 MDL61 0 MDL60 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 x 0 0 1 * * * * * 0 0 1 1 MDL60 x 0 1 0 * * * * * 0 1 0 1 k x 4 5 6 * * * * * 252 253 254 255 Output clock selection of 8-bit counter 0 0 0 0 * * * * * 1 1 1 1 0 0 0 0 * * * * * 1 1 1 1 0 0 0 0 * * * * * 1 1 1 1 0 0 0 0 * * * * * 1 1 1 1 0 0 0 0 * * * * * 1 1 1 1 0 1 1 1 * * * * * 1 1 1 1 Setting prohibited fXCLK6/4 fXCLK6/5 fXCLK6/6 * * * * * fXCLK6/252 fXCLK6/253 fXCLK6/254 fXCLK6/255 Cautions 1. Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when rewriting the MDL67 to MDL60 bits. 2. The baud rate is the output clock of the 8-bit counter divided by 2. Remarks 1. fXCLK6: Frequency of base clock selected by the TPS63 to TPS60 bits of CKSR6 register 2. k: Value set by MDL67 to MDL60 bits (k = 4, 5, 6, ..., 255) 3. x: Don't care User's Manual U17397EJ4V0UD 357 CHAPTER 15 SERIAL INTERFACE UART6 www..com (6) Asynchronous serial interface control register 6 (ASICL6) This register controls the serial communication operations of serial interface UART6. ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 16H. Caution ASICL6 can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (POWER6, TXE6) of ASIM6 = 1 or bits 7 and 5 (POWER6, RXE6) of ASIM6 = 1). However, do not set both SBRT6 and SBTT6 to 1 by a refresh operation during SBF reception (SBRT6 = 1) or SBF transmission (until INTST6 occurs since SBTT6 has been set (1)), because it may re-trigger SBF reception or SBF transmission. Figure 15-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (1/2) Address: FF58H After reset: 16H R/W Symbol ASICL6 <7> SBRF6 <6> SBRT6 Note 5 SBTT6 4 SBL62 3 SBL61 2 SBL60 1 DIR6 0 TXDLV6 SBRF6 0 1 SBF reception status flag If POWER6 = 0 and RXE6 = 0 or if SBF reception has been completed correctly SBF reception in progress SBRT6 0 1 SBF reception trigger SBF reception trigger - SBTT6 0 1 SBF transmission trigger SBF transmission trigger - Note Bit 7 is read-only. 358 User's Manual U17397EJ4V0UD CHAPTER 15 SERIAL INTERFACE UART6 www..com Figure 15-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (2/2) SBL62 1 1 1 0 0 0 0 1 SBL61 0 1 1 0 0 1 1 0 SBL60 1 0 1 0 1 0 1 0 SBF transmission output width control SBF is output with 13-bit length. SBF is output with 14-bit length. SBF is output with 15-bit length. SBF is output with 16-bit length. SBF is output with 17-bit length. SBF is output with 18-bit length. SBF is output with 19-bit length. SBF is output with 20-bit length. DIR6 0 1 MSB LSB First-bit specification TXDLV6 0 1 Normal output of TXD6 Inverted output of TXD6 Enables/disables inverting TXD6 output Cautions 1. In the case of an SBF reception error, the mode returns to the SBF reception mode. The status of the SBRF6 flag is held (1). 2. Before setting the SBRT6 bit, make sure that bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1. After setting the SBRT6 bit to 1, do not clear it to 0 before SBF reception is completed (before an interrupt request signal is generated). 3. The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to 0 after SBF reception has been correctly completed. 4. Before setting the SBTT6 bit to 1, make sure that bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1. After setting the SBTT6 bit to 1, do not clear it to 0 before SBF transmission is completed (before an interrupt request signal is generated). 5. The read value of the SBTT6 bit is always 0. SBTT6 is automatically cleared to 0 at the end of SBF transmission. 6. Do not set the SBRT6 bit to 1 during reception, and do not set the SBTT6 bit to 1 during transmission. 7. Before rewriting the DIR6 and TXDLV6 bits, clear the TXE6 and RXE6 bits to 0. User's Manual U17397EJ4V0UD 359 CHAPTER 15 SERIAL INTERFACE UART6 www..com (7) Input switch control register (ISC) The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN (Local Interconnect Network) reception. The signal input from the P14/RXD6 pin is selected as the input source of INTP0 and TI000 when ISC0 and ISC1 are set to 1. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 15-11. Format of Input Switch Control Register (ISC) Address: FF4FH Symbol ISC After reset: 00H 7 0 6 0 R/W 5 0 4 0 3 0 2 0 1 ISC1 0 ISC0 ISC1 0 1 TI000 (P00) RXD6 (P14) TI000 input source selection ISC0 0 1 INTP0 (P120) RXD6 (P14) INTP0 input source selection (8) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using the P13/TXD6 pin for serial interface data output, clear PM13 to 0 and set the output latch of P13 to 1. When using the P14/RXD6 pin for serial interface data input, set PM14 to 1. The output latch of P14 at this time may be 0 or 1. PM1 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Figure 15-12. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol PM1 7 PM17 After reset: FFH 6 PM16 R/W 5 PM15 4 PM14 3 PM13 2 PM12 1 PM11 0 PM10 PM1n 0 1 P1n pin I/O mode selection (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off) 360 User's Manual U17397EJ4V0UD CHAPTER 15 SERIAL INTERFACE UART6 www..com 15.4 Operation of Serial Interface UART6 Serial interface UART6 has the following two modes. * Operation stop mode * Asynchronous serial interface (UART) mode 15.4.1 Operation stop mode In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In addition, the pins can be used as ordinary port pins in this mode. To set the operation stop mode, clear bits 7, 6, and 5 (POWER6, TXE6, and RXE6) of ASIM6 to 0. (1) Register used The operation stop mode is set by asynchronous serial interface operation mode register 6 (ASIM6). ASIM6 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 01H. Address: FF50H After reset: 01H R/W Symbol ASIM6 <7> POWER6 <6> TXE6 <5> RXE6 4 PS61 3 PS60 2 CL6 1 SL6 0 ISRM6 POWER6 0 Note 1 Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit Note 2 . TXE6 0 Enables/disables transmission Disables transmission operation (synchronously resets the transmission circuit). RXE6 0 Enables/disables reception Disables reception (synchronously resets the reception circuit). Notes 1. 2. The output of the TXD6 pin goes high and the input from the RXD6 pin is fixed to high level when POWER6 = 0 during transmission. Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset. Caution Clear POWER6 to 0 after clearing TXE6 and RXE6 to 0 to stop the operation. To start the communication, set POWER6 to 1, and then set TXE6 or RXE6 to 1. Remark To use the RXD6/P14 and TXD6/P13 pins as general-purpose port pins, see CHAPTER 5 FUNCTIONS. PORT User's Manual U17397EJ4V0UD 361 CHAPTER 15 SERIAL INTERFACE UART6 www..com 15.4.2 Asynchronous serial interface (UART) mode In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) Registers used * Asynchronous serial interface operation mode register 6 (ASIM6) * Asynchronous serial interface reception error status register 6 (ASIS6) * Asynchronous serial interface transmission status register 6 (ASIF6) * Clock selection register 6 (CKSR6) * Baud rate generator control register 6 (BRGC6) * Asynchronous serial interface control register 6 (ASICL6) * Input switch control register (ISC) * Port mode register 1 (PM1) * Port register 1 (P1) The basic procedure of setting an operation in the UART mode is as follows. <1> Set the CKSR6 register (see Figure 15-8). <2> Set the BRGC6 register (see Figure 15-9). <3> Set bits 0 to 4 (ISRM6, SL6, CL6, PS60, PS61) of the ASIM6 register (see Figure 15-5). <4> Set bits 0 and 1 (TXDLV6, DIR6) of the ASICL6 register (see Figure 15-10). <5> Set bit 7 (POWER6) of the ASIM6 register to 1. <6> Set bit 6 (TXE6) of the ASIM6 register to 1. Transmission is enabled. Set bit 5 (RXE6) of the ASIM6 register to 1. Reception is enabled. <7> Write data to transmit buffer register 6 (TXB6). Data transmission is started. Caution Take relationship with the other party of communication when setting the port mode register and port register. The relationship between the register settings and pins is shown below. Table 15-2. Relationship Between Register Settings and Pins POWER6 TXE6 RXE6 PM13 x Note Note P13 x x Note Note PM14 x x Note P14 x x Note UART6 Operation Stop Reception Transmission Transmission/ reception Pin Function TXD6/P13 P13 P13 TXD6 TXD6 RXD6/P14 P14 RXD6 P14 RXD6 0 1 0 0 1 1 0 1 0 1 x 1 Note x Note 0 0 1 1 1 x Note Can be set as port function. Remark x: TXE6: RXE6: PM1x: P1x: don't care Bit 6 of ASIM6 Bit 5 of ASIM6 Port mode register Port output latch User's Manual U17397EJ4V0UD POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6) 362 CHAPTER 15 SERIAL INTERFACE UART6 www..com (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 15-13 and 15-14 show the format and waveform example of the normal transmit/receive data. Figure 15-13. Format of Normal UART Transmit/Receive Data 1. LSB-first transmission/reception 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bit Character bits 2. MSB-first transmission/reception 1 data frame Start bit D7 D6 D5 D4 D3 D2 D1 D0 Parity bit Stop bit Character bits One data frame consists of the following bits. * Start bit ... 1 bit * Character bits ... 7 or 8 bits * Parity bit ... Even parity, odd parity, 0 parity, or no parity * Stop bit ... 1 or 2 bits The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface operation mode register 6 (ASIM6). Whether data is communicated with the LSB or MSB first is specified by bit 1 (DIR6) of asynchronous serial interface control register 6 (ASICL6). Whether the TXD6 pin outputs normal or inverted data is specified by bit 0 (TXDLV6) of ASICL6. User's Manual U17397EJ4V0UD 363 CHAPTER 15 SERIAL INTERFACE UART6 www..com Figure 15-14. Example of Normal UART Transmit/Receive Data Waveform 1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop 2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 3. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H, TXD6 pin inverted output 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 4. Data length: 7 bits, LSB first, Parity: Odd parity, Stop bit: 2 bits, Communication data: 36H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 Parity Stop Stop 5. Data length: 8 bits, LSB first, Parity: None, Stop bit: 1 bit, Communication data: 87H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 D7 Stop 364 User's Manual U17397EJ4V0UD CHAPTER 15 SERIAL INTERFACE UART6 www..com (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected. With zero parity and no parity, an error cannot be detected. Caution Fix the PS61 and PS60 bits to 0 when the device is used in LIN communication operation. (i) Even parity * Transmission Transmit data, including the parity bit, is controlled so that the number of bits that are "1" is even. The value of the parity bit is as follows. If transmit data has an odd number of bits that are "1": 1 If transmit data has an even number of bits that are "1": 0 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is odd, a parity error occurs. (ii) Odd parity * Transmission Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are "1" is odd. If transmit data has an odd number of bits that are "1": 0 If transmit data has an even number of bits that are "1": 1 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is even, a parity error occurs. (iii) 0 parity The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. The parity bit is not detected when the data is received. Therefore, a parity error does not occur regardless of whether the parity bit is "0" or "1". (iv) No parity No parity bit is appended to the transmit data. Reception is performed assuming that there is no parity bit when data is received. Because there is no parity bit, a parity error does not occur. User's Manual U17397EJ4V0UD 365 CHAPTER 15 SERIAL INTERFACE UART6 www..com (c) Normal transmission When bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and bit 6 (TXE6) of ASIM6 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit buffer register 6 (TXB6). The start bit, parity bit, and stop bit are automatically appended to the data. When transmission is started, the data in TXB6 is transferred to transmit shift register 6 (TXS6). After that, the transmit data is sequentially output from TXS6 to the TXD6 pin. When transmission is completed, the parity and stop bits set by ASIM6 are appended and a transmission completion interrupt request (INTST6) is generated. Transmission is stopped until the data to be transmitted next is written to TXB6. Figure 15-15 shows the timing of the transmission completion interrupt request (INTST6). This interrupt occurs as soon as the last stop bit has been output. Figure 15-15. Normal Transmission Completion Interrupt Request Timing 1. Stop bit length: 1 TXD6 (output) Start D0 D1 D2 D6 D7 Parity Stop INTST6 2. Stop bit length: 2 TXD6 (output) Start D0 D1 D2 D6 D7 Parity Stop INTST6 366 User's Manual U17397EJ4V0UD CHAPTER 15 SERIAL INTERFACE UART6 www..com (d) Continuous transmission The next transmit data can be written to transmit buffer register 6 (TXB6) as soon as transmit shift register 6 (TXS6) has started its shift operation. Consequently, even while the INTST6 interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized. In addition, the TXB6 register can be efficiently written twice (2 bytes) without having to wait for the transmission time of one data frame, by reading bit 0 (TXSF6) of asynchronous serial interface transmission status register 6 (ASIF6) when the transmission completion interrupt has occurred. To transmit data continuously, be sure to reference the ASIF6 register to check the transmission status and whether the TXB6 register can be written, and then write the data. Cautions 1. The TXBF6 and TXSF6 flags of the ASIF6 register change from "10" to "11", and to "01" during continuous transmission. To check the status, therefore, do not use a combination of the TXBF6 and TXSF6 flags for judgment. Read only the TXBF6 flag when executing continuous transmission. 2. When the device is use in LIN communication operation, the continuous transmission function cannot be used. Make sure that asynchronous serial interface transmission status register 6 (ASIF6) is 00H before writing transmit data to transmit buffer register 6 (TXB6). TXBF6 0 1 Writing enabled Writing disabled Writing to TXB6 Register Caution To transmit data continuously, write the first transmit data (first byte) to the TXB6 register. Be sure to check that the TXBF6 flag is "0". If so, write the next transmit data (second byte) to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is "1", the transmit data cannot be guaranteed. The communication status can be checked using the TXSF6 flag. TXSF6 0 1 Transmission is completed. Transmission is in progress. Transmission Status Cautions 1. To initialize the transmission unit upon completion of continuous transmission, be sure to check that the TXSF6 flag is "0" after generation of the transmission completion interrupt, and then execute initialization. If initialization is executed while the TXSF6 flag is "1", the transmit data cannot be guaranteed. 2. During continuous transmission, the next transmission may complete before execution of INTST6 interrupt servicing after transmission of one data frame. the number of transmit data and by referencing the TXSF6 flag. As a countermeasure, detection can be performed by developing a program that can count User's Manual U17397EJ4V0UD 367 CHAPTER 15 SERIAL INTERFACE UART6 www..com Figure 15-16 shows an example of the continuous transmission processing flow. Figure 15-16. Example of Continuous Transmission Processing Flow Set registers. Write TXB6. Transfer executed necessary number of times? No Yes Read ASIF6 TXBF6 = 0? Yes No Write TXB6. Transmission completion interrupt occurs? Yes No Transfer executed necessary number of times? No Yes Read ASIF6 TXSF6 = 0? Yes Yes Completion of transmission processing No Remark TXB6: Transmit buffer register 6 ASIF6: Asynchronous serial interface transmission status register 6 TXBF6: Bit 1 of ASIF6 (transmit buffer data flag) TXSF6: Bit 0 of ASIF6 (transmit shift register data flag) 368 User's Manual U17397EJ4V0UD CHAPTER 15 SERIAL INTERFACE UART6 www..com Figure 15-17 shows the timing of starting continuous transmission, and Figure 15-18 shows the timing of ending continuous transmission. Figure 15-17. Timing of Starting Continuous Transmission TXD6 INTST6 Start Data (1) Parity Stop Start Data (2) Parity Stop Start TXB6 FF Data (1) Data (2) Data (3) TXS6 TXBF6 TXSF6 FF Data (1) Data (2) Data (3) Note Note When ASIF6 is read, there is a period in which TXBF6 and TXSF6 = 1, 1. Therefore, judge whether writing is enabled using only the TXBF6 bit. Remark TXD6: TXB6: TXS6: ASIF6: TXD6 pin (output) Transmit buffer register 6 Transmit shift register 6 Asynchronous serial interface transmission status register 6 INTST6: Interrupt request signal TXBF6: Bit 1 of ASIF6 TXSF6: Bit 0 of ASIF6 User's Manual U17397EJ4V0UD 369 CHAPTER 15 SERIAL INTERFACE UART6 www..com Figure 15-18. Timing of Ending Continuous Transmission TXD6 INTST6 Stop Start Data (n - 1) Parity Stop Start Data (n) Parity Stop TXB6 Data (n - 1) Data (n) TXS6 Data (n - 1) Data (n) FF TXBF6 TXSF6 POWER6 or TXE6 Remark TXD6: INTST6: TXB6: TXS6: ASIF6: TXBF6: TXSF6: TXE6: TXD6 pin (output) Interrupt request signal Transmit buffer register 6 Transmit shift register 6 Asynchronous serial interface transmission status register 6 Bit 1 of ASIF6 Bit 0 of ASIF6 Bit 6 of asynchronous serial interface operation mode register (ASIM6) POWER6: Bit 7 of asynchronous serial interface operation mode register (ASIM6) 370 User's Manual U17397EJ4V0UD CHAPTER 15 SERIAL INTERFACE UART6 www..com (e) Normal reception Reception is enabled and the RXD6 pin input is sampled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. The 8-bit counter of the baud rate generator starts counting when the falling edge of the RXD6 pin input is detected. When the set value of baud rate generator control register 6 (BRGC6) has been counted, the RXD6 pin input is sampled again ( as a start bit. When the start bit is detected, reception is started, and serial data is sequentially stored in the receive shift register (RXS6) at the set baud rate. When the stop bit has been received, the reception completion interrupt (INTSR6) is generated and the data of RXS6 is written to receive buffer register 6 (RXB6). If an overrun error (OVE6) occurs, however, the receive data is not written to RXB6. Even if a parity error (PE6) occurs while reception is in progress, reception continues to the reception position of the stop bit, and a reception error interrupt (INTSR6/INTSRE6) is generated on completion of reception. Figure 15-19. Reception Completion Interrupt Request Timing in Figure 15-19). If the RXD6 pin is low level at this time, it is recognized RXD6 (input) Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop INTSR6 RXB6 Cautions 1. If a reception error occurs, read ASIS6 and then RXB6 to clear the error flag. Otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. 2. Reception is always performed with the "number of stop bits = 1". The second stop bit is ignored. 3. Be sure to read asynchronous serial interface reception error status register 6 (ASIS6) before reading RXB6. User's Manual U17397EJ4V0UD 371 CHAPTER 15 SERIAL INTERFACE UART6 www..com (f) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data reception, a reception error interrupt request (INTSR6/INTSRE6) is generated. Which error has occurred during reception can be identified by reading the contents of ASIS6 in the reception error interrupt (INTSR6/INTSRE6) servicing (see Figure 15-6). The contents of ASIS6 are cleared to 0 when ASIS6 is read. Table 15-3. Cause of Reception Error Reception Error Parity error Framing error Overrun error Cause The parity specified for transmission does not match the parity of the receive data. Stop bit is not detected. Reception of the next data is completed before data is read from receive buffer register 6 (RXB6). The reception error interrupt can be separated into reception completion interrupt (INTSR6) and error interrupt (INTSRE6) by clearing bit 0 (ISRM6) of asynchronous serial interface operation mode register 6 (ASIM6) to 0. Figure 15-20. Reception Error Interrupt 1. If ISRM6 is cleared to 0 (reception completion interrupt (INTSR6) and error interrupt (INTSRE6) are separated) (a) No error during reception INTSR6 (b) Error during reception INTSR6 INTSRE6 INTSRE6 2. If ISRM6 is set to 1 (error interrupt is included in INTSR6) (a) No error during reception (b) Error during reception INTSR6 INTSRE6 INTSR6 INTSRE6 372 User's Manual U17397EJ4V0UD CHAPTER 15 SERIAL INTERFACE UART6 www..com (g) Noise filter of receive data The RxD6 signal is sampled with the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data. Because the circuit is configured as shown in Figure 15-21, the internal processing of the reception operation is delayed by two clocks from the external signal status. Figure 15-21. Noise Filter Circuit Base clock RXD6/P14 In Q Internal signal A In Q Internal signal B Match detector LD_EN (h) SBF transmission When the device is use in LIN communication operation, the SBF (Synchronous Break Field) transmission control function is used for transmission. For the transmission operation of LIN, see Figure 15-1 Transmission Operation. When bit 7 (POWER6) of asynchronous serial interface mode register 6 (ASIM6) is set to 1, the TXD6 pin outputs high level. Next, when bit 6 (TXE6) of ASIM6 is set to 1, the transmission enabled status is entered, and SBF transmission is started by setting bit 5 (SBTT6) of asynchronous serial interface control register 6 (ASICL6) to 1. Thereafter, a low level of bits 13 to 20 (set by bits 4 to 2 (SBL62 to SBL60) of ASICL6) is output. Following the end of SBF transmission, the transmission completion interrupt request (INTST6) is generated and SBTT6 is automatically cleared. Thereafter, the normal transmission mode is restored. Transmission is suspended until the data to be transmitted next is written to transmit buffer register 6 (TXB6), or until SBTT6 is set to 1. Figure 15-22. SBF Transmission TXD6 1 2 3 4 5 6 7 8 9 10 11 12 13 Stop LIN INTST6 SBTT6 Remark TXD6: TXD6 pin (output) INTST6: Transmission completion interrupt request SBTT6: Bit 5 of asynchronous serial interface control register 6 (ASICL6) User's Manual U17397EJ4V0UD 373 CHAPTER 15 SERIAL INTERFACE UART6 www..com (i) SBF reception When the device is used in LIN communication operation, the SBF (Synchronous Break Field) reception control function is used for reception. For the reception operation of LIN, see Figure 15-2 LIN Reception Operation. Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. SBF reception is enabled when bit 6 (SBRT6) of asynchronous serial interface control register 6 (ASICL6) is set to 1. In the SBF reception enabled status, the RXD6 pin is sampled and the start bit is detected in the same manner as the normal reception enable status. When the start bit has been detected, reception is started, and serial data is sequentially stored in the receive shift register 6 (RXS6) at the set baud rate. When the stop bit is received and if the width of SBF is 11 bits or more, a reception completion interrupt request (INTSR6) is generated as normal processing. At this time, the SBRF6 and SBRT6 bits are automatically cleared, and SBF reception ends. Detection of errors, such as OVE6, PE6, and FE6 (bits 0 to 2 of asynchronous serial interface reception error status register 6 (ASIS6)) is suppressed, and error detection processing of UART communication is not performed. In addition, data transfer between receive shift register 6 (RXS6) and receive buffer register 6 (RXB6) is not performed, and the reset value of FFH is retained. If the width of SBF is 10 bits or less, an interrupt does not occur as error processing after the stop bit has been received, and the SBF reception mode is restored. In this case, the SBRF6 and SBRT6 bits are not cleared. Figure 15-23. SBF Reception 1. Normal SBF reception (stop bit is detected with a width of more than 10.5 bits) RXD6 1 2 3 4 5 6 7 8 9 10 11 SBRT6 /SBRF6 INTSR6 2. SBF reception error (stop bit is detected with a width of 10.5 bits or less) RXD6 1 2 3 4 5 6 7 8 9 10 SBRT6 /SBRF6 INTSR6 "0" Remark RXD6: RXD6 pin (input) SBRT6: Bit 6 of asynchronous serial interface control register 6 (ASICL6) SBRF6: Bit 7 of ASICL6 INTSR6: Reception completion interrupt request 374 User's Manual U17397EJ4V0UD CHAPTER 15 SERIAL INTERFACE UART6 www..com 15.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of UART6. Separate 8-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator * Base clock The clock selected by bits 3 to 0 (TPS63 to TPS60) of clock selection register 6 (CKSR6) is supplied to each module when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is 1. This clock is called the base clock and its frequency is called fXCLK6. The base clock is fixed to low level when POWER6 = 0. * Transmission counter This counter stops operation, cleared to 0, when bit 7 (POWER6) or bit 6 (TXE6) of asynchronous serial interface operation mode register 6 (ASIM6) is 0. It starts counting when POWER6 = 1 and TXE6 = 1. The counter is cleared to 0 when the first data transmitted is written to transmit buffer register 6 (TXB6). If data are continuously transmitted, the counter is cleared to 0 again when one frame of data has been completely transmitted. If there is no data to be transmitted next, the counter is not cleared to 0 and continues counting until POWER6 or TXE6 is cleared to 0. * Reception counter This counter stops operation, cleared to 0, when bit 7 (POWER6) or bit 5 (RXE6) of asynchronous serial interface operation mode register 6 (ASIM6) is 0. It starts counting when the start bit has been detected. The counter stops operation after one frame has been received, until the next start bit is detected. User's Manual U17397EJ4V0UD 375 CHAPTER 15 SERIAL INTERFACE UART6 www..com Figure 15-24. Configuration of Baud Rate Generator POWER6 fPRS fPRS/2 fPRS/22 fPRS/23 fPRS/24 fPRS/25 fPRS/26 fPRS/27 fPRS/28 fPRS/29 fPRS/210 8-bit timer/ event counter 50 output Selector fXCLK6 Baud rate generator POWER6, TXE6 (or RXE6) 8-bit counter Match detector 1/2 Baud rate CKSR6: TPS63 to TPS60 BRGC6: MDL67 to MDL60 Remark POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6) TXE6: RXE6: CKSR6: BRGC6: Bit 6 of ASIM6 Bit 5 of ASIM6 Clock selection register 6 Baud rate generator control register 6 (2) Generation of serial clock A serial clock to be generated can be specified by using clock selection register 6 (CKSR6) and baud rate generator control register 6 (BRGC6). The clock to be input to the 8-bit counter can be set by bits 3 to 0 (TPS63 to TPS60) of CKSR6 and the division value (fXCLK6/4 to fXCLK6/255) of the 8-bit counter can be set by bits 7 to 0 (MDL67 to MDL60) of BRGC6. 376 User's Manual U17397EJ4V0UD CHAPTER 15 SERIAL INTERFACE UART6 www..com 15.4.4 Calculation of baud rate (1) Baud rate calculation expression The baud rate can be calculated by the following expression. * Baud rate = fXCLK6 2xk [bps] fXCLK6: Frequency of base clock selected by TPS63 to TPS60 bits of CKSR6 register k: Value set by MDL67 to MDL60 bits of BRGC6 register (k = 4, 5, 6, ..., 255) Table 15-4. Set Value of TPS63 to TPS60 TPS63 TPS62 TPS61 TPS60 Base Clock (fXCLK6) Selection fPRS = 2 MHz 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 fPRS fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 2 3 fPRS = 5 MHz 5 MHz 2.5 MHz 1.25 MHz 625 kHz fPRS = 10 MHz 10 MHz 5 MHz 2.5 MHz 1.25 MHz fPRS = 20 MHz 20 MHz 10 MHz 5 MHz 2.5 MHz 1.25 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 4 312.5 kHz 625 kHz 5 156.25 kHz 312.5 kHz 625 kHz 6 31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz 15.625 kHz 39.06 kHz 78.13 kHz 156.25 kHz 7.813 kHz 19.53 kHz 39.06 kHz 78.13 kHz 3.906 kHz 9.77 kHz 1.953 kHz 4.88 kHz 19.53 kHz 39.06 kHz 9.77 kHz 19.53 kHz 7 8 9 10 TM50 output Setting prohibited Other than above (2) Error of baud rate The baud rate error can be calculated by the following expression. * Error (%) = Actual baud rate (baud rate with error) Desired baud rate (correct baud rate) - 1 x 100 [%] Cautions 1. Keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. Make sure that the baud rate error during reception satisfies the range shown in (4) Permissible baud rate range during reception. Example: Frequency of base clock = 10 MHz = 10,000,000 Hz Set value of MDL67 to MDL60 bits of BRGC6 register = 00100001B (k = 33) Target baud rate = 153600 bps Baud rate = 10 M / (2 x 33) = 10000000 / (2 x 33) = 151,515 [bps] Error = (151515/153600 - 1) x 100 = -1.357 [%] User's Manual U17397EJ4V0UD 377 CHAPTER 15 SERIAL INTERFACE UART6 www..com (3) Example of setting baud rate Table 15-5. Set Data of Baud Rate Generator Baud Rate [bps] 300 600 1200 2400 4800 9600 19200 24000 31250 38400 48000 76800 115200 153600 312500 625000 TPS63TPS60 fPRS = 2.0 MHz k Calculated ERR TPS63Value fPRS = 5.0 MHz k Calculated ERR TPS63Value fPRS = 10.0 MHz k Calculated ERR TPS63Value fPRS = 20.0 MHz k Calculated ERR Value [%] 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -0.79 0 0.16 -0.79 0.16 TPS60 [%] 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0 0.16 0.16 -1.36 TPS60 [%] 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0 0.16 0.16 0.16 0.94 TPS60 [%] 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0 0.16 0.16 0.16 8H 7H 6H 5H 4H 3H 2H 1H 1H 1H 0H 0H 0H - - - 13 13 13 13 13 13 13 21 4 13 21 13 9 - - - 301 601 1202 2404 4808 9615 19231 23810 31250 38462 47619 76923 7H 6H 5H 4H 3H 2H 1H 3H 4H 0H 2H 0H 1H 1H 0H 0H 65 65 65 65 65 65 65 13 5 65 13 33 11 8 8 4 301 601 1202 2404 4808 9615 19231 24038 31250 38462 48077 75758 8H 7H 6H 5H 4H 3H 2H 4H 5H 1H 3H 0H 0H 0H 1H 1H 65 65 65 65 65 65 65 13 5 65 13 65 43 33 8 4 301 601 1202 2404 4808 9615 19231 24038 31250 38462 48077 76923 116279 9H 8H 7H 6H 5H 4H 3H 5H 6H 2H 4H 1H 0H 1H 2H 2H 65 65 65 65 65 65 65 13 5 65 13 65 87 33 8 4 301 601 1202 2404 4808 9615 19231 24038 31250 38462 48077 76923 111111 -3.55 - - - - - - 113636 -1.36 156250 312500 625000 1.73 0 0 114943 -0.22 151515 -1.36 312500 625000 0 0 151515 -1.36 312500 625000 0 0 Remark TPS63 to TPS60: Bits 3 to 0 of clock selection register 6 (CKSR6) (setting of base clock (fXCLK6)) k: fPRS: ERR: Value set by MDL67 to MDL60 bits of baud rate generator control register 6 (BRGC6) (k = 4, 5, 6, ..., 255) Peripheral hardware clock frequency Baud rate error 378 User's Manual U17397EJ4V0UD CHAPTER 15 SERIAL INTERFACE UART6 www..com (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. Figure 15-25. Permissible Baud Rate Range During Reception Latch timing Data frame length of UART6 Start bit Bit 0 FL Bit 1 Bit 7 Parity bit Stop bit 1 data frame (11 x FL) Minimum permissible data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmin Maximum permissible data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmax As shown in Figure 15-25, the latch timing of the receive data is determined by the counter set by baud rate generator control register 6 (BRGC6) after the start bit has been detected. If the last data (stop bit) meets this latch timing, the data can be correctly received. Assuming that 11-bit data is received, the theoretical values can be calculated as follows. FL = (Brate)-1 Brate: Baud rate of UART6 k: FL: Set value of BRGC6 1-bit data length Margin of latch timing: 2 clocks User's Manual U17397EJ4V0UD 379 CHAPTER 15 SERIAL INTERFACE UART6 www..com Minimum permissible data frame length: FLmin = 11 x FL - k-2 2k x FL = 21k + 2 2k FL Therefore, the maximum receivable baud rate at the transmission destination is as follows. 22k BRmax = (FLmin/11)-1 = Brate 21k + 2 Similarly, the maximum permissible data frame length can be calculated as follows. 10 11 k+2 2xk 21k - 2 2xk x FLmax = 11 x FL - 21k - 2 20k x FL = FL FLmax = FL x 11 Therefore, the minimum receivable baud rate at the transmission destination is as follows. BRmin = (FLmax/11)-1 = 20k 21k - 2 Brate The permissible baud rate error between UART6 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. Table 15-6. Maximum/Minimum Permissible Baud Rate Error Division Ratio (k) 4 8 20 50 100 255 Maximum Permissible Baud Rate Error +2.33% +3.53% +4.26% +4.56% +4.66% +4.72% Minimum Permissible Baud Rate Error -2.44% -3.61% -4.31% -4.58% -4.67% -4.73% Remarks 1. The permissible error of reception depends on the number of bits in one frame, input clock frequency, and division ratio (k). The higher the input clock frequency and the higher the division ratio (k), the higher the permissible error. 2. k: Set value of BRGC6 380 User's Manual U17397EJ4V0UD CHAPTER 15 SERIAL INTERFACE UART6 www..com (5) Data frame length during continuous transmission When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. However, the result of communication is not affected because the timing is initialized on the reception side when the start bit is detected. Figure 15-26. Data Frame Length During Continuous Transmission 1 data frame Start bit of second byte Bit 7 FL Parity bit FL Stop bit FLstp Start bit FL Bit 0 FL Start bit FL Bit 0 FL Bit 1 FL Where the 1-bit data length is FL, the stop bit length is FLstp, and base clock frequency is fXCLK6, the following expression is satisfied. FLstp = FL + 2/fXCLK6 Therefore, the data frame length during continuous transmission is: Data frame length = 11 x FL + 2/fXCLK6 User's Manual U17397EJ4V0UD 381 www..com CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 16.1 Functions of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 have the following two modes. * Operation stop mode * 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial communication is not performed and can enable a reduction in the power consumption. For details, see 16.4.1 Operation stop mode. (2) 3-wire serial I/O mode (MSB/LSB-first selectable) This mode is used to communicate 8-bit data using three lines: a serial clock line (SCK1n) and two serial data lines (SI1n and SO1n). The processing time of data communication can be shortened in the 3-wire serial I/O mode because transmission and reception can be simultaneously executed. In addition, whether 8-bit data is communicated with the MSB or LSB first can be specified, so this interface can be connected to any device. The 3-wire serial I/O mode is used for connecting peripheral ICs and display controllers with a clocked serial interface. For details, see 16.4.2 3-wire serial I/O mode. Remark n = 0, 1 382 User's Manual U17397EJ4V0UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 www..com 16.2 Configuration of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 include the following hardware. Table 16-1. Configuration of Serial Interfaces CSI10 and CSI11 Item Controller Transmit controller Clock start/stop controller & clock phase controller Registers Transmit buffer register 1n (SOTB1n) Serial I/O shift register 1n (SIO1n) Control registers Serial operation mode register 1n (CSIM1n) Serial clock selection register 1n (CSIC1n) Port mode register 0 (PM0) or port mode register 1 (PM1) Port register 0 (P0) or port register 1 (P1) Configuration Remark n = 0, 1 Figure 16-1. Block Diagram of Serial Interface CSI10 Internal bus (a) 8 8 Transmit buffer register 10 (SOTB10) Output selector SO10/P12 Serial I/O shift register 10 (SIO10) SI10/P11/RXD0 Transmit data controller Output latch Output latch (P12) PM12 Transmit controller fPRS/2 fPRS/22 fPRS/23 fPRS/24 fPRS/25 fPRS/26 fPRS/27 SCK10/P10/TxD0 Selector Clock start/stop controller & clock phase controller INTCSI10 Baud rate generator Output latch (P10) PM10 Remark (a): SO10 output User's Manual U17397EJ4V0UD 383 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 www..com Figure 16-2. Block Diagram of Serial Interface CSI11 Internal bus 8 SI11/P03 Serial I/O shift register 11 (SIO11) 8 Transmit buffer register 11 (SOTB11) Output selector SO11/P02 (a) Transmit data controller Output latch Output latch (P02) SSI11 Transmit controller fPRS/2 fPRS/22 fPRS/23 fPRS/24 fPRS/25 fPRS/26 fPRS/27 SCK11/P04 PM02 Selector Clock start/stop controller & clock phase controller INTCSI11 SSI11 Baud rate generator Output latch (P04) PM04 Remark (a): SO11 output (1) Transmit buffer register 1n (SOTB1n) This register sets the transmit data. Transmission/reception is started by writing data to SOTB1n when bit 7 (CSIE1n) and bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 1. The data written to SOTB1n is converted from parallel data into serial data by serial I/O shift register 1n, and output to the serial output pin (SO1n). SOTB1n can be written or read by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Cautions 1. Do not access SOTB1n when CSOT1n = 1 (during serial communication). 2. In the slave mode, transmission/reception is started when data is written to SOTB11 with a low level input to the SSI11 pin. For details on the transmission/reception operation, see 16.4.2 (2) Communication operation. (2) Serial I/O shift register 1n (SIO1n) This is an 8-bit register that converts data from parallel data into serial data and vice versa. This register can be read by an 8-bit memory manipulation instruction. Reception is started by reading data from SIO1n if bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 0. During reception, the data is read from the serial input pin (SI1n) to SIO1n. Reset signal generation clears this register to 00H. Cautions 1. Do not access SIO1n when CSOT1n = 1 (during serial communication). 2. In the slave mode, reception is started when data is read from SIO11 with a low level input to the SSI11 pin. For details on the reception operation, see 16.4.2 (2) Communication operation. Remark n = 0, 1 384 User's Manual U17397EJ4V0UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 www..com 16.3 Registers Controlling Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 are controlled by the following four registers. * Serial operation mode register 1n (CSIM1n) * Serial clock selection register 1n (CSIC1n) * Port mode register 0 (PM0) or port mode register 1 (PM1) * Port register 0 (P0) or port register 1 (P1) (1) Serial operation mode register 1n (CSIM1n) CSIM1n is used to select the operation mode and enable or disable operation. CSIM1n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Remark n = 0, 1 Figure 16-3. Format of Serial Operation Mode Register 10 (CSIM10) Address: FF80H After reset: 00H R/W Symbol CSIM10 <7> CSIE10 6 TRMD10 Note 1 5 0 4 DIR10 3 0 2 0 1 0 0 CSOT10 CSIE10 0 1 Disables operation Enables operation Note 2 Operation control in 3-wire serial I/O mode and asynchronously resets the internal circuit Note 3 . TRMD10 0 Note 5 Note 4 Transmit/receive mode control Receive mode (transmission disabled). Transmit/receive mode 1 DIR10 0 1 Note 6 First bit specification MSB LSB CSOT10 0 1 Communication is stopped. Communication is in progress. Communication status flag Notes 1. 2. 3. 4. 5. 6. Bit 0 is a read-only bit. To use P10/SCK10/TXD0 and P12/SO10 as general-purpose ports, set CSIM10 in the default status (00H). Bit 0 (CSOT10) of CSIM10 and serial I/O shift register 10 (SIO10) are reset. Do not rewrite TRMD10 when CSOT10 = 1 (during serial communication). The SO10 output (see (a) in Figure 16-1) is fixed to the low level when TRMD10 is 0. Reception is started when data is read from SIO10. Do not rewrite DIR10 when CSOT10 = 1 (during serial communication). Caution Be sure to clear bit 5 to 0. User's Manual U17397EJ4V0UD 385 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 www..com Figure 16-4. Format of Serial Operation Mode Register 11 (CSIM11) Address: FF88H After reset: 00H R/W Symbol CSIM11 <7> CSIE11 6 TRMD11 Note 1 5 SSE11 4 DIR11 3 0 2 0 1 0 0 CSOT11 CSIE11 0 1 Disables operation Enables operation Note 2 Operation control in 3-wire serial I/O mode and asynchronously resets the internal circuit Note 3 . TRMD11 0 Note 5 Note 4 Transmit/receive mode control Receive mode (transmission disabled). Transmit/receive mode 1 SSE11 0 1 Notes 6, 7 SSI11 pin use selection SSI11 pin is not used SSI11 pin is used DIR11 0 1 Note 8 First bit specification MSB LSB CSOT11 0 1 Communication is stopped. Communication is in progress. Communication status flag Notes 1. 2. 3. 4. 5. 6. 7. 8. Bit 0 is a read-only bit. To use P02/SO11, P04/SCK11, and P05/SSI11/TI001 as general-purpose ports, set CSIM11 in the default status (00H). Bit 0 (CSOT11) of CSIM11 and serial I/O shift register 11 (SIO11) are reset. Do not rewrite TRMD11 when CSOT11 = 1 (during serial communication). The SO11 output (see (a) in Figure 16-2) is fixed to the low level when TRMD11 is 0. Reception is started when data is read from SIO11. Do not rewrite SSE11 when CSOT11 = 1 (during serial communication). Before setting this bit to 1, fix the SSI11 pin input level to 0 or 1. Do not rewrite DIR11 when CSOT11 = 1 (during serial communication). 386 User's Manual U17397EJ4V0UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 www..com (2) Serial clock selection register 1n (CSIC1n) This register specifies the timing of the data transmission/reception and sets the serial clock. CSIC1n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Remark n = 0, 1 Figure 16-5. Format of Serial Clock Selection Register 10 (CSIC10) Address: FF81H After reset: 00H R/W Symbol CSIC10 7 0 6 0 5 0 4 CKP10 3 DAP10 2 CKS102 1 CKS101 0 CKS100 CKP10 0 DAP10 0 Specification of data transmission/reception timing Type 1 SCK10 SO10 SI10 input timing D7 D6 D5 D4 D3 D2 D1 D0 0 1 SCK10 SO10 SI10 input timing D7 D6 D5 D4 D3 D2 D1 D0 2 1 0 SCK10 SO10 SI10 input timing D7 D6 D5 D4 D3 D2 D1 D0 3 1 1 SCK10 SO10 SI10 input timing D7 D6 D5 D4 D3 D2 D1 D0 4 CKS102 CKS101 CKS100 CSI10 serial clock selection fPRS = 2 MHz fPRS = 5 MHz 2.5 MHz 1.25 MHz 625 kHz 312.5 kHz fPRS = 10 MHz 5 MHz 2.5 MHz 1.25 MHz 625 kHz fPRS = 20 MHz 10 MHz 5 MHz 2.5 MHz 1.25 MHz 625 kHz Mode 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 2 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz Master mode 3 4 5 156.25 kHz 312.5 kHz 6 31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz 156.25 kHz Slave mode 7 15.63 kHz 39.06 kHz 78.13 kHz External clock input to SCK10 Cautions 1. Do not write to CSIC10 while CSIE10 = 1 (operation enabled). 2. To use P10/SCK10/TXD0 and P12/SO10 as general-purpose ports, set CSIC10 in the default status (00H). 3. The phase type of the data clock is type 1 after reset. Remark fPRS: Peripheral hardware clock frequency User's Manual U17397EJ4V0UD 387 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 www..com Figure 16-6. Format of Serial Clock Selection Register 11 (CSIC11) Address: FF89H After reset: 00H R/W Symbol CSIC11 7 0 6 0 5 0 4 CKP11 3 DAP11 2 CKS112 1 CKS111 0 CKS110 CKP11 0 DAP11 0 Specification of data transmission/reception timing SCK11 SO11 SI11 input timing D7 D6 D5 D4 D3 D2 D1 D0 Type 1 0 1 SCK11 SO11 SI11 input timing D7 D6 D5 D4 D3 D2 D1 D0 2 1 0 SCK11 SO11 SI11 input timing D7 D6 D5 D4 D3 D2 D1 D0 3 1 1 SCK11 SO11 SI11 input timing D7 D6 D5 D4 D3 D2 D1 D0 4 CKS112 CKS111 CKS110 CSI11 serial clock selection fPRS = 2 MHz fPRS = 5 MHz 2.5 MHz 1.25 MHz 625 kHz 312.5 kHz fPRS = 10 MHz 5 MHz 2.5 MHz 1.25 MHz 625 kHz fPRS = 20 MHz 10 MHz 5 MHz 2.5 MHz 1.25 MHz 625 kHz Mode 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 2 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz Master mode 3 4 5 156.25 kHz 312.5 kHz 6 31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz 156.25 kHz Slave mode 7 15.63 kHz 39.06 kHz 78.13 kHz External clock input to SCK11 Cautions 1. Do not write to CSIC11 while CSIE11 = 1 (operation enabled). 2. To use P02/SO11 and P04/SCK11 as general-purpose ports, set CSIC11 in the default status (00H). 3. The phase type of the data clock is type 1 after reset. Remark fPRS: Peripheral hardware clock frequency 388 User's Manual U17397EJ4V0UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 www..com (3) Port mode registers 0 and 1 (PM0, PM1) These registers set port 0 and 1 input/output in 1-bit units. When using P10/SCK10 and P04/SCK11 as the clock output pins of the serial interface, clear PM10 and PM04 to 0, and set the output latches of P10 and P04 to 1. When using P12/SO10 and P02/SO11 as the data output pins of the serial interface, clear PM12, PM02, and the output latches of P12 and P02 to 0. When using P10/SCK10 and P04/SCK11 as the clock input pins of the serial interface, P11/SI10/RXD0 and P03/SI11 as the data input pins, and P05/SSI11/TI001 as the chip select input pin, set PM10, PM04, PM11, PM03, and PM05 to 1. At this time, the output latches of P10, P04, P11, P03, and P05 may be 0 or 1. PM0 and PM1 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Figure 16-7. Format of Port Mode Register 0 (PM0) Address: FF20H Symbol PM0 7 1 6 After reset: FFH 5 4 R/W 3 2 1 0 PM06 PM05 PM04 PM03 PM02 PM01 PM00 PM0n 0 1 P0n pin I/O mode selection (n = 0 to 6) Output mode (output buffer on) Input mode (output buffer off) Figure 16-8. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol 7 6 After reset: FFH 5 4 R/W 3 2 1 0 PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM1n 0 1 P1n pin I/O mode selection (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off) User's Manual U17397EJ4V0UD 389 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 www..com 16.4 Operation of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 can be used in the following two modes. * Operation stop mode * 3-wire serial I/O mode 16.4.1 Operation stop mode Serial communication is not executed in this mode. Therefore, the power consumption can be reduced. In addition, the P10/SCK10/TXD0, P11/SI10/RXD0, P12/SO10, P02/SO11, P03/SI11, and P04/SCK11 pins can be used as ordinary I/O port pins in this mode. (1) Register used The operation stop mode is set by serial operation mode register 1n (CSIM1n). To set the operation stop mode, clear bit 7 (CSIE1n) of CSIM1n to 0. (a) Serial operation mode register 1n (CSIM1n) CSIM1n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears CSIM1n to 00H. Remark n = 0, 1 * Serial operation mode register 10 (CSIM10) Address: FF80H After reset: 00H R/W Symbol CSIM10 <7> CSIE10 6 TRMD10 5 0 4 DIR10 3 0 2 0 1 0 0 CSOT10 CSIE10 0 Disables operation Note 1 Operation control in 3-wire serial I/O mode and asynchronously resets the internal circuit Note 2 . Notes 1. 2. To use P10/SCK10/TXD0 and P12/SO10 as general-purpose ports, set CSIM10 in the default status (00H). Bit 0 (CSOT10) of CSIM10 and serial I/O shift register 10 (SIO10) are reset. * Serial operation mode register 11 (CSIM11) Address: FF88H After reset: 00H R/W Symbol CSIM11 <7> CSIE11 6 TRMD11 5 SSE11 4 DIR11 3 0 2 0 1 0 0 CSOT11 CSIE11 0 Disables operation Note 1 Operation control in 3-wire serial I/O mode and asynchronously resets the internal circuit Note 2 . Notes 1. 2. To use P02/SO11, P04/SCK11, and P05/SSI11/TI001 as general-purpose ports, set CSIM11 in the default status (00H). Bit 0 (CSOT11) of CSIM11 and serial I/O shift register 11 (SIO11) are reset. 390 User's Manual U17397EJ4V0UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 www..com 16.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is used for connecting peripheral ICs and display controllers with a clocked serial interface. In this mode, communication is executed by using three lines: the serial clock (SCK1n), serial output (SO1n), and serial input (SI1n) lines. (1) Registers used * Serial operation mode register 1n (CSIM1n) * Serial clock selection register 1n (CSIC1n) * Port mode register 0 (PM0) or port mode register 1 (PM1) * Port register 0 (P0) or port register 1 (P1) The basic procedure of setting an operation in the 3-wire serial I/O mode is as follows. <1> Set the CSIC1n register (see Figures 16-5 and 16-6). <2> Set bits 4 to 6 (DIR1n, SSE11 (serial interface CSI11 only), and TRMD1n) of the CSIM1n register (see Figures 16-3 and 16-4). <3> Set bit 7 (CSIE1n) of the CSIM1n register to 1. Transmission/reception is enabled. <4> Write data to transmit buffer register 1n (SOTB1n). Data transmission/reception is started. Read data from serial I/O shift register 1n (SIO1n). Data reception is started. Caution Take relationship with the other party of communication when setting the port mode register and port register. Remark n = 0, 1 User's Manual U17397EJ4V0UD 391 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 www..com The relationship between the register settings and pins is shown below. Table 16-2. Relationship Between Register Settings and Pins (1/2) (a) Serial interface CSI10 CSIE10 TRMD10 PM11 P11 PM12 P12 PM10 P10 CSI10 Operation Pin Function SI10/RXD0/ SO10/P12 P11 0 x x Note 1 SCK10/ TXD0/P10 x Note 1 x Note 1 x x Note 1 x Note 1 x Note 1 Stop RXD0/P11 P12 TXD0/ P10 Note 2 1 0 x 1 Note 1 x x Note 1 x Note 1 Note 1 1 x x x Slave reception Note 3 SI10 P12 SCK10 (input) Note 3 1 1 0 0 1 Slave transmission Note 3 RXD0/P11 SO10 SCK10 (input) Note 3 1 1 1 x 0 0 1 Slave transmission/ reception Note 3 SI10 SO10 SCK10 (input) Note 3 1 0 x 1 Note 1 x x Note 1 x Note 1 x Note 1 0 1 Master reception SI10 P12 SCK10 (output) 1 1 0 0 0 1 Master transmission RXD0/P11 SO10 SCK10 (output) 1 1 1 x 0 0 0 1 Master transmission/ reception SI10 SO10 SCK10 (output) Notes 1. Can be set as port function. 2. To use P10/SCK10/TXD0 as port pins, clear CKP10 to 0. 3. To use the slave mode, set CKS102, CKS101, and CKS100 to 1, 1, 1. Remark x: CSIE10: TRMD10: CKP10: PM1x: P1x: don't care Bit 7 of serial operation mode register 10 (CSIM10) Bit 6 of CSIM10 Bit 4 of serial clock selection register 10 (CSIC10) Port mode register Port output latch CKS102, CKS101, CKS100: Bits 2 to 0 of CSIC10 392 User's Manual U17397EJ4V0UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 www..com Table 16-2. Relationship Between Register Settings and Pins (2/2) (b) Serial interface CSI11 CSIE11 TRMD11 SSE11 PM03 P03 PM02 P02 PM04 P04 PM05 P05 CSI11 Operation SI11/ P03 0 x 0 x 0 x Note 1 Pin Function SO11/ P02 P02 SCK11/ P04 P04 Note 2 SSI11/ TI001/P05 TI001/ P05 x Note 1 x Note 1 x x Note 1 x Note 1 x Note 1 x x Note 1 x x Note 1 Stop P03 1 1 x x Note 1 Note 1 1 x Note 1 Note 1 Slave reception Note 3 SI11 P02 SCK11 (input) Note 3 TI001/ P05 SSI11 1 1 1 0 x Note 1 1 x Note 1 x x Note 1 0 0 1 x x Note 1 Slave transmission Note 3 P03 SO11 SCK11 (input) Note 3 TI001/ P05 SSI11 1 1 1 0 1 x 0 0 1 x x 1 Note 1 x x Note 1 Slave transmission/ reception Note 3 SI11 SO11 SCK11 (input) Note 3 TI001/ P05 SSI11 1 1 0 0 x 1 Note 1 1 x x Note 1 x x x x Note 1 x Note 1 x Note 1 0 1 x Note 1 Master reception SI11 P02 SCK11 (output) TI001/ P05 TI001/ P05 TI001/ P05 1 1 0 0 0 0 1 x x Note 1 Note 1 Master transmission P03 SO11 SCK11 (output) 1 1 0 1 x 0 0 0 1 Note 1 Note 1 Master transmission/ reception SI11 SO11 SCK11 (output) Notes 1. Can be set as port function. 2. To use P04/SCK11 as port pins, clear CKP11 to 0. 3. To use the slave mode, set CKS112, CKS111, and CKS110 to 1, 1, 1. Remark x: CSIE11: TRMD11: CKP11: PM0x: P0x: don't care Bit 7 of serial operation mode register 11 (CSIM11) Bit 6 of CSIM11 Bit 4 of serial clock selection register 11 (CSIC11) Port mode register Port output latch CKS112, CKS111, CKS110: Bits 2 to 0 of CSIC11 User's Manual U17397EJ4V0UD 393 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 www..com (2) Communication operation In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or received in synchronization with the serial clock. Data can be transmitted or received if bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 1. Transmission/reception is started when a value is written to transmit buffer register 1n (SOTB1n). In addition, data can be received when bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 0. Reception is started when data is read from serial I/O shift register 1n (SIO1n). However, communication is performed as follows if bit 5 (SSE11) of CSIM11 is 1 when serial interface CSI11 is in the slave mode. <1> Low level input to the SSI11 pin Transmission/reception is started when SOTB11 is written, or reception is started when SIO11 is read. <2> High level input to the SSI11 pin Transmission/reception or reception is held, therefore, even if SOTB11 is written or SIO11 is read, transmission/reception or reception will not be started. <3> Data is written to SOTB11 or data is read from SIO11 while a high level is input to the SSI11 pin, then a low level is input to the SSI11 pin Transmission/reception or reception is started. <4> A high level is input to the SSI11 pin during transmission/reception or reception Transmission/reception or reception is suspended. After communication has been started, bit 0 (CSOT1n) of CSIM1n is set to 1. When communication of 8-bit data has been completed, a communication completion interrupt request flag (CSIIF1n) is set, and CSOT1n is cleared to 0. Then the next communication is enabled. Cautions 1. Do not access the control register and data register when CSOT1n = 1 (during serial communication). 2. When using serial interface CSI11, wait for the duration of at least one clock before the clock operation is started to change the level of the SSI11 pin in the slave mode; otherwise, malfunctioning may occur. Remark n = 0, 1 394 User's Manual U17397EJ4V0UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 www..com Figure 16-9. Timing in 3-Wire Serial I/O Mode (1/2) (a) Transmission/reception timing (Type 1: TRMD1n = 1, DIR1n = 0, CKP1n = 0, DAP1n = 0, SSE11 = 1Note) SSI11Note SCK1n Read/write trigger SOTB1n 55H (communication data) SIO1n ABH 56H ADH 5AH B5H 6AH D5H AAH CSOT1n INTCSI1n CSIIF1n SI1n (receive AAH) SO1n 55H is written to SOTB1n. Note The SSE11 flag and SSI11 pin are available only for serial interface CSI11, and are used in the slave mode. Remark n = 0, 1 User's Manual U17397EJ4V0UD 395 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 www..com Figure 16-9. Timing in 3-Wire Serial I/O Mode (2/2) (b) Transmission/reception timing (Type 2: TRMD1n = 1, DIR1n = 0, CKP1n = 0, DAP1n = 1, SSE11 = 1Note) SSI11Note SCK1n Read/write trigger SOTB1n 55H (communication data) SIO1n ABH 56H ADH 5AH B5H 6AH D5H AAH CSOT1n INTCSI1n CSIIF1n SI1n (input AAH) SO1n 55H is written to SOTB1n. Note The SSE11 flag and SSI11 pin are available only for serial interface CSI11, and are used in the slave mode. Remark n = 0, 1 396 User's Manual U17397EJ4V0UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 www..com Figure 16-10. Timing of Clock/Data Phase (a) Type 1: CKP1n = 0, DAP1n = 0, DIR1n = 0 SCK1n SI1n capture SO1n Writing to SOTB1n or reading from SIO1n CSIIF1n CSOT1n D7 D6 D5 D4 D3 D2 D1 D0 (b) Type 2: CKP1n = 0, DAP1n = 1, DIR1n = 0 SCK1n SI1n capture SO1n Writing to SOTB1n or reading from SIO1n CSIIF1n CSOT1n D7 D6 D5 D4 D3 D2 D1 D0 (c) Type 3: CKP1n = 1, DAP1n = 0, DIR1n = 0 SCK1n SI1n capture SO1n Writing to SOTB1n or reading from SIO1n CSIIF1n CSOT1n D7 D6 D5 D4 D3 D2 D1 D0 (d) Type 4: CKP1n = 1, DAP1n = 1, DIR1n = 0 SCK1n SI1n capture SO1n Writing to SOTB1n or reading from SIO1n CSIIF1n CSOT1n D7 D6 D5 D4 D3 D2 D1 D0 Remarks 1. n = 0, 1 2. The above figure illustrates a communication operation where data is transmitted with the MSB first. User's Manual U17397EJ4V0UD 397 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 www..com (3) Timing of output to SO1n pin (first bit) When communication is started, the value of transmit buffer register 1n (SOTB1n) is output from the SO1n pin. The output operation of the first bit at this time is described below. Figure 16-11. Output Operation of First Bit (1/2) (a) Type 1: CKP1n = 0, DAP1n = 0 SCK1n Writing to SOTB1n or reading from SIO1n SOTB1n SIO1n Output latch SO1n First bit 2nd bit (b) Type 3: CKP1n = 1, DAP1n = 0 SCK1n Writing to SOTB1n or reading from SIO1n SOTB1n SIO1n Output latch SO1n First bit 2nd bit The first bit is directly latched by the SOTB1n register to the output latch at the falling (or rising) edge of SCK1n, and output from the SO1n pin via an output selector. Then, the value of the SOTB1n register is transferred to the SIO1n register at the next rising (or falling) edge of SCK1n, and shifted one bit. At the same time, the first bit of the receive data is stored in the SIO1n register via the SI1n pin. The second and subsequent bits are latched by the SIO1n register to the output latch at the next falling (or rising) edge of SCK1n, and the data is output from the SO1n pin. Remark n = 0, 1 398 User's Manual U17397EJ4V0UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 www..com Figure 16-11. Output Operation of First Bit (2/2) (c) Type 2: CKP1n = 0, DAP1n = 1 SCK1n Writing to SOTB1n or reading from SIO1n SOTB1n SIO1n Output latch SO1n First bit 2nd bit 3rd bit (d) Type 4: CKP1n = 1, DAP1n = 1 SCK1n Writing to SOTB1n or reading from SIO1n SOTB1n SIO1n Output latch SO1n First bit 2nd bit 3rd bit The first bit is directly latched by the SOTB1n register at the falling edge of the write signal of the SOTB1n register or the read signal of the SIO1n register, and output from the SO1n pin via an output selector. Then, the value of the SOTB1n register is transferred to the SIO1n register at the next falling (or rising) edge of SCK1n, and shifted one bit. At the same time, the first bit of the receive data is stored in the SIO1n register via the SI1n pin. The second and subsequent bits are latched by the SIO1n register to the output latch at the next rising (or falling) edge of SCK1n, and the data is output from the SO1n pin. Remark n = 0, 1 User's Manual U17397EJ4V0UD 399 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 www..com (4) Output value of SO1n pin (last bit) After communication has been completed, the SO1n pin holds the output value of the last bit. Figure 16-12. Output Value of SO1n Pin (Last Bit) (1/2) (a) Type 1: CKP1n = 0, DAP1n = 0 SCK1n Writing to SOTB1n or reading from SIO1n SOTB1n SIO1n Output latch SO1n Last bit ( Next request is issued.) (b) Type 3: CKP1n = 1, DAP1n = 0 SCK1n Writing to SOTB1n or reading from SIO1n SOTB1n SIO1n Output latch SO1n Last bit ( Next request is issued.) Remark n = 0, 1 400 User's Manual U17397EJ4V0UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 www..com Figure 16-12. Output Value of SO1n Pin (Last Bit) (2/2) (c) Type 2: CKP1n = 0, DAP1n = 1 SCK1n Writing to SOTB1n or reading from SIO1n SOTB1n SIO1n Output latch SO1n Last bit ( Next request is issued.) (d) Type 4: CKP1n = 1, DAP1n = 1 SCK1n Writing to SOTB1n or reading from SIO1n SOTB1n SIO1n Output latch SO1n Last bit ( Next request is issued.) Remark n = 0, 1 User's Manual U17397EJ4V0UD 401 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 www..com (5) SO1n output (see (a) in Figures 16-1 and 16-2) The status of the SO1n output is as follows if bit 7 (CSIE1n) of serial operation mode register 1n (CSIM1n) is cleared to 0. Table 16-3. SO1n Output Status TRMD1n TRMD1n = 0 TRMD1n = 1 Note 2 DAP1n - DAP1n = 0 DIR1n - - DIR1n = 0 DIR1n = 1 SO1n Output Outputs low level Note 2 Note 1 Value of SO1n latch (low-level output) DAP1n = 1 Value of bit 7 of SOTB1n Value of bit 0 of SOTB1n Notes 1. 2. The actual output of the SO10/P12 or SO11/P02 pin is determined according to PM12 and P12 or PM02 and P02, as well as the SO1n output. Status after reset Caution If a value is written to TRMD1n, DAP1n, and DIR1n, the output value of SO1n changes. Remark n = 0, 1 402 User's Manual U17397EJ4V0UD www..com CHAPTER 17 SERIAL INTERFACE CSIA0 17.1 Functions of Serial Interface CSIA0 Serial interface CSIA0 has the following three modes. (1) Operation stop mode This mode is used when serial communication is not performed and can enable a reduction in the power consumption. For details, see 17.4.1 Operation stop mode. (2) 3-wire serial I/O mode (MSB/LSB-first selectable) This mode is to communicate data successively in 8-bit units, by using three lines: serial clock (SCKA0) and serial data (SIA0 and SOA0) lines. The processing time of data communication can be shortened in the 3-wire serial I/O mode because transmission and reception can be simultaneously executed. In addition, whether 8-bit data is communicated MSB or LSB first can be specified, so this interface can be connected to any device. For details, see 17.4.2 3-wire serial I/O mode. (3) 3-wire serial I/O mode with automatic transmit/receive function (MSB/LSB-first selectable) This mode is used to communicate data continuously in 8-bit units using three lines: a serial clock line (SCKA0) and two serial data lines (SIA0 and SOA0). The processing time of data communication can be shortened in the 3-wire serial I/O mode with automatic transmit/receive function because transmission and reception can be simultaneously executed. In addition, whether 8-bit data is communicated MSB or LSB first can be specified, so this interface can be connected to any device. Data can be communicated to/from a display driver etc. without using software since a 32-byte transfer buffer RAM is incorporated. Also, the incorporation of handshake pins (STB0, BUSY0) used in the master mode has made connection to peripheral ICs easy. For details, see 17.4.3 3-wire serial I/O mode with automatic transmit/receive function. The features of serial interface CSIA0 are as follows. * Master mode/slave mode selectable * Communication data length: 8 bits * MSB/LSB-first selectable for communication data * Automatic transmit/receive function: Number of transfer bytes can be specified between 1 and 32 Transfer interval can be specified (0 to 63 clocks) Single communication/repeat communication selectable Internal 32-byte buffer RAM * On-chip dedicated baud rate generator (6/8/16/32 divisions) * 3-wire SOA0: SIA0: Serial data output Serial data input Strobe output SCKA0: Serial clock I/O * Handshake function incorporated STB0: BUSY0: Busy input * Detection of bit shift error due to BUSY0 signal * Transmission/reception completion interrupt: INTACSI User's Manual U17397EJ4V0UD 403 CHAPTER 17 SERIAL INTERFACE CSIA0 www..com 17.2 Configuration of Serial Interface CSIA0 Serial interface CSIA0 consists of the following hardware. Table 17-1. Configuration of Serial Interface CSIA0 Item Controller Registers Control registers Serial transfer controller Serial I/O shift register 0 (SIOA0) Serial operation mode specification register 0 (CSIMA0) Serial status register 0 (CSIS0) Serial trigger register 0 (CSIT0) Divisor selection register 0 (BRGCA0) Automatic data transfer address point specification register 0 (ADTP0) Automatic data transfer interval specification register 0 (ADTI0) Automatic data transfer address count register 0 (ADTC0) Port mode register 14 (PM14) Port register 14 (P14) Configuration 404 User's Manual U17397EJ4V0UD Figure 17-1. Block Diagram of Serial Interface CSIA0 Buffer RAM Automatic data transfer address point specification register 0 (ADTP0) Automatic data transfer address count register 0 (ADTC0) Internal bus ATE0 DIR0 ATM0 SIA0/P143 RXAE0 SOA0/P144 P144 TXAE0 2 STB0/P145 PM145 BUSY0/P141 P145 Serial transfer controller Serial clock counter Interrupt generator INTACSI 4 3 Serial I/O shift register 0 (SIOA0) Divisor selection register 0 (BRGCA0) Serial trigger register 0 (CSIT0) ATSTP0 ATSTA0 CHAPTER 17 SERIAL INTERFACE CSIA0 Serial status register 0 (CSIS0) STBE0 BUSYE0 BUSYLV0 ERRE0 ERRF0 TSF0 Selector User's Manual U17397EJ4V0UD PM144 SCKA0/P142 PM142 P142 Selector fW/6 to fW/32 Automatic data transfer interval specification register 0 (ADTI0) Baud rate generator fPRS fPRS/2 fW MASTER0 6-bit counter CKS000 www..com CSIAE0 ATE0 ATM0 MASTER0 TXEA0 RXEA0 DIR0 Serial operation mode specification register 0 (CSIMA0) Internal bus 405 CHAPTER 17 SERIAL INTERFACE CSIA0 www..com (1) Serial I/O shift register 0 (SIOA0) This is an 8-bit register used to store transmit/receive data in 1-byte transfer mode (bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) = 0). Writing transmit data to SIOA0 starts the communication. In addition, after a communication completion interrupt request (INTACSI) is output (bit 0 (TSF0) of serial status register 0 (CSIS0) = 0), data can be received by reading data from SIOA0. This register can be written or read by an 8-bit memory manipulation instruction. However, writing to SIOA0 is prohibited when bit 0 (TSF0) of serial status register 0 (CSIS0) = 1. Reset signal generation clears this register to 00H. Cautions 1. A communication operation is started by writing to SIOA0. Consequently, when transmission is disabled (bit 3 (TXEA0) of CSIMA0 = 0), write dummy data to the SIOA0 register to start the communication operation, and then perform a receive operation. 2. Do not write data to SIOA0 while the automatic transmit/receive function is operating. 17.3 Registers Controlling Serial Interface CSIA0 Serial interface CSIA0 is controlled by the following nine registers. * Serial operation mode specification register 0 (CSIMA0) * Serial status register 0 (CSIS0) * Serial trigger register 0 (CSIT0) * Divisor selection register 0 (BRGCA0) * Automatic data transfer address point specification register 0 (ADTP0) * Automatic data transfer interval specification register 0 (ADTI0) * Automatic data transfer address count register 0 (ADTC0) * Port mode register 14 (PM14) * Port register 14 (P14) 406 User's Manual U17397EJ4V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 www..com (1) Serial operation mode specification register 0 (CSIMA0) This is an 8-bit register used to control the serial communication operation. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 17-2. Format of Serial Operation Mode Specification Register 0 (CSIMA0) Address: FF90H Symbol CSIMA0 <> CSIAE0 CSIAE0 0 1 ATE0 ATM0 MASTER0 After reset: 00H R/W <> TXEA0 <> RXEA0 DIR0 0 Control of CSIA0 operation enable/disable CSIA0 operation disabled (SOA0: Low level, SCKA0: High level) and asynchronously resets the internal circuitNote. CSIA0 operation enabled ATE0 0 1 ATM0 0 1 MASTER0 0 1 Control of automatic communication operation enable/disable 1-byte communication mode Automatic communication mode Automatic communication mode specification Single transfer mode (stops at the address specified by the ADTP0 register) Repeat transfer mode (after transfer is complete, clear the ADTC0 register to 00H to resume transfer) CSIA0 master/slave mode specification Slave mode (synchronous with SCKA0 input clock) Master mode (synchronous with internal clock) Control of transmit operation enable/disable Transmit operation disabled (SOA0: Low level) Transmit operation enabled Control of receive operation enable/disable Receive operation disabled Receive operation enabled First bit specification MSB LSB TXEA0 0 1 RXEA0 0 1 DIR0 0 1 Note Automatic data transfer address count register 0 (ADTC0), serial trigger register 0 (CSIT0), serial I/O shift register 0 (SIOA0), and bit 0 (TSF0) of serial status register 0 (CSIS0) are reset. Cautions 1. When CSIAE0 = 0, the buffer RAM cannot be accessed. 2. When CSIAE0 is changed from 1 to 0, the registers and bits mentioned in Note above are asynchronously initialized. To set CSIAE0 = 1 again, be sure to re-set the initialized registers. 3. When CSIAE0 is re-set to 1 after CSIAE0 is changed from 1 to 0, it is not guaranteed that the value of the buffer RAM will be retained. User's Manual U17397EJ4V0UD 407 CHAPTER 17 SERIAL INTERFACE CSIA0 www..com (2) Serial status register 0 (CSIS0) This is an 8-bit register used to select the base clock, control the communication operation, and indicate the status of serial interface CSIA0. This register can be set by a 1-bit or 8-bit memory manipulation instruction. However, rewriting CSIS0 is prohibited when bit 0 (TSF0) is 1. Reset signal generation clears this register to 00H. Figure 17-3. Format of Serial Status Register 0 (CSIS0) (1/2) Address: FF91H Symbol CSIS0 After reset: 00H 7 0 CKS00 fPRS = 2 MHz 0 1 STBE0Notes 2, 3 0 1 BUSYE0 0 1 BUSYLV0Note 4 0 1 Low level High level Strobe output disabled Strobe output enabled Busy signal detection enable/disable Busy signal detection disabled (input via BUSY0 pin is ignored) Busy signal detection enabled and communication wait by busy signal is executed Busy signal active level setting fPRS fPRS/2 2 MHz 1 MHz 6 CKS00 R/WNote 1 5 STBE0 4 BUSYE0 3 BUSYLV0 2 ERRE0 1 ERRF0 0 TSF0 Base clock (fW) selection fPRS = 5 MHz 5 MHz 2.5 MHz Strobe output enable/disable fPRS = 10 MHz 10 MHz 5 MHz fPRS = 20 MHz 20 MHz 10 MHz Notes 1. 2. 3. Bits 0 and 1 are read-only. STBE0 is valid only in master mode. When STBE0 is set to 1, two transfer clocks are consumed between byte transfers regardless of the setting of automatic data transfer interval specification register 0 (ADTI0). That is, 10 transfer clocks are used for 1-byte transfer if ADTI0 = 00H is set. 4. Caution Remark In bit error detection by busy input, the active level specified by BUSYLV0 is detected. Be sure to clear bit 7 to 0. fPRS: Peripheral hardware clock frequency 408 User's Manual U17397EJ4V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 www..com Figure 17-3. Format of Serial Status Register 0 (CSIS0) (2/2) ERRE0Note 0 1 ERRF0 0 Error detection disabled Error detection enabled Bit error detection flag * Bit 7 (CSIAE0) of serial operation mode specification register 0 (CSIMA0) = 0 * At reset input * When communication is started by setting bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) to 1 or writing to SIOA0. Bit error detected (when ERRE0 = 1, the level specified by BUSYLV0 during the data bit transfer period is detected via BUSY0 pin input). Bit error detection enable/disable 1 TSF0 0 * * * * Transfer status detection flag Bit 7 (CSIAE0) of serial operation mode specification register 0 (CSIMA0) = 0 At reset input At the end of the specified transfer When transfer is stopped by setting bit 1 (ATSTP0) of serial trigger register 0 (CSIT0) to 1 1 From the transfer start to the end of the specified transfer Note The ERRE0 setting is valid even when BUSYE0 = 0. Caution During transfer (TSF0 = 1), rewriting serial operation mode specification register 0 (CSIMA0), serial status register 0 (CSIS0), divisor selection register 0 (BRGCA0), automatic data transfer address point specification register 0 (ADTP0), automatic data transfer interval specification register 0 (ADTI0), and serial I/O shift register 0 (SIOA0) are prohibited. rewritten during transfer. However, these registers can be read and re-written to the same value. In addition, the buffer RAM can be User's Manual U17397EJ4V0UD 409 CHAPTER 17 SERIAL INTERFACE CSIA0 www..com (3) Serial trigger register 0 (CSIT0) This is an 8-bit register used to control execution/stop of automatic data transfer between buffer RAM and serial I/O shift register 0 (SIOA0). This register can be set by a 1-bit or 8-bit memory manipulation instruction. This register can be set when bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) is 1. Reset signal generation clears this register to 00H. Figure 17-4. Format of Serial Trigger Register 0 (CSIT0) Address: FF92H Symbol CSIT0 After reset: 00H 7 0 ATSTP0 0 1 ATSTA0 0 1 Automatic data transfer started Automatic data transfer stopped Automatic data transfer start - 6 0 R/W 5 0 4 0 3 0 2 0 <1> ATSTP0 <0> ATSTA0 Automatic data transfer stop - Cautions 1. Even if ATSTP0 or ATSTA0 is set to 1, automatic transfer cannot be started/stopped until 1byte transfer is complete. 2. ATSTP0 and ATSTA0 change to 0 automatically after the interrupt signal INTACSI is generated. 3. After automatic data transfer is stopped, the data address when the transfer stopped is stored in automatic data transfer address count register 0 (ADTC0). However, since no function to restart automatic data transfer is incorporated, when transfer is stopped by setting ATSTP0 = 1, start automatic data transfer by setting ATSTA0 to 1 after re-setting the registers. 410 User's Manual U17397EJ4V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 www..com (4) Divisor selection register 0 (BRGCA0) This is an 8-bit register used to select the base clock divisor of CSIA0. This register can be set by an 8-bit memory manipulation instruction. However, when bit 0 (TSF0) of serial status register 0 (CSIS0) is 1, rewriting BRGCA0 is prohibited. Reset signal generation sets this register to 03H. Figure 17-5. Format of Divisor Selection Register 0 (BRGCA0) Address: FF93H Symbol BRGCA0 After reset: 03H 7 0 BRGCA01 6 0 BRGCA00 R/W 5 0 4 0 3 0 2 0 1 BRGCA01 0 BRGCA00 Selection of base clock (fW) divisor of CSIA0 fW = 1 MHz fW = 2 MHz fW = 2.5 MHz fW = 5 MHz fW = 10 MHz fW = 20 MHzNote 0 0 1 1 0 1 0 1 fW/6 fW/23 fW/24 fW/2 5 166.67 kHz 333.3 kHz 416.67 kHz 833.33 kHz 1.67 MHzNote Setting prohibited 125 kHz 62.5 kHz 250 kHz 125 kHz 312.5 kHz 625 kHz 1.25 MHzNote Setting prohibited 1.25 MHz 625 kHz 156.25 kHz 312.5 kHz 625 kHz 78.125 kHz 156.25 kHz 312.5 kHz 31.25 kHz 62.5 kHz Note Settable only when 4.0 V VDD 5.5 V Caution Set the transfer clock so as to satisfy the following conditions. * When 4.0 V VDD 5.5 V: 1.67 MHz or lower * When 2.7 V VDD < 4.0 V: 833.33 kHz or lower Remark fW: Base clock frequency selected by CKS00 bit of CSIS0 register fPRS: Peripheral hardware clock frequency User's Manual U17397EJ4V0UD 411 CHAPTER 17 SERIAL INTERFACE CSIA0 www..com (5) Automatic data transfer address point specification register 0 (ADTP0) This is an 8-bit register used to specify the buffer RAM address that ends transfer during automatic data transfer (bit 6 (ATE0) of serial operation mode specification register 0 = 1). This register can be set by an 8-bit memory manipulation instruction. However, during transfer (TSF0 = 1), rewriting ADTP0 is prohibited. In the 78K0/KF2, 00H to 1FH can be specified because 32 bytes of buffer RAM are incorporated. Example When ADTP0 is set to 07H 8 bytes of FA00H to FA07H are transferred. In repeat transfer mode (bit 5 (ATM0) of CSIMA0 = 1), transfer is performed repeatedly up to the address specified with ADTP0. Example When ADTP0 is set to 07H (repeat transfer mode) Transfer is repeated as FA00H to FA07H, FA00H to FA07H, ... . Figure 17-6. Format of Automatic Data Transfer Address Point Specification Register 0 (ADTP0) Address: FF94H Symbol ADTP0 After reset: 00H 7 0 6 0 R/W 5 0 4 ADTP04 3 ADTP03 2 ADTP02 1 ADTP01 0 ADTP00 Caution Be sure to clear bits 7 to 5 to "0". The relationship between transfer end buffer RAM address values and ADTP0 setting values is shown below. Table 17-2. Relationship Between Transfer End Buffer RAM Address Values and ADTP0 Setting Values Transfer End Buffer RAM Address Value FAxxH ADTP0 Setting Value xxH Remark xx: 00 to 1F 412 User's Manual U17397EJ4V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 www..com (6) Automatic data transfer interval specification register 0 (ADTI0) This is an 8-bit register used to specify the interval time for byte data transfer during automatic data transfer (bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) = 1). Set this register when in master mode (bit 4 (MASTER0) of CSIMA0 = 1) (setting is unnecessary in slave mode). Setting in 1-byte communication mode (bit 6 (ATE0) of CSIMA0 = 0) is also valid. When the interval time specified by ADTI0 after the end of 1-byte communication has elapsed, an interrupt request signal (INTACSI) is output. The number of clocks for the interval can be set to between 0 and 63 clocks. This register can be set by an 8-bit memory manipulation instruction. However, when bit 0 (TSF0) of serial status register 0 (CSIS0) is 1, rewriting ADTI0 is prohibited. Figure 17-7. Format of Automatic Data Transfer Interval Specification Register 0 (ADTI0) Address: FF95H Symbol ADTI0 After reset: 00H 7 0 6 0 R/W 5 ADTI05 4 ADTI04 3 ADTI03 2 ADTI02 1 ADTI01 0 ADTI00 Caution Because the setting of bit 5 (STBE0) and bit 4 (BUSYE0) of serial status register 0 (CSIS0) takes priority over the ADTI0 setting, the interval time based on the setting of STBE0 and BUSYE0 is generated even when ADTI0 is cleared to 00H. Example Interval time when ADTI0 = 00H and busy signal is not generated <1> When STBE0 = 1, BUSYE0 = 0: Interval time of two serial clocks is generated <2> When STBE0 = 0, BUSYE0 = 1: Interval time of one serial clock is generated <3> When STBE0 = 1, BUSYE0 = 1: Interval time of two serial clocks is generated Therefore, clearing STBE0 and BUSYE0 to 0 is required to perform no-wait transfer. The specified interval time is the serial clock (specified by divisor selection register 0 (BRGCA0)) multiplied by an integer value. Example When ADTI0 = 03H SCKA0 Interval time of 3 clocks User's Manual U17397EJ4V0UD 413 CHAPTER 17 SERIAL INTERFACE CSIA0 www..com (7) Automatic data transfer address count register 0 (ADTC0) This is a register used to indicate buffer RAM addresses during automatic transfer. When automatic transfer is stopped, the data position when transfer stopped can be ascertained by reading ADTC0 register value. This register can be read by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. However, reading from ADTC0 is prohibited when bit 0 (TSF0) of serial status register 0 (CSIS0) = 1. Figure 17-8. Format of Automatic Data Transfer Address Count Register 0 (ADTC0) Address: FF97H Symbol ADTC0 After reset: 00H 7 0 6 0 R 5 0 4 ADTC04 3 ADTC03 2 ADTC02 1 ADTC01 0 ADTP00 (8) Port mode register 14 (PM14) This register sets port 14 input/output in 1-bit units. When using P142/SCKA0 pin as the clock output of the serial interface, clear PM142 to 0 and set the output latch of P142 to 1. When using P144/SOA0 and P145/STB0 pins as the data output or strobe output of the serial interface, clear PM144, PM145, and the output latches of P144 and P145 to 0. When using P141/BUSY0, P142/SCKA0, and P143/SIA0 pins as the busy input, clock input, or data input of the serial interface, set PM141, PM142, and PM143 to 1. At this time, the output latches of P141, P142, and P143 may be 0 or 1. PM14 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Figure 17-9. Format of Port Mode Register 14 (PM14) Address: FF2EH Symbol PM14 7 1 After reset: FFH 6 1 R/W 5 PM145 4 PM144 3 PM143 2 PM142 1 PM141 0 PM140 PM14n 0 1 P14n pin I/O mode selection (n = 0 to 5) Output mode (output buffer on) Input mode (output buffer off) 414 User's Manual U17397EJ4V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 www..com 17.4 Operation of Serial Interface CSIA0 Serial interface CSIA0 has the following three modes. Operation stop mode 3-wire serial I/O mode * 3-wire serial I/O mode with automatic transmit/receive function 17.4.1 Operation stop mode Serial communication is not executed in this mode. Therefore, the power consumption can be reduced. In addition, the P142/SCKA0, P143/SIA0, and P144/SOA0 pins can be used as ordinary I/O port pins in this mode. (1) Register used The operation stop mode is set by serial operation mode specification register 0 (CSIMA0). To set the operation stop mode, clear bit 7 (CSIAE0) of CSIMA0 to 0. (a) Serial operation mode specification register 0 (CSIMA0) This is an 8-bit register used to control the serial communication operation. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Address: FF90H <> CSIMA0 CSIAE0 ATE0 ATM0 MASTER0 After reset: 00H R/W <> TXEA0 <> RXEA0 DIR0 0 CSIAE0 0 Control of CSIA0 operation enable/disable CSIA0 operation disabled (SOA0: Low level, SCKA0: High level) and asynchronously resets the internal circuit User's Manual U17397EJ4V0UD 415 CHAPTER 17 SERIAL INTERFACE CSIA0 www..com 17.4.2 3-wire serial I/O mode The one-byte data transmission/reception is executed in the mode in which bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) is cleared to 0. The 3-wire serial I/O mode is useful for connecting peripheral ICs and display controllers with a clocked serial interface. In this mode, communication is executed by using three lines: serial clock (SCKA0), serial output (SOA0), and serial input (SIA0) lines. (1) Registers used Serial operation mode specification register 0 (CSIMA0)Note 1 Serial status register 0 (CSIS0)Note 2 Divisor selection register 0 (BRGCA0) Port mode register 14 (PM14) Port register 14 (P14) Notes 1. Bits 7, 6, and 4 to 1 (CSIAE0, ATE0, MASTER0, TXEA0, RXEA0, and DIR0) are used. Setting of bit 5 (ATM0) is invalid. 2. Only bit 0 (TSF0) and bit 6 (CKS00) are used. The basic procedure of setting an operation in the 3-wire serial I/O mode is as follows. <1> Set bit 6 (CKS00) of the CSIS0 register (see Figure 17-3)Note 1. <2> Set the BRGCA0 register (see Figure 17-5) Note 1 . <3> Set bits 4 to 1 (MASTER0, TXEA0, RXEA0, and DIR0) of the CSIMA0 register (see Figure 17-2). <4> Set bit 7 (CSIAE0) of the CSIMA0 register to 1 and clear bit 6 (ATE0) to 0. <5> Write data to serial I/O shift register 0 (SIOA0). Data transmission/reception is startedNote 2. Notes 1. This register does not have to be set when the slave mode is specified (MASTER0 = 0). 2. Write dummy data to SIOA0 only for reception. Caution Take relationship with the other party of communication when setting the port mode register and port register. 416 User's Manual U17397EJ4V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 www..com The relationship between the register settings and pins is shown below. Table 17-3. Relationship Between Register Settings and Pins CSIAE0 ATE0 MASTER0 PM143 P143 PM144 P144 PM142 P142 Serial I/O Shift Register 0 Operation 0 x x xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 Operation stopped 1 0 0 1Note 2 xNote 2 0Note 3 0Note 3 1 x Operation enabled 1 0 1 Count operation SIA0Note 2 SOA0Note 3 SCKA0 (input) SCKA0 (output) Serial Clock Counter Operation Control Clear P143 P144 P142 SIA0/ P143 Pin Function SOA0/ P144 SCKA0/ P142 Notes 1. Can be set as port function. 2. Can be used as P143 when only transmission is performed. Clear bit 2 (RXEA0) of CSIMA0 to 0. 3. Can be used as P144 when only reception is performed. Clear bit 3 (TXEA0) of CSIMA0 to 0. Remark x: CSIAE0: ATE0: MASTER0: PM14x: P14x: don't care Bit 7 of serial operation mode specification register 0 (CSIMA0) Bit 6 of CSIMA0 Bit 4 of CSIMA0 Port mode register Port output latch User's Manual U17397EJ4V0UD 417 CHAPTER 17 SERIAL INTERFACE CSIA0 www..com (2) 1-byte transmission/reception communication operation (a) 1-byte transmission/reception When bit 7 (CSIAE0) and bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) = 1, 0, respectively, if communication data is written to serial I/O shift register 0 (SIOA0), the data is output via the SOA0 pin in synchronization with the SCKA0 falling edge, and stored in the SIOA0 register in synchronization with the rising edge 1 clock later. Data transmission and data reception can be performed simultaneously. If only reception is to be performed, communication can only be started by writing a dummy value to the SIOA0 register. When communication of 1 byte is complete, an interrupt request signal (INTACSI) is generated. In 1-byte transmission/reception, the setting of bit 5 (ATM0) of CSIMA0 is invalid. Be sure to read data after confirming that bit 0 (TSF0) of serial status register 0 (CSIS0) = 0. Figure 17-10. 3-Wire Serial I/O Mode Timing SCKA0 1 2 3 4 5 6 7 8 SIA0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SOA0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 TSF0 ACSIIF Transfer starts at falling edge of SCKA0 SIOA0 write End of transfer Caution The SOA0 pin becomes low level by an SIOA0 write. 418 User's Manual U17397EJ4V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 www..com (b) Data format In the data format, data is changed in synchronization with the SCKA0 falling edge as shown below. The data length is fixed to 8 bits and the data communication direction can be switched by the specification of bit 1 (DIR0) of serial operation mode specification register 0 (CSIMA0). Figure 17-11. Format of Transmit/Receive Data (a) MSB-first (DIR0 bit = 0) SCKA0 SIA0 SOA0 DO7 DI7 DO6 DI6 DO5 DI5 DO4 DI4 DO3 DI3 DO2 DI2 DO1 DI1 DO0 DI0 (b) LSB-first (DIR0 bit = 1) SCKA0 SIA0 SOA0 DO0 DI0 DO1 DI1 DO2 DI2 DO3 DI3 DO4 DI4 DO5 DI5 DO6 DI6 DO7 DI7 User's Manual U17397EJ4V0UD 419 CHAPTER 17 SERIAL INTERFACE CSIA0 www..com (c) Switching MSB/LSB as start bit Figure 17-12 shows the configuration of serial I/O shift register 0 (SIOA0) and the internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form. Switching MSB/LSB as the start bit can be specified using bit 1 (DIR0) of serial operation mode specification register 0 (CSIMA0). Figure 17-12. Transfer Bit Order Switching Circuit 7 6 Internal bus 1 0 LSB-first MSB-first Read/write gate Read/write gate SOA0 latch SIA0 Shift register 0 (SIOA0) D Q SOA0 SCKA0 Start bit switching is realized by switching the bit order for data written to SIOA0. The SIOA0 shift order remains unchanged. Thus, switching between MSB-first and LSB-first must be performed before writing data to the shift register. (d) Communication start Serial communication is started by setting communication data to serial I/O shift register 0 (SIOA0) when the following two conditions are satisfied. * Serial interface CSIA0 operation control bit (CSIAE0) = 1 * Serial communication is not in progress Caution If CSIAE0 is set to 1 after data is written to SIOA0, communication does not start. Upon termination of 8-bit communication, serial communication automatically stops and the interrupt request flag (ACSIIF) is set. 420 User's Manual U17397EJ4V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 www..com 17.4.3 3-wire serial I/O mode with automatic transmit/receive function Up to 32 bytes of data can be transmitted/received without using software in the mode in which bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) is set to 1. After communication is started, only data of the set number of bytes stored in RAM in advance can be transmitted, and only data of the set number of bytes can be received and stored in RAM. In addition, to transmit/receive data continuously when used as the master, handshake signals (STB0 and BUSY0) generated by hardware are supported. Therefore, connection to peripheral ICs such as OSD (On Screen Display) ICs and LCD controller/drivers can be easily realized. (1) Registers used Serial operation mode specification register 0 (CSIMA0) Serial status register 0 (CSIS0) Serial trigger register 0 (CSIT0) Divisor selection register 0 (BRGCA0) Automatic data transfer address point specification register 0 (ADTP0) Automatic data transfer interval specification register 0 (ADTI0) Port mode register 14 (PM14) Port register 14 (P14) The relationship between the register settings and pins is shown below. Caution A wait state may be generated when data is written to the buffer RAM. For details, see CHAPTER 34 CAUTIONS FOR WAIT. User's Manual U17397EJ4V0UD 421 422 0 1 Table 17-4. Relationship Between Register Settings and Pins CSIAE0 ATE0 MASTER0 STBE0 BUSYE0 ERRE0 PM143 P143 PM144 P144 PM142 P142 PM145 P145 PM141 P141 Serial I/O Shift Register 0 Operation Serial Clock Counter Operation Control Pin Function SIA0/ SOA0/ SCKA0/ STB0/ BUSY0/ P143 P143 Note 2 P144 P144 Note 3 P142 P142 P145 P145 P141 P141 P141 x 1 x 0 x x Note 1 xNote 1 x Note 1 xNote 1 0/1 xNote 1 1 xNote 1 x xNote 1 0 xNote 1 0 xNote 1 1 xNote 1 x xNote 1 x Note 1 xNote 1 x Note 1 xNote 1 x Note 1 xNote 1 Operation stopped Clear x Note 1 Operation enabled Count operation SIA0 SOA10 SCKA0 P145 (input) 1 0 1 0 1 0/1 0/1 0 1 xNote 1 0 xNote 1 0 xNote 1 1 xNote 1 x SCKA0 P145 P141 (output) STB0 BUSY0 Notes 1. 2. 3. User's Manual U17397EJ4V0UD Can be set as port function. CHAPTER 17 SERIAL INTERFACE CSIA0 Can be used as P143 when only transmission is performed. Clear bit 2 (RXEA0) of CSIMA0 to 0. Can be used as P144 when only reception is performed. Clear bit 3 (TXEA0) of CSIMA0 to 0. x: CSIAE0: ATE0: STBE0: BUSYE0: ERRE0: PM14x: P14x: don't care Bit 7 of serial operation mode specification register 0 (CSIMA0) Bit 6 of CSIMA0 Bit 5 of serial status register 0 (CSIS0) Bit 4 of CSIS0 Bit 2 of CSIS0 Port mode register Port output latch Remark MASTER0: Bit 4 of CSIMA0 www..com CHAPTER 17 SERIAL INTERFACE CSIA0 www..com (2) Automatic transmit/receive data setting Here is an example of the procedure for successively transmitting/receiving data as the master. <1> Enable CSIA0 to operate by setting bit 7 (CSIAE0) of serial operation mode specification register 0 (CSIMA0) to 1 (the buffer RAM can now be accessed). <2> Select a serial clock by using serial status register 0 (CSIS0). <3> Set the division ratio of the serial clock by using division value selection register 0 (BRGCA0), and specify a communication rate. <4> Sequentially write data to be transmitted to the buffer RAM, starting from the least significant address FA00H, up to FA1FH. Data is transmitted from the lowest address, continuing on to higher addresses. <5> Set "number of data items to be transmitted - 1" to automatic data transfer address point specification register 0 (ADTP0). <6> Set bits 6 (ATE0) and 4 (MASTER0) of CSIMA0 to select a master operation in the automatic communication mode. <7> Set bits 3 (TXEA0) and 2 (RXEA0) of CSIMA0 to 1 to enable transmission/reception. <8> Set the transmission interval of data to the automatic data transfer interval specification register (ADTI0). <9> Automatic transmit/receive processing is started when bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) is set to 1. Caution Take the relationship with the other communicating party into consideration when setting the port mode register and port register. Operations <1> to <9> execute the following operation. * After the buffer RAM data indicated by automatic data transfer address count register 0 (ADTC0) is transferred to SIOA0, transmission is carried out (start of automatic transmission/reception). * The received data is written to the buffer RAM address indicated by ADTC0. * ADTC0 is incremented and the next data transmission/reception is carried out. Data transmission/reception continues until the ADTC0 incremental output matches the set value of automatic data transfer address point specification register 0 (ADTP0) (end of automatic transmission/reception). However, if bit 5 (ATM0) of CSIMA0 is set to 1 (repeat mode), ADTC0 is cleared after a match between ADTP0 and ADTC0, and then repeated transmission/reception is started. * When automatic transmission/reception is terminated, an interrupt request (INTACSI) is generated and bit 0 (TSF0) of CSIS0 is cleared. * To continue transmitting the next data, set the new data to the buffer RAM, and set "number of data to be transmitted - 1" to ADTP0. After setting the number of data, set ATSTA0 to 1. User's Manual U17397EJ4V0UD 423 CHAPTER 17 SERIAL INTERFACE CSIA0 www..com (3) Automatic transmission/reception communication operation (a) Automatic transmission/reception mode Automatic transmission/reception can be performed using buffer RAM. The data stored in the buffer RAM is output from the SOA0 pin via the SIOA0 register in synchronization with the SCKA0 falling edge by performing (2) Automatic transmit/receive data setting. The receive data is stored in the buffer RAM via the SIOA0 register in synchronization with the SCKA0 rising edge. Data transfer ends if bit 0 (TSF0) of serial status register 0 (CSIS0) is set to 1 when any of the following conditions is met. * Communication stop: Reset by clearing bit 7 (CSIAE0) of the CSIMA0 register to 0 * Communication suspension: Transfer of 1 byte is complete by setting bit 1 (ATSTP0) of the CSIT0 register to 1 * Bit shift error: Transfer of 1 byte is complete when bit 1 (ERRF0) of the CSIS0 register becomes 1 while bit 2 (ERRE0) = 1 * Transfer of the range specified by the ADTP0 register is complete At this time, an interrupt request signal (INTACSI) is generated except when the CSIAE0 bit = 0. If a transfer is terminated in the middle, transfer starting from the remaining data is not possible. Read automatic data transfer address count register 0 (ADTC0) to confirm how much of the data has already been transferred and re-execute transfer by performing (2) Automatic transmit/receive data setting. In addition, when busy control and strobe control are not performed, the BUSY0/BUZ/INTP7/P141 and STB0/P145 pins can be used as ordinary I/O port pins. Figure 17-13 shows the example of the operation timing in automatic transmission/reception mode and Figure 17-14 shows the operation flowchart. Figures 17-15 and 17-16 show the operation of internal buffer RAM when 6 bytes of data are transmitted/received. 424 User's Manual U17397EJ4V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 www..com Figure 17-13. Example of Automatic Transmission/Reception Mode Operation Timings Interval SCKA0 SOA0 SIA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 ACSIIF TSF0 Cautions 1. Because, byte in the automatic transmission/reception an interval is mode, the until automatic the next transmit/receive function writes/reads data to/from the internal buffer RAM after 1transmission/reception, inserted transmission/reception. As the buffer RAM write/read is performed at the same time as CPU processing, the interval is dependent upon the value of automatic data transfer interval specification register 0 (ADTI0) and the set values of bits 5 and 4 (STBE0, BUSYE0) of serial status register 0 (CSIS0) (see (5) transmit/receive interval time). 2. If an access to the buffer RAM by the CPU conflicts with an access to the buffer RAM by serial interface CSIA0 during the interval period, the interval time specified by automatic data transfer interval specification register 0 (ADTI0) may be extended. Remark ACSIIF: Interrupt request flag TSF0: Bit 0 of serial status register 0 (CSIS0) Automatic User's Manual U17397EJ4V0UD 425 CHAPTER 17 SERIAL INTERFACE CSIA0 www..com Figure 17-14. Automatic Transmission/Reception Mode Flowchart Start Set CSIAE0 to 1 Set the communication speed Write transmit data in internal buffer RAMNote Software execution Set ADTP0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Set the automatic transmission/reception mode Set ATSTA0 to 1 Write transmit data from internal buffer RAM to SIOA0 Transmission/reception operation Increment ADTC0 Hardware execution Write receive data from SIOA0 to internal buffer RAMNote ADTP0 = ADTC0 No Yes TSF0 = 0 No Software execution Yes End CSIAE0: ADTP0: ADTI0: ATSTA0: SIOA0: ADTC0: TSF0: Bit 7 of serial operation mode specification register 0 (CSIMA0) Automatic data transfer address point specification register 0 Automatic data transfer interval specification register 0 Bit 0 of serial trigger register 0 (CSIT0) Serial I/O shift register 0 Automatic data transfer address count register 0 Bit 0 of serial status register 0 (CSIS0) For details, see Note A wait state may be generated when data is written to the buffer RAM. CHAPTER 34 CAUTIONS FOR WAIT. 426 User's Manual U17397EJ4V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 www..com In 6-byte transmission/reception (ATM0 = 0, RXEA0 = 1, TXEA0 = 1, ATE0 = 1) in automatic transmission/reception mode, internal buffer RAM operates as follows. (i) Starting automatic transmission/reception (see Figure 17-15) <1> When bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) is set to 1, transmit data 1 (T1) is transferred from the internal buffer RAM to SIOA0 and transmission/reception is started. <2> When transmission of the first byte is completed, the receive data 1 (R1) is transferred from SIOA0 to the buffer RAM, and automatic data transfer address count register 0 (ADTC0) is incremented. <3> Next, transmit data 2 (T2) is transferred from the internal buffer to SIOA0. Figure 17-15. Internal Buffer RAM Operation in Automatic Transmission/Reception Mode (Starting Transmission/Reception) (1/2) <1> Starting 1st byte transmission/reception FA1FH FA05H Transmit data 6 (T6) Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) Transmit data 2 (T2) 5 SIOA0 ADTP0 0 ADTC0 FA00H Transmit data 1 (T1) 0 ACSIIF FA1FH Data transmission FA05H Transmit data 6 (T6) Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) Transmit data 2 (T2) FA00H Transmit data 1 (T1) 0 ACSIIF 5 ADTP0 Transmit data 1 (T1) SIOA0 0 ADTC0 User's Manual U17397EJ4V0UD 427 CHAPTER 17 SERIAL INTERFACE CSIA0 www..com Figure 17-15. Internal Buffer RAM Operation in Automatic Transmission/Reception Mode (Starting Transmission/Reception) (2/2) <2> End of 1st byte transmission/reception FA1FH Data reception FA05H Transmit data 6 (T6) Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) Transmit data 2 (T2) FA00H Transmit data 1 (T1) +1 0 ACSIIF 5 ADTP0 Receive data 1 (R1) SIOA0 0 ADTC0 <3> Starting of 2nd byte transmission/reception FA1FH FA05H Transmit data 6 (T6) Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) Transmit data 2 (T2) Receive data 1 (R1) SIOA0 5 ADTP0 1 ADTC0 FA00H Receive data 1 (R1) 0 ACSIIF (ii) Completion of transmission/reception (see Figure 17-16) <1> When transmission/reception of the sixth byte is completed, receive data 6 (R6) is transferred from SIOA0 to the internal buffer RAM and ADTC0 is incremented. <2> When the value of ADPT0 and that of ADTC0 match, the automatic transmission/reception ends, and an interrupt request flag (ACSIIF) is set (INTACSI is generated). ADTC0 and bit 0 (TSF0) of serial status register 0 (CSIS0) are cleared to 0. 428 User's Manual U17397EJ4V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 www..com Figure 17-16. Internal Buffer RAM Operation in Automatic Transmission/Reception Mode (End of Transmission/Reception) <1> End of 6th byte transmission/reception FA1FH Data reception FA05H Transmit data 6 (T6) Receive data 5 (R5) Receive data 4 (R4) Receive data 3 (R3) Receive data 2 (R2) FA00H Receive data 1 (R1) +1 0 ACSIIF 5 ADTP0 Receive data 6 (R6) SIOA0 4 ADTC0 <2> End of automatic transmission/reception FA1FH FA05H Receive data 6 (R6) Receive data 5 (R5) Receive data 4 (R4) Receive data 3 (R3) Receive data 2 (R2) Receive data 6 (R6) SIOA0 5 Match 5 ADTP0 ADTC0 FA00H Receive data 1 (R1) 0 ACSIIF FA1FH FA05H Receive data 6 (R6) Receive data 5 (R5) Receive data 4 (R4) Receive data 3 (R3) Receive data 2 (R2) Receive data 6 (R6) SIOA0 5 ADTP0 5 ADTC0 FA00H Receive data 1 (R1) 1 ACSIIF User's Manual U17397EJ4V0UD 429 CHAPTER 17 SERIAL INTERFACE CSIA0 www..com (b) Automatic transmission mode In this mode, the specified data is transmitted in 8-bit unit. Serial communication is started when bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) is set to 1 while bit 7 (CSIAE0), bit 6 (ATE0), and bit 3 (TXEA0) of serial operation mode specification register 0 (CSIMA0) are set to 1. When the final byte has been transmitted, an interrupt request flag (ACSIIF) is set. The termination of automatic transmission can also be judged by bit 0 (TSF0) of serial status register 0 (CSIS0). If a receive operation, busy control and strobe control are not executed, the SIA0/P143, BUSY0/BUZ/INTP7/P141, and STB0/P145 pins can be used as normal I/O port pins. Figure 17-17 shows the example of the automatic transmission mode operation timing, and Figure 17-18 shows the operation flowchart. Figure 17-17. Example of Automatic Transmission Mode Operation Timing Interval SCKA0 SOA0 ACSIIF TSF0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Cautions 1. Because, in the automatic transmission mode, the automatic transmit/receive function reads data from the internal buffer RAM after 1-byte transmission, an interval is inserted until the next transmission. As the buffer RAM read is performed at the same time as CPU processing, the interval is dependent upon the value of automatic data transfer interval specification register 0 (ADTI0) and the set values of bits 5 and 4 (STBE0, BUSYE0) of serial status register 0 (CSIS0) (see (5) Automatic transmit/receive interval time). 2. If an access to the buffer RAM by the CPU conflicts with an access to the buffer RAM by serial interface CSIA0 during the interval period, the interval time specified by automatic data transfer interval specification register 0 (ADTI0) may be extended. Remark ACSIIF: Interrupt request flag TSF0: Bit 0 of serial status register 0 (CSIS0) 430 User's Manual U17397EJ4V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 www..com Figure 17-18. Automatic Transmission Mode Flowchart Start Set CSIAE0 to 1 Set the communication rate Write transmit data in internal buffer RAMNote Software execution Set ADTP0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Set the automatic transmission mode Set ATSTA0 to 1 Write transmit data from internal buffer RAM to SIOA0 Increment ADTC0 Transmission operation Hardware execution ADTP0 = ADTC0 No Yes TSF0 = 0 No Software execution Yes End CSIAE0: ADTP0: ADTI0: ATSTA0: SIOA0: ADTC0: TSF0: Bit 7 of serial operation mode specification register 0 (CSIMA0) Automatic data transfer address point specification register 0 Automatic data transfer interval specification register 0 Bit 0 of serial trigger register 0 (CSIT0) Serial I/O shift register 0 Automatic data transfer address count register 0 Bit 0 of serial status register 0 (CSIS0) For details, see Note A wait state may be generated when data is written to the buffer RAM. CHAPTER 34 CAUTIONS FOR WAIT. User's Manual U17397EJ4V0UD 431 CHAPTER 17 SERIAL INTERFACE CSIA0 www..com (c) Repeat transmission mode In this mode, data stored in the internal buffer RAM is transmitted repeatedly. Serial communication is started when bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) is set to 1 while bit 7 (CSIAE0), bit 6 (ATE0), bit 5 (ATM0), and bit 3 (TXEA0) of serial operation mode specification register 0 (CSIMA0) are set to 1. Unlike the automatic transmission mode, after the number of setting bytes has been transmitted, the interrupt request flag (ACSIIF) is not set, automatic data transfer address count register 0 (ADTC0) is reset to 0, and the internal buffer RAM contents are transmitted again. When a reception operation, busy control and strobe control are not performed, the SIA0/P143, BUSY0/BUZ/INTP7/P141, and STB0/P145 pins can be used as ordinary I/O port pins. The example of the repeat transmission mode operation timing is shown in Figure 17-19, and the operation flowchart in Figure 17-20. Figure 17-19. Example of Repeat Transmission Mode Operation Timing Interval Interval SCKA0 SOA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 Cautions 1. Because, in the repeat transmission mode, a read is performed on the buffer RAM after the transmission of one byte, the interval is included in the period up to the next transmission. As the buffer RAM read is performed at the same time as CPU processing, the interval is dependent upon automatic data transfer interval specification register 0 (ADTI0) and the set values of bits 5 and 4 (STBE0, BUSYE0) of serial status register 0 (CSIS0) (see (5) Automatic transmit/receive interval time). 2. If an access to the buffer RAM by the CPU conflicts with an access to the buffer RAM by serial interface CSIA0 during the interval period, the interval time specified by automatic data transfer interval specification register 0 (ADTI0) may be extended. 432 User's Manual U17397EJ4V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 www..com Figure 17-20. Repeat Transmission Mode Flowchart Start Set CSIAE0 to 1 Set the communication rate Write transmit data in internal buffer RAMNote Software execution Set ADTP0 to the value (point value) obtained by subtracting 1 from the number of transmit data bytes Set the repeat transmission mode Set ATSTA0 to 1 Write transmit data from internal buffer RAM to SIOA0 Increment ADTC0 Transmission operation Hardware execution ADTP0 = ADTC0 No Yes Reset ADTC0 to 0 CSIAE0: ADTP0: ADTI0: ATSTA0: SIOA0: ADTC0: Bit 7 of serial operation mode specification register 0 (CSIMA0) Automatic data transfer address point specification register 0 Automatic data transfer interval specification register 0 Bit 0 of serial trigger register 0 (CSIT0) Serial I/O shift register 0 Automatic data transfer address count register 0 For details, see Note A wait state may be generated when data is written to the buffer RAM. CHAPTER 34 CAUTIONS FOR WAIT. User's Manual U17397EJ4V0UD 433 CHAPTER 17 SERIAL INTERFACE CSIA0 www..com (d) Data format Data is changed in synchronization with the SCKA0 falling edge as shown below. The data length is fixed to 8 bits and the data transfer direction can be switched by the specification of bit 1 (DIR0) of serial operation mode specification register 0 (CSIMA0). Figure 17-21. Format of CSIA0 Transmit/Receive Data (a) MSB-first (DIR0 bit = 0) SCKA0 SIA0 SOA0 DO7 DI7 DO6 DI6 DO5 DI5 DO4 DI4 DO3 DI3 DO2 DI2 DO1 DI1 DO0 DI0 (b) LSB-first (DIR0 bit = 1) SCKA0 SIA0 SOA0 DO0 DI0 DO1 DI1 DO2 DI2 DO3 DI3 DO4 DI4 DO5 DI5 DO6 DI6 DO7 DI7 434 User's Manual U17397EJ4V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 www..com (e) Automatic transmission/reception suspension and restart Automatic transmission/reception can be temporarily suspended by setting bit 1 (ATSTP0) of serial trigger register 0 (CSIT0) to 1. During 8-bit data communication, the transmission/reception is not suspended. It is suspended upon completion of 8-bit data communication. When suspended, bit 0 (TSF0) of serial status register 0 (CSIS0) is cleared to 0 after transfer of the 8th bit. Cautions 1. If the HALT instruction is executed during automatic transmission/reception, communication is suspended and the HALT mode is set if during 8-bit data communication. When the HALT mode is cleared, automatic transmission/reception is restarted from the suspended point. 2. When suspending automatic transmission/reception, do not change the operating mode to 3-wire serial I/O mode while TSF0 = 1. Figure 17-22. Automatic Transmission/Reception Suspension and Restart Suspend command (ATSTP0 = 1) Suspend Restart command (after each register setting, ATSTA0 = 1) SCKA0 SOA0 SIA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 ATSTP0: Bit 1 of serial trigger register 0 (CSIT0) ATSTA0: Bit 0 of CSIT0 User's Manual U17397EJ4V0UD 435 CHAPTER 17 SERIAL INTERFACE CSIA0 www..com (4) Synchronization control Busy control and strobe control are functions used to synchronize transmission/reception between the master device and a slave device. By using these functions, a shift in bits being transmitted or received can be detected. (a) Busy control option Busy control is a function to keep the serial transmission/reception by the master device waiting while the busy signal output by a slave device to the master is active. When using this busy control option, the following conditions must be satisfied. * Bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) is set to 1. * Bit 4 (BUSYE0) of serial status register 0 (CSIS0) is set to 1. Figure 17-23 shows the system configuration of the master device and slave device when the busy control option is used. Figure 17-23. System Configuration When Busy Control Option Is Used Master device (78K0/KF2) SCKA0 SOA0 SIA0 BUSY0 Slave device SCKA SIA SOA Busy output The master device inputs the busy signal output by the slave device to the BUSY0/BUZ/INTP7/P141 pin. The master device samples the input busy signal in synchronization with the falling of the serial clock. Even if the busy signal becomes active while 8-bit data is being transmitted or received, transmission/reception by the master is not kept waiting. If the busy signal is active at the rising edge of the serial clock one clock after completion of transmission/reception of the 8-bit data, the busy input becomes valid. After that, the master transmission/reception is kept waiting while the busy signal is active. The active level of the busy signal is set by bit 3 (BUSYLV0) of CSIS0. BUSYLV0 = 1: Active-high BUSYLV0 = 0: Active-low When using the busy control option, select the master mode. Control with the busy signal cannot be implemented in the slave mode. Figure 17-24 shows the example of the operation timing when the busy control option is used. Caution Busy control cannot be used simultaneously with the interval time control function of automatic data transfer interval specification register 0 (ADTI0). 436 User's Manual U17397EJ4V0UD CHAPTER 17 SERIAL INTERFACE CSIA0 www..com Figure 17-24. Example of Operation Timing When Busy Control Option Is Used (When BUSYLV0 = 1) SCKA0 SOA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SIA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 BUSY0 Wait ACSIIF Busy input released Busy input valid TSF0 Remark ACSIIF: Interrupt request flag TSF0: Bit 0 of serial status register 0 (CSIS0) When the busy signal becomes inactive, waiting is released. If the sampled busy signal is inactive, transmission/reception of the next 8-bit data is started at the falling edge of the next serial clock. Because the busy signal is asynchronous with the serial clock, it takes up to 1 clock until the busy signal is sampled, even if made inactive by the slave. It takes 0.5 clock until data transfer is started after the busy signal was sampled. To accurately release the waiting, keep the busy signal inactive at the slave side, until SCKA0 falls. Figure 17-25 shows the example of the timing of the busy signal and releasing the waiting. This figure shows an example in which the busy signal is active as soon as transmission/reception has been started. Figure 17-25. Busy Signal and Wait Release (When BUSYLV0 = 1) SCKA0 SOA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SIA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 BUSY0 (active-high) 1.5 clocks (MAX.) If made inactive immediately after sampled Wait Busy input released Busy input valid User's Manual U17397EJ4V0UD 437 CHAPTER 17 SERIAL INTERFACE CSIA0 www..com (b) Busy & strobe control option Strobe control is a function used to synchronize data transmission/reception between the master and slave devices. The master device outputs the strobe signal from the STB0/P145 pin when 8-bit transmission/reception has been completed. By this signal, the slave device can determine the timing of the end of data transmission. Therefore, synchronization is established even if a bit shift occurs because noise is superimposed on the serial clock, and transmission of the next byte is not affected by the bit shift. To use the strobe control option, the following conditions must be satisfied: * Bit 6 (ATE0) of the serial operation mode specification register 0 (CSIMA0) is set to 1. * Bit 5 (STBE0) of serial status register 0 (CSIS0) is set to 1. Usually, the busy control and strobe control options are simultaneously used as handshake signals. In this case, the strobe signal is output from the STB0/P145 pin, the BUSY0/BUZ/INTP7/P141 pin can be sampled to keep transmission/reception waiting while the busy signal is input. A high level lasting for one transfer clock is output from the STB0/P145 pin in synchronization with the falling edge of the ninth serial clock as the strobe signal. The busy signal is detected at the rising edge of the serial clock two clocks after 8-bit data transmission/reception completion. Figure 17-26 shows the example of the operation timing when the busy & strobe control options are used. When the strobe control option is used, the interrupt request flag (ACSIIF) that is set on completion of transmission/reception is set after the strobe signal is output. Figure 17-26. Example of Operation Timing When Busy & Strobe Control Options Are Used (When BUSYLV0 = 1) SCKA0 SOA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SIA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 STB0 BUSY0 ACSIIF Busy input released Busy input valid TSF0 Caution Remark When TSF0 is cleared, the SOA0 pin goes low. ACSIIF: Interrupt request flag TSF0: Bit 0 of serial status register 0 (CSIS0) User's Manual U17397EJ4V0UD 438 CHAPTER 17 SERIAL INTERFACE CSIA0 www..com (c) Bit shift detection by busy signal During automatic transmission/reception, a bit shift of the serial clock of the slave device may occur because noise is superimposed on the serial clock signal output by the master device. Unless the strobe control option is used at this time, the bit shift affects transmission of the next byte. In this case, the master can detect the bit shift by checking the busy signal during transmission by using the busy control option. A bit shift is detected by using the busy signal as follows: The slave outputs the busy signal after the rising of the eighth serial clock during data transmission/reception (to not keep transmission/reception waiting by the busy signal at this time, make the busy signal inactive within 2 clocks). The master samples the busy signal in synchronization with the falling edge of the serial clock if bit 2 (ERRE0) of serial status register 0 (CSIS0) is set to 1. If a bit shift does not occur, all the eight serial clocks that have been sampled are inactive. If the sampled serial clocks are active, it is assumed that a bit shift has occurred, error processing is executed (by setting bit 1 (ERRF0) of serial status register 0 (CSIS0) to 1, and communication is suspended and an interrupt request signal (INTACSI) is output). Although communication is suspended after completion of 1-byte data communication, slave signal output, wait due to the busy signal, and wait due to the interval time specified by ADTI0 are not executed. If ERRE0 = 0, ERRF0 cannot become 1 even if a bit shift occurs. Figure 17-27 shows the example of the operation timing of the bit shift detection function by the busy signal. Figure 17-27. Example of Operation Timing of Bit Shift Detection Function by Busy Signal (When BUSYLV0 = 1) SCKA0 (Master) Bit shift due to noise SCKA0 (Slave) SOA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D7 D6 D5 D4 D3 D2 D1 D0 SIA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D7 D6 D5 D4 D3 D2 D1 D0 BUSY0 ACSIIF CSIAE0 ERRF0 Busy not detected Error interrupt request generated Error detected ACSIIF: ERRF0: Interrupt request flag Bit 1 of serial status register 0 (CSIS0) CSIAE0: Bit 7 of serial operation mode specification register 0 (CSIMA0) User's Manual U17397EJ4V0UD 439 CHAPTER 17 SERIAL INTERFACE CSIA0 www..com (5) Automatic transmit/receive interval time When using the automatic transmit/receive function, the read/write operations from/to the internal buffer RAM are performed after transmitting/receiving one byte. transmit/receive operation. Since the read/write operations from/to the buffer RAM are performed in parallel with the CPU processing when using the automatic transmit/receive function by the internal clock, the interval depends on the value which is set in automatic data transfer interval specification register 0 (ADTI0) and bits 5 (STBE0) and 4 (BUSYE0) of serial status register 0 (CSIS0). When ADTI0 is cleared to 00H, an interval time based on the to STBE0 and BUSYE0 settings is inserted. If ADTI0 = 00H and STBE0 = BUSYE0 = 1, for example, then an interval time of two clocks is inserted, and the interval time can be further extended by using an external busy signal. If an interval time of two clocks or more is set by using ADTI0, then the interval time set by ADTI0 is inserted, regardless of the settings of STBE0 and BUSYE0. When BUSYE0 = 1, the interval time can be further extended by an external busy signal. Example Interval time when ADTI0 = 00H and busy signal is not generated <1> When STBE0 = 1, BUSYE0 = 0: Interval time of two serial clocks is generated <2> When STBE0 = 0, BUSYE0 = 1: Interval time of one serial clock is generated <3> When STBE0 = 1, BUSYE0 = 1: Interval time of two serial clocks is generated Figure 17-28. Example of Interval Time for Automatic Transmission/Reception (When ADTI0 = 00H, STBE0 = 1, BUSYE0 = 0 (Two Clocks)) Interval Therefore, an interval is inserted before the next SCKA0 SOA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SIA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 ACSIIF ACSIIF: Interrupt request flag 440 User's Manual U17397EJ4V0UD www..com CHAPTER 18 SERIAL INTERFACE IIC0 18.1 Functions of Serial Interface IIC0 Serial interface IIC0 has the following two modes. (1) Operation stop mode This mode is used when serial transfers are not performed. It can therefore be used to reduce power consumption. (2) I2C bus mode (multimaster supported) This mode is used for 8-bit data transfers with several devices via two lines: a serial clock (SCL0) line and a serial data bus (SDA0) line. This mode complies with the I2C bus format and the master device can generated "start condition", "address", "transfer direction specification", "data", and "stop condition" data to the slave device, via the serial data bus. The slave device automatically detects these received status and data by hardware. This function can simplify the part of application program that controls the I2C bus. Since the SCL0 and SDA0 pins are used for open drain outputs, IIC0 requires pull-up resistors for the serial clock line and the serial data bus line. Figure 18-1 shows a block diagram of serial interface IIC0. User's Manual U17397EJ4V0UD 441 CHAPTER 18 SERIAL INTERFACE IIC0 www..com Figure 18-1. Block Diagram of Serial Interface IIC0 Internal bus IIC status register 0 (IICS0) MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0 IIC control register 0 (IICC0) IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 SDA0/ P61 Noise eliminator Slave address register 0 (SVA0) Match signal Clear Set Start condition generator DFC0 IIC shift register 0 (IIC0) DQ SO latch CL01, CL00 Stop condition generator TRC0 N-ch opendrain output PM61 Output latch (P61) Data hold time correction circuit ACK generator Wake-up controller Output control ACK detector Start condition detector Stop condition detector SCL0/ P60 Noise eliminator DFC0 N-ch opendrain output PM60 Output latch (P60) Serial clock counter Serial clock controller Serial clock wait controller Interrupt request signal generator INTIIC0 IICS0.MSTS0, EXC0, COI0 IIC shift register 0 (IIC0) Bus status detector IICC0.STT0, SPT0 IICS0.MSTS0, EXC0, COI0 fPRS EXSCL0/ P62 Prescaler CLD0 DAD0 SMC0 DFC0 CL01 CL00 IIC clock selection register 0 (IICCL0) CLX0 STCF IICBSY STCEN IICRSV IIC flag register 0 (IICF0) IIC function expansion register 0 (IICX0) Internal bus 442 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com Figure 18-2 shows a serial bus configuration example. Figure 18-2. Serial Bus Configuration Example Using I2C Bus + VDD + VDD Master CPU1 Slave CPU1 Address 0 SDA0 SCL0 Serial data bus Serial clock SDA0 SCL0 Master CPU2 Slave CPU2 Address 1 SDA0 SCL0 Slave CPU3 Address 2 SDA0 SCL0 Slave IC Address 3 SDA0 SCL0 Slave IC Address N User's Manual U17397EJ4V0UD 443 CHAPTER 18 SERIAL INTERFACE IIC0 www..com 18.2 Configuration of Serial Interface IIC0 Serial interface IIC0 includes the following hardware. Table 18-1. Configuration of Serial Interface IIC0 Item Registers Control registers Configuration IIC shift register 0 (IIC0) Slave address register 0 (SVA0) IIC control register 0 (IICC0) IIC status register 0 (IICS0) IIC flag register 0 (IICF0) IIC clock selection register 0 (IICCL0) IIC function expansion register 0 (IICX0) Port mode register 6 (PM6) Port register 6 (P6) (1) IIC shift register 0 (IIC0) IIC0 is used to convert 8-bit serial data to 8-bit parallel data and vice versa in synchronization with the serial clock. IIC0 can be used for both transmission and reception. The actual transmit and receive operations can be controlled by writing and reading operations to IIC0. Cancel the wait state and start data transfer by writing data to IIC0 during the wait period. IIC0 is set by an 8-bit memory manipulation instruction. Reset signal generation clears IIC0 to 00H. Figure 18-3. Format of IIC Shift Register 0 (IIC0) Address: FFA5H Symbol IIC0 7 After reset: 00H 6 5 R/W 4 3 2 1 0 Cautions 1. Do not write data to IIC0 during data transfer. 2. Write or read IIC0 only during the wait period. Accessing IIC0 in a communication state other than during the wait period is prohibited. When the device serves as the master, however, IIC0 can be written only once after the communication trigger bit (STT0) is set to 1. (2) Slave address register 0 (SVA0) This register stores local addresses when in slave mode. SVA0 is set by an 8-bit memory manipulation instruction. However, rewriting to this register is prohibited while STD0 = 1 (while the start condition is detected). Reset signal generation clears SVA0 to 00H. Figure 18-4. Format of Slave Address Register 0 (SVA0) Address: FFA7H Symbol SVA0 7 After reset: 00H 6 5 R/W 4 3 2 1 0 0Note Note Bit 0 is fixed to 0. 444 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com (3) SO latch The SO latch is used to retain the SDA0 pin's output level. (4) Wake-up controller This circuit generates an interrupt request (INTIIC0) when the address received by this register matches the address value set to slave address register 0 (SVA0) or when an extension code is received. (5) Prescaler This selects the sampling clock to be used. (6) Serial clock counter This counter counts the serial clocks that are output or input during transmit/receive operations and is used to verify that 8-bit data was transmitted or received. (7) Interrupt request signal generator This circuit controls the generation of interrupt request signals (INTIIC0). An I2C interrupt request is generated by the following two triggers. * Falling edge of eighth or ninth clock of the serial clock (set by WTIM0 bit) * Interrupt request generated when a stop condition is detected (set by SPIE0 bit) Remark WTIM0 bit: Bit 3 of IIC control register 0 (IICC0) SPIE0 bit: Bit 4 of IIC control register 0 (IICC0) (8) Serial clock controller In master mode, this circuit generates the clock output via the SCL0 pin from a sampling clock. (9) Serial clock wait controller This circuit controls the wait timing. (10) ACK generator, stop condition detector, start condition detector, and ACK detector These circuits generate and detect each status. (11) Data hold time correction circuit This circuit generates the hold time for data corresponding to the falling edge of the serial clock. (12) Start condition generator This circuit generates a start condition when the STT0 bit is set to 1. However, in the communication reservation disabled status (IICRSV bit = 1), when the bus is not released (IICBSY bit = 1), start condition requests are ignored and the STCF bit is set to 1. (13) Stop condition generator This circuit generates a stop condition when the SPT0 bit is set to 1. User's Manual U17397EJ4V0UD 445 CHAPTER 18 SERIAL INTERFACE IIC0 www..com (14) Bus status detector This circuit detects whether or not the bus is released by detecting start conditions and stop conditions. However, as the bus status cannot be detected immediately following operation, the initial status is set by the STCEN bit. Remark STT0 bit: SPT0 bit: IICBSY bit: STCF bit: Bit 1 of IIC control register 0 (IICC0) Bit 0 of IIC control register 0 (IICC0) Bit 6 of IIC flag register 0 (IICF0) Bit 7 of IIC flag register 0 (IICF0) IICRSV bit: Bit 0 of IIC flag register 0 (IICF0) STCEN bit: Bit 1 of IIC flag register 0 (IICF0) 446 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com 18.3 Registers to Control Serial Interface IIC0 Serial interface IIC0 is controlled by the following seven registers. * IIC control register 0 (IICC0) * IIC flag register 0 (IICF0) * IIC status register 0 (IICS0) * IIC clock selection register 0 (IICCL0) * IIC function expansion register 0 (IICX0) * Port mode register 6 (PM6) * Port register 6 (P6) (1) IIC control register 0 (IICC0) This register is used to enable/stop I2C operations, set wait timing, and set other I2C operations. IICC0 is set by a 1-bit or 8-bit memory manipulation instruction. However, set the SPIE0, WTIM0, and ACKE0 bits while IICE0 bit = 0 or during the wait period. These bits can be set at the same time when the IICE0 bit is set from "0" to "1". Reset signal generation clears IICC0 to 00H. User's Manual U17397EJ4V0UD 447 CHAPTER 18 SERIAL INTERFACE IIC0 www..com Figure 18-5. Format of IIC Control Register 0 (IICC0) (1/4) Address: FFA6H Symbol IICC0 <7> IICE0 After reset: 00H <6> LREL0 R/W <5> WREL0 <4> SPIE0 2 <3> WTIM0 <2> ACKE0 <1> STT0 <0> SPT0 IICE0 0 1 I C operation enable Stop operation. Reset IIC status register 0 (IICS0) Enable operation. Note 1 . Stop internal operation. Be sure to set this bit (1) while the SCL0 and SDA0 lines are at high level. Condition for clearing (IICE0 = 0) * Cleared by instruction * Reset Note 2 Condition for setting (IICE0 = 1) * Set by instruction LREL0 0 1 Exit from communications Normal operation This exits from the current communications and sets standby mode. This setting is automatically cleared to 0 after being executed. Its uses include cases in which a locally irrelevant extension code has been received. The SCL0 and SDA0 lines are set to high impedance. The following flags of IIC control register 0 (IICC0) and IIC status register 0 (IICS0) are cleared to 0. * STT0 * SPT0 * MSTS0 * EXC0 * COI0 * TRC0 * ACKD0 * STD0 The standby mode following exit from communications remains in effect until the following communications entry conditions are met. * After a stop condition is detected, restart is in master mode. * An address match or extension code reception occurs after the start condition. Condition for clearing (LREL0 = 0) * Automatically cleared after execution * Reset WREL0 0 1 Note 2 Condition for setting (LREL0 = 1) * Set by instruction Wait cancellation Do not cancel wait Cancel wait. This setting is automatically cleared after wait is canceled. When WREL0 is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status (TRC0 = 1), the SDA0 line goes into the high impedance state (TRC0 = 0). Condition for clearing (WREL0 = 0) * Automatically cleared after execution * Reset Condition for setting (WREL0 = 1) * Set by instruction Notes 1. The IICS0 register, the STCF0 and IICBSY bits of the IICF0 register, and the CLD0 and DAD0 bits of the IICCL0 register are reset. 2. This flag's signal is invalid when IICE0 = 0. Caution The start condition is detected immediately after I2C is enabled to operate (IICE0 = 1) while the SCL0 line is at high level and the SDA0 line is at low level. Immediately after enabling I2C to operate (IICE0 = 1), set LREL0 (1) by using a 1-bit memory manipulation instruction. 448 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com Figure 18-5. Format of IIC Control Register 0 (IICC0) (2/4) SPIE0 0 1 Note 1 Enable/disable generation of interrupt request when stop condition is detected Disable Enable Condition for setting (SPIE0 = 1) * Set by instruction Condition for clearing (SPIE0 = 0) * Cleared by instruction * Reset WTIM0 0 Note 1 Control of wait and interrupt request generation Interrupt request is generated at the eighth clock's falling edge. Master mode: After output of eight clocks, clock output is set to low level and wait is set. Slave mode: After input of eight clocks, the clock is set to low level and wait is set for master device. 1 Interrupt request is generated at the ninth clock's falling edge. Master mode: After output of nine clocks, clock output is set to low level and wait is set. Slave mode: After input of nine clocks, the clock is set to low level and wait is set for master device. An interrupt is generated at the falling edge of the ninth clock during address transfer independently of the setting of this bit. The setting of this bit is valid when the address transfer is completed. When in master mode, a wait is inserted at the falling edge of the ninth clock during address transfers. For a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after an acknowledge (ACK) is issued. However, when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. Condition for clearing (WTIM0 = 0) * Cleared by instruction * Reset Condition for setting (WTIM0 = 1) * Set by instruction ACKE0 0 1 Notes 1, 2 Acknowledgment control Disable acknowledgment. Enable acknowledgment. During the ninth clock period, the SDA0 line is set to low level. Condition for setting (ACKE0 = 1) * Set by instruction Condition for clearing (ACKE0 = 0) * Cleared by instruction * Reset Notes 1. This flag's signal is invalid when IICE0 = 0. 2. The set value is invalid during address transfer and if the code is not an extension code. When the device serves as a slave and the addresses match, an acknowledge is generated regardless of the set value. User's Manual U17397EJ4V0UD 449 CHAPTER 18 SERIAL INTERFACE IIC0 www..com Figure 18-5. Format of IIC Control Register 0 (IICC0) (3/4) STT0 0 1 Note Start condition trigger Do not generate a start condition. When bus is released (in STOP mode): Generate a start condition (for starting as master). When the SCL0 line is high level, the SDA0 line is changed from high level to low level and then the start condition is generated. Next, after the rated amount of time has elapsed, SCL0 is changed to low level (wait state). When a third party is communicating: * When communication reservation function is enabled (IICRSV = 0) Functions as the start condition reservation flag. When set to 1, automatically generates a start condition after the bus is released. * When communication reservation function is disabled (IICRSV = 1) STCF is set to 1 and information that is set (1) to STT0 is cleared. No start condition is generated. In the wait state (when master device): Generates a restart condition after releasing the wait. Cautions concerning set timing * For master reception: Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when ACKE0 has been cleared to 0 and slave has been notified of final reception. * For master transmission: A start condition cannot be generated normally during the acknowledge period. Set to 1 during the wait period that follows output of the ninth clock. * Cannot be set to 1 at the same time as SPT0. * Setting STT0 to 1 and then setting it again before it is cleared to 0 is prohibited. Condition for clearing (STT0 = 0) * Cleared by setting SST0 to 1 while communication reservation is prohibited. * Cleared by loss in arbitration * Cleared after start condition is generated by master device * Cleared by LREL0 = 1 (exit from communications) * When IICE0 = 0 (operation stop) * Reset Condition for setting (STT0 = 1) * Set by instruction Note This flag's signal is invalid when IICE0 = 0. Remarks 1. Bit 1 (STT0) becomes 0 when it is read after data setting. 2. IICRSV: Bit 0 of IIC flag register (IICF0) STCF: Bit 7 of IIC flag register (IICF0) 450 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com Figure 18-5. Format of IIC Control Register 0 (IICC0) (4/4) SPT0 0 1 Stop condition is not generated. Stop condition is generated (termination of master device's transfer). After the SDA0 line goes to low level, either set the SCL0 line to high level or wait until it goes to high level. Next, after the rated amount of time has elapsed, the SDA0 line changes from low level to high level and a stop condition is generated. Cautions concerning set timing * For master reception: Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when ACKE0 has been cleared to 0 and slave has been notified of final reception. * For master transmission: A stop condition cannot be generated normally during the acknowledge period. Therefore, set it during the wait period that follows output of the ninth clock. * Cannot be set to 1 at the same time as STT0. * SPT0 can be set to 1 only when in master mode Note Stop condition trigger . * When WTIM0 has been cleared to 0, if SPT0 is set to 1 during the wait period that follows output of eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock. WTIM0 should be changed from 0 to 1 during the wait period following the output of eight clocks, and SPT0 should be set to 1 during the wait period that follows the output of the ninth clock. * Setting SPT0 to 1 and then setting it again before it is cleared to 0 is prohibited. Condition for clearing (SPT0 = 0) * Cleared by loss in arbitration * Automatically cleared after stop condition is detected * Cleared by LREL0 = 1 (exit from communications) * When IICE0 = 0 (operation stop) * Reset Condition for setting (SPT0 = 1) * Set by instruction Note Set SPT0 to 1 only in master mode. However, SPT0 must be set to 1 and a stop condition generated before the first stop condition is detected following the switch to the operation enabled status. For details, see 18.5.15 Cautions. Caution When bit 3 (TRC0) of IIC status register 0 (IICS0) is set to 1, WREL0 is set to 1 during the ninth clock and wait is canceled, after which TRC0 is cleared and the SDA0 line is set to high impedance. Remark Bit 0 (SPT0) becomes 0 when it is read after data setting. User's Manual U17397EJ4V0UD 451 CHAPTER 18 SERIAL INTERFACE IIC0 www..com (2) IIC status register 0 (IICS0) This register indicates the status of I2C. IICS0 is read by a 1-bit or 8-bit memory manipulation instruction only when STT0 = 1 and during the wait period. Reset signal generation clears IICS0 to 00H. Caution If data is read from IICS0, a wait cycle is generated. Do not read data from IICS0 when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 34 CAUTIONS FOR WAIT. Figure 18-6. Format of IIC Status Register 0 (IICS0) (1/3) Address: FFAAH Symbol IICS0 <7> MSTS0 After reset: 00H <6> ALD0 <5> EXC0 R <4> COI0 <3> TRC0 <2> ACKD0 <1> STD0 <0> SPD0 MSTS0 0 1 Master device status Slave device status or communication standby status Master device communication status Condition for setting (MSTS0 = 1) * When a start condition is generated Condition for clearing (MSTS0 = 0) * When a stop condition is detected * When ALD0 = 1 (arbitration loss) * Cleared by LREL0 = 1 (exit from communications) * When IICE0 changes from 1 to 0 (operation stop) * Reset ALD0 0 1 Detection of arbitration loss This status means either that there was no arbitration or that the arbitration result was a "win". This status indicates the arbitration result was a "loss". MSTS0 is cleared. Condition for setting (ALD0 = 1) Note Condition for clearing (ALD0 = 0) * Automatically cleared after IICS0 is read * When IICE0 changes from 1 to 0 (operation stop) * Reset EXC0 0 1 Extension code was not received. Extension code was received. * When the arbitration result is a "loss". Detection of extension code reception Condition for clearing (EXC0 = 0) * When a start condition is detected * When a stop condition is detected * Cleared by LREL0 = 1 (exit from communications) * When IICE0 changes from 1 to 0 (operation stop) * Reset Condition for setting (EXC0 = 1) * When the higher four bits of the received address data is either "0000" or "1111" (set at the rising edge of the eighth clock). Note This register is also cleared when a 1-bit memory manipulation instruction is executed for bits other than IICS0. Therefore, when using the ALD0 bit, read the data of this bit before the data of the other bits. Remark LREL0: Bit 6 of IIC control register 0 (IICC0) IICE0: Bit 7 of IIC control register 0 (IICC0) User's Manual U17397EJ4V0UD 452 CHAPTER 18 SERIAL INTERFACE IIC0 www..com Figure 18-6. Format of IIC Status Register 0 (IICS0) (2/3) COI0 0 1 Addresses do not match. Addresses match. Condition for setting (COI0 = 1) * When the received address matches the local address (slave address register 0 (SVA0)) (set at the rising edge of the eighth clock). Detection of matching addresses Condition for clearing (COI0 = 0) * When a start condition is detected * When a stop condition is detected * Cleared by LREL0 = 1 (exit from communications) * When IICE0 changes from 1 to 0 (operation stop) * Reset TRC0 0 1 Detection of transmit/receive status Receive status (other than transmit status). The SDA0 line is set for high impedance. Transmit status. The value in the SO0 latch is enabled for output to the SDA0 line (valid starting at the falling edge of the first byte's ninth clock). Condition for clearing (TRC0 = 0) Note Condition for setting (TRC0 = 1) (wait cancel) * When ALD0 changes from 0 to 1 (arbitration loss) Note If the wait state is canceled by setting bit 5 (WREL0) of IIC control register 0 (IICC0) to 1 at the ninth clock when bit 3 (TRC0) of IIC status register 0 (IICS0) is 1, TRC0 is cleared, and the SDA0 line goes into a high-impedance state. Remark LREL0: Bit 6 of IIC control register 0 (IICC0) IICE0: Bit 7 of IIC control register 0 (IICC0) User's Manual U17397EJ4V0UD 453 CHAPTER 18 SERIAL INTERFACE IIC0 www..com Figure 18-6. Format of IIC Status Register 0 (IICS0) (3/3) ACKD0 0 1 Acknowledge was not detected. Acknowledge was detected. Condition for setting (ACKD0 = 1) * After the SDA0 line is set to low level at the rising edge of SCL0's ninth clock Detection of acknowledge (ACK) Condition for clearing (ACKD0 = 0) * When a stop condition is detected * At the rising edge of the next byte's first clock * Cleared by LREL0 = 1 (exit from communications) * When IICE0 changes from 1 to 0 (operation stop) * Reset STD0 0 1 Start condition was not detected. Detection of start condition Start condition was detected. This indicates that the address transfer period is in effect. Condition for setting (STD0 = 1) * When a start condition is detected Condition for clearing (STD0 = 0) * When a stop condition is detected * At the rising edge of the next byte's first clock following address transfer * Cleared by LREL0 = 1 (exit from communications) * When IICE0 changes from 1 to 0 (operation stop) * Reset SPD0 0 1 Stop condition was not detected. Detection of stop condition Stop condition was detected. The master device's communication is terminated and the bus is released. Condition for setting (SPD0 = 1) * When a stop condition is detected Condition for clearing (SPD0 = 0) * At the rising edge of the address transfer byte's first clock following setting of this bit and detection of a start condition * When IICE0 changes from 1 to 0 (operation stop) * Reset Remark LREL0: Bit 6 of IIC control register 0 (IICC0) IICE0: Bit 7 of IIC control register 0 (IICC0) (3) IIC flag register 0 (IICF0) This register sets the operation mode of I2C and indicates the status of the I2C bus. IICF0 is set by a 1-bit or 8-bit memory manipulation instruction. However, the STCF and IICBSY bits are readonly. The IICRSV bit can be used to enable/disable the communication reservation function (see 18.5.14 Communication reservation). STCEN can be used to set the initial value of the IICBSY bit (see 18.5.15 Cautions). IICRSV and STCEN can be written only when the operation of I2C is disabled (bit 7 (IICE0) of IIC control register 0 (IICC0) = 0). When operation is enabled, the IICF0 register can be read. Reset signal generation clears IICF0 to 00H. 454 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com Figure 18-7. Format of IIC Flag Register 0 (IICF0) Address: FFABH Symbol IICF0 <7> STCF STCF 0 1 Generate start condition Start condition generation unsuccessful: clear STT0 flag Condition for setting (STCF = 1) * Generating start condition unsuccessful and STT0 cleared to 0 when communication reservation is disabled (IICRSV = 1). I2C bus status flag Bus release status (communication initial status when STCEN = 1) Bus communication status (communication initial status when STCEN = 0) Condition for setting (IICBSY = 1) * Detection of start condition * Setting of IICE0 when STCEN = 0 After reset: 00H <6> IICBSY 5 0 R/WNote 4 0 3 0 2 0 <1> STCEN <0> IICRSV STT0 clear flag Condition for clearing (STCF = 0) * Cleared by STT0 = 1 * When IICE0 = 0 (operation stop) * Reset IICBSY 0 1 Condition for clearing (IICBSY = 0) * Detection of stop condition * When IICE0 = 0 (operation stop) * Reset STCEN 0 1 Initial start enable trigger After operation is enabled (IICE0 = 1), enable generation of a start condition upon detection of a stop condition. After operation is enabled (IICE0 = 1), enable generation of a start condition without detecting a stop condition. Condition for setting (STCEN = 1) * Set by instruction Condition for clearing (STCEN = 0) * Detection of start condition * Reset IICRSV 0 1 Communication reservation function disable bit Enable communication reservation Disable communication reservation Condition for setting (IICRSV = 1) * Set by instruction Condition for clearing (IICRSV = 0) * Cleared by instruction * Reset Note Bits 6 and 7 are read-only. Cautions 1. Write to STCEN only when the operation is stopped (IICE0 = 0). 2. As the bus release status (IICBSY = 0) is recognized regardless of the actual bus status when STCEN = 1, when generating the first start condition (STT0 = 1), it is necessary to verify that no third party communications are in progress in order to prevent such communications from being destroyed. 3. Write to IICRSV only when the operation is stopped (IICE0 = 0). Remark STT0: Bit 1 of IIC control register 0 (IICC0) IICE0: Bit 7 of IIC control register 0 (IICC0) User's Manual U17397EJ4V0UD 455 CHAPTER 18 SERIAL INTERFACE IIC0 www..com (4) IIC clock selection register 0 (IICCL0) This register is used to set the transfer clock for the I2C bus. IICCL0 is set by a 1-bit or 8-bit memory manipulation instruction. However, the CLD0 and DAD0 bits are readonly. The SMC0, CL01, and CL00 bits are set in combination with bit 0 (CLX0) of IIC function expansion register 0 (IICX0) (see 18.3 (6) I2C transfer clock setting method). Set IICCL0 while bit 7 (IICE0) of IIC control register 0 (IICC0) is 0. Reset signal generation clears IICCL0 to 00H. Figure 18-8. Format of IIC Clock Selection Register 0 (IICCL0) Address: FFA8H Symbol IICCL0 7 0 After reset: 00H 6 0 R/W <5> CLD0 Note <4> DAD0 <3> SMC0 <2> DFC0 1 CL01 0 CL00 CLD0 0 1 Detection of SCL0 pin level (valid only when IICE0 = 1) The SCL0 pin was detected at low level. The SCL0 pin was detected at high level. Condition for setting (CLD0 = 1) * When the SCL0 pin is at high level Condition for clearing (CLD0 = 0) * When the SCL0 pin is at low level * When IICE0 = 0 (operation stop) * Reset DAD0 0 1 Detection of SDA0 pin level (valid only when IICE0 = 1) The SDA0 pin was detected at low level. The SDA0 pin was detected at high level. Condition for setting (DAD0 = 1) * When the SDA0 pin is at high level Condition for clearing (DAD0 = 0) * When the SDA0 pin is at low level * When IICE0 = 0 (operation stop) * Reset SMC0 0 1 Operates in standard mode. Operates in high-speed mode. Operation mode switching DFC0 0 1 Digital filter off. Digital filter on. Digital filter operation control Digital filter can be used only in high-speed mode. In high-speed mode, the transfer clock does not vary regardless of DFC0 bit set (1)/clear (0). The digital filter is used for noise elimination in high-speed mode. Note Bits 4 and 5 are read-only. Remark IICE0: Bit 7 of IIC control register 0 (IICC0) 456 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com (5) IIC function expansion register 0 (IICX0) This register sets the function expansion of I2C. IICX0 is set by a 1-bit or 8-bit memory manipulation instruction. The CLX0 bit is set in combination with bits 3, 1, and 0 (SMC0, CL01, and CL00) of IIC clock selection register 0 (IICCL0) (see 18.3 (6) I2C transfer clock setting method). Set IICX0 while bit 7 (IICE0) of IIC control register 0 (IICC0) is 0. Reset signal generation clears IICX0 to 00H. Figure 18-9. Format of IIC Function Expansion Register 0 (IICX0) Address: FFA9H Symbol IICX0 7 0 After reset: 00H 6 0 5 0 R/W 4 0 3 0 2 0 1 0 <0> CLX0 (6) I2C transfer clock setting method The I2C transfer clock frequency (fSCL) is calculated using the following expression. fSCL = 1/(m x T + tR + tF) m = 12, 18, 24, 44, 66, 86 (see Table 18-2 Selection Clock Setting) T: tR: tF: 1/fW SCL0 rise time SCL0 fall time User's Manual U17397EJ4V0UD 457 CHAPTER 18 SERIAL INTERFACE IIC0 www..com For example, the I2C transfer clock frequency (fSCL) when fW = fPRS/2 = 4.19 MHz, m = 86, tR = 200 ns, and tF = 50 ns is calculated using following expression. fSCL = 1/(88 x 238.7 ns + 200 ns + 50 ns) 48.1 kHz m x T + tR + tF tR m/2 x T tF m/2 x T SCL0 SCL0 inversion SCL0 inversion SCL0 inversion The selection clock is set using a combination of bits 3, 1, and 0 (SMC0, CL01, and CL00) of IIC clock selection register 0 (IICCL0) and bit 0 (CLX0) of IIC function expansion register 0 (IICX0). Table 18-2. Selection Clock Setting IICX0 Bit 0 CLX0 0 0 0 0 0 0 0 1 1 1 1 Bit 3 SMC0 0 0 0 0 1 1 1 0 1 1 1 IICCL0 Bit 1 CL01 0 0 1 1 0 1 1 x 0 1 1 Bit 0 CL00 0 1 0 1 x 0 1 x x 0 1 fPRS/2 fPRS/2 fPRS/4 fEXSCL0 fPRS/2 fPRS/4 fEXSCL0 Setting prohibited fPRS/2 fPRS/4 Setting prohibited fW/12 fW/12 4.00 to 4.19 MHz High-speed mode (SMC0 bit = 1) fW/44 fW/86 fW/86 fW/66 fW/24 fW/24 fW/18 6.4 MHz 6.4 MHz 4.00 to 8.38 MHz High-speed mode (SMC0 bit = 1) 2.00 to 4.19 MHz 4.19 to 8.38 MHz Normal mode (SMC0 bit = 0) Selection Clock (fW) Transfer Clock (fW/m) Settable Selection Clock (fW) Range Operation Mode Caution Determine the transfer clock frequency of I2C by using CLX0, SMC0, CL01, and CL00 before enabling the operation (by setting bit 7 (IICE0) of IIC control register 0 (IICC0) to 1). To change the transfer clock frequency, clear IICE0 once to 0. Remarks 1. x: 2. fPRS: 3. fEXSCL0: don't care Peripheral hardware clock frequency External clock frequency from EXSCL0 pin 458 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com (7) Port mode register 6 (PM6) This register sets the input/output of port 6 in 1-bit units. When using the P60/SCL0 pin as clock I/O and the P61/SDA0 pin as serial data I/O, clear PM60 and PM61, and the output latches of P60 and P61 to 0. Set IICE0 (bit 7 of IIC control register 0 (IICC0)) to 1 before setting the output mode because the P60/SCL0 and P61/SDA0 pins output a low level (fixed) when IICE0 is 0. PM6 is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PM6 to FFH. Figure 18-10. Format of Port Mode Register 6 (PM6) Address: FF26H Symbol PM6 7 PM67 After reset: FFH 6 PM66 R/W 5 PM65 4 PM64 3 PM63 2 PM62 1 PM61 0 PM60 PM6n 0 1 P6n pin I/O mode selection (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off) User's Manual U17397EJ4V0UD 459 CHAPTER 18 SERIAL INTERFACE IIC0 www..com 18.4 I2C Bus Mode Functions 18.4.1 Pin configuration The serial clock pin (SCL0) and serial data bus pin (SDA0) are configured as follows. (1) SCL0....... This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. (2) SDA0 ...... This pin is used for serial data input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. Since outputs from the serial clock line and the serial data bus line are N-ch open-drain outputs, an external pull-up resistor is required. Figure 18-11. Pin Configuration Diagram Slave device VDD Master device SCL0 Clock output VSS (Clock input) SDA0 Data output VSS Data input VSS Data input SDA0 Data output VDD VSS Clock input SCL0 (Clock output) 460 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com 18.5 I2C Bus Definitions and Control Methods The following section describes the I2C bus's serial data communication format and the signals used by the I2C bus. Figure 18-12 shows the transfer timing for the "start condition", "address", "data", and "stop condition" output via the I2C bus's serial data bus. Figure 18-12. I2C Bus Serial Data Transfer Timing SCL0 1-7 8 9 1-8 9 1-8 9 SDA0 Start condition Address R/W ACK Data ACK Data ACK Stop condition The master device generates the start condition, slave address, and stop condition. The acknowledge (ACK) can be generated by either the master or slave device (normally, it is output by the device that receives 8-bit data). The serial clock (SCL0) is continuously output by the master device. However, in the slave device, the SCL0's low level period can be extended and a wait can be inserted. 18.5.1 Start conditions A start condition is met when the SCL0 pin is at high level and the SDA0 pin changes from high level to low level. The start conditions for the SCL0 pin and SDA0 pin are signals that the master device generates to the slave device when starting a serial transfer. When the device is used as a slave, start conditions can be detected. Figure 18-13. Start Conditions SCL0 H SDA0 A start condition is output when bit 1 (STT0) of IIC control register 0 (IICC0) is set (to 1) after a stop condition has been detected (SPD0: Bit 0 = 1 in IIC status register 0 (IICS0)). When a start condition is detected, bit 1 (STD0) of IICS0 is set (to 1). User's Manual U17397EJ4V0UD 461 CHAPTER 18 SERIAL INTERFACE IIC0 www..com 18.5.2 Addresses The address is defined by the 7 bits of data that follow the start condition. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines. Therefore, each slave device connected via the bus lines must have a unique address. The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address data matches the data values stored in slave address register 0 (SVA0). If the address data matches the SVA0 values, the slave device is selected and communicates with the master device until the master device generates a start condition or stop condition. Figure 18-14. Address SCL0 1 2 3 4 5 6 7 8 9 SDA0 A6 A5 A4 A3 Address A2 A1 A0 R/W INTIIC0 Note Note INTIIC0 is not issued if data other than a local address or extension code is received during slave device operation. The slave address and the eighth bit, which specifies the transfer direction as described in 18.5.3 addresses are written to IIC0. The slave address is assigned to the higher 7 bits of IIC0. 18.5.3 Transfer direction specification In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this transfer direction specification bit has a value of "0", it indicates that the master device is transmitting data to a slave device. When the transfer direction specification bit has a value of "1", it indicates that the master device is receiving data from a slave device. Figure 18-15. Transfer Direction Specification SCL0 1 2 3 4 5 6 7 8 9 Transfer direction specification below, are together written to IIC shift register 0 (IIC0) and are then output. Received SDA0 A6 A5 A4 A3 A2 A1 A0 R/W Transfer direction specification INTIIC0 Note Note INTIIC0 is not issued if data other than a local address or extension code is received during slave device operation. 462 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com 18.5.4 Acknowledge (ACK) ACK is used to check the status of serial data at the transmission and reception sides. The reception side returns ACK each time it has received 8-bit data. The transmission side usually receives ACK after transmitting 8-bit data. When ACK is returned from the reception side, it is assumed that reception has been correctly performed and processing is continued. Whether ACK has been detected can be checked by using bit 2 (ACKD0) of IIC status register 0 (IICS0). When the master receives the last data item, it does not return ACK and instead generates a stop condition. If a slave does not return ACK after receiving data, the master outputs a stop condition or restart condition and stops transmission. If ACK is not returned, the possible causes are as follows. <1> Reception was not performed normally. <2> The final data item was received. <3> The reception side specified by the address does not exist. To generate ACK, the reception side makes the SDA0 line low at the ninth clock (indicating normal reception). Automatic generation of ACK is enabled by setting bit 2 (ACKE0) of IIC control register 0 (IICC0) to 1. Bit 3 (TRC0) of the IICS0 register is set by the data of the eighth bit that follows 7-bit address information. Usually, set ACKE0 to 1 for reception (TRC0 = 0). If a slave can receive no more data during reception (TRC0 = 0) or does not require the next data item, then the slave must inform the master, by clearing ACKE0 to 0, that it will not receive any more data. When the master does not require the next data item during reception (TRC0 = 0), it must clear ACKE0 to 0 so that ACK is not generated. In this way, the master informs a slave at the transmission side that it does not require any more data (transmission will be stopped). Figure 18-16. ACK SCL0 1 2 3 4 5 6 7 8 9 SDA0 A6 A5 A4 A3 A2 A1 A0 R/W ACK When the local address is received, ACK is automatically generated, regardless of the value of ACKE0. When an address other than that of the local address is received, ACK is not generated (NACK). When an extension code is received, ACK is generated if ACKE0 is set to 1 in advance. How ACK is generated when data is received differs as follows depending on the setting of the wait timing. * When 8-clock wait state is selected (bit 3 (WTIM0) of IICC0 register = 0): By setting ACKE0 to 1 before releasing the wait state, ACK is generated at the falling edge of the eighth clock of the SCL0 pin. * When 9-clock wait state is selected (bit 3 (WTIM0) of IICC0 register = 1): ACK is generated by setting ACKE0 to 1 in advance. User's Manual U17397EJ4V0UD 463 CHAPTER 18 SERIAL INTERFACE IIC0 www..com 18.5.5 Stop condition When the SCL0 pin is at high level, changing the SDA0 pin from low level to high level generates a stop condition. A stop condition is a signal that the master device generates to the slave device when serial transfer has been completed. When the device is used as a slave, stop conditions can be detected. Figure 18-17. Stop Condition SCL0 H SDA0 A stop condition is generated when bit 0 (SPT0) of IIC control register 0 (IICC0) is set to 1. When the stop condition is detected, bit 0 (SPD0) of IIC status register 0 (IICS0) is set to 1 and INTIIC0 is generated when bit 4 (SPIE0) of IICC0 is set to 1. 464 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com 18.5.6 Wait The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCL0 pin to low level notifies the communication partner of the wait state. When wait state has been canceled for both the master and slave devices, the next data transfer can begin. Figure 18-18. Wait (1/2) (1) When master device has a nine-clock wait and slave device has an eight-clock wait (master transmits, slave receives, and ACKE0 = 1) Master Master returns to high impedance but slave is in wait state (low level). Wait after output of ninth clock IIC0 data write (cancel wait) IIC0 SCL0 6 7 8 9 1 2 3 Slave Wait after output of eighth clock FFH is written to IIC0 or WREL0 is set to 1 IIC0 SCL0 ACKE0 Transfer lines H Wait from slave SCL0 6 7 8 9 Wait from master 1 2 3 SDA0 D2 D1 D0 ACK D7 D6 D5 User's Manual U17397EJ4V0UD 465 CHAPTER 18 SERIAL INTERFACE IIC0 www..com Figure 18-18. Wait (2/2) (2) When master and slave devices both have a nine-clock wait (master transmits, slave receives, and ACKE0 = 1) Master IIC0 Master and slave both wait after output of ninth clock IIC0 data write (cancel wait) SCL0 6 7 8 9 1 2 3 Slave IIC0 FFH is written to IIC0 or WREL0 is set to 1 SCL0 H Wait from master and slave SCL0 6 7 8 9 ACKE0 Transfer lines Wait from slave 1 2 3 SDA0 D2 D1 D0 ACK D7 D6 D5 Generate according to previously set ACKE0 value Remark ACKE0: Bit 2 of IIC control register 0 (IICC0) WREL0: Bit 5 of IIC control register 0 (IICC0) A wait may be automatically generated depending on the setting of bit 3 (WTIM0) of IIC control register 0 (IICC0). Normally, the receiving side cancels the wait state when bit 5 (WREL0) of IICC0 is set to 1 or when FFH is written to IIC shift register 0 (IIC0), and the transmitting side cancels the wait state when data is written to IIC0. The master device can also cancel the wait state via either of the following methods. * By setting bit 1 (STT0) of IICC0 to 1 * By setting bit 0 (SPT0) of IICC0 to 1 466 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com 18.5.7 Canceling wait The I2C usually cancels a wait state by the following processing. * Writing data to IIC shift register 0 (IIC0) * Setting bit 5 (WREL0) of IIC control register 0 (IICC0) (canceling wait) * Setting bit 1 (STT0) of IIC0 register (generating start condition)Note * Setting bit 0 (SPT0) of IIC0 register (generating stop condition)Note Note Master only When the above wait canceling processing is executed, the I2C cancels the wait state and communication is resumed. To cancel a wait state and transmit data (including addresses), write the data to IIC0. To receive data after canceling a wait state, or to complete data transmission, set bit 5 (WREL0) of the IIC0 control register 0 (IICC0) to 1. To generate a restart condition after canceling a wait state, set bit 1 (STT0) of IICC0 to 1. To generate a stop condition after canceling a wait state, set bit 0 (SPT0) of IICC0 to 1. Execute the canceling processing only once for one wait state. If, for example, data is written to IIC0 after canceling a wait state by setting WREL0 to 1, an incorrect value may be output to SDA0 because the timing for changing the SDA0 line conflicts with the timing for writing IIC0. In addition to the above, communication is stopped if IICE0 is cleared to 0 when communication has been aborted, so that the wait state can be canceled. If the I2C bus has deadlocked due to noise, processing is saved from communication by setting bit 6 (LREL0) of IICC0, so that the wait state can be canceled. 18.5.8 Interrupt request (INTIIC0) generation timing and wait control The setting of bit 3 (WTIM0) of IIC control register 0 (IICC0) determines the timing by which INTIIC0 is generated and the corresponding wait control, as shown in Table 18-3. Table 18-3. INTIIC0 Generation Timing and Wait Control WTIM0 Address 0 1 9 9 Notes 1, 2 During Slave Device Operation Data Reception 8 9 Note 2 During Master Device Operation Address 9 9 Data Reception 8 9 Data Transmission 8 9 Data Transmission 8 9 Note 2 Notes 1, 2 Note 2 Note 2 Notes 1. The slave device's INTIIC0 signal and wait period occurs at the falling edge of the ninth clock only when there is a match with the address set to slave address register 0 (SVA0). At this point, ACK is generated regardless of the value set to IICC0's bit 2 (ACKE0). For a slave device that has received an extension code, INTIIC0 occurs at the falling edge of the eighth clock. However, if the address does not match after restart, INTIIC0 is generated at the falling edge of the 9th clock, but wait does not occur. 2. If the received address does not match the contents of slave address register 0 (SVA0) and extension code is not received, neither INTIIC0 nor a wait occurs. Remark The numbers in the table indicate the number of the serial clock's clock signals. Interrupt requests and wait control are both synchronized with the falling edge of these clock signals. User's Manual U17397EJ4V0UD 467 CHAPTER 18 SERIAL INTERFACE IIC0 www..com (1) During address transmission/reception * Slave device operation: Interrupt and wait timing are determined depending on the conditions described in Notes 1 and 2 above, regardless of the WTIM0 bit. * Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of the WTIM0 bit. (2) During data reception * Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit. (3) During data transmission * Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit. (4) Wait cancellation method The four wait cancellation methods are as follows. * Writing data to IIC shift register 0 (IIC0) * Setting bit 5 (WREL0) of IIC control register 0 (IICC0) (canceling wait) * Setting bit 1 (STT0) of IIC0 register (generating start condition)Note * Setting bit 0 (SPT0) of IIC0 register (generating stop condition) Note Master only. When an 8-clock wait has been selected (WTIM0 = 0), the presence/absence of ACK generation must be determined prior to wait cancellation. (5) Stop condition detection INTIIC0 is generated when a stop condition is detected (only when SPIE0 = 1). 18.5.9 Address match detection method In I2C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match can be detected automatically by hardware. An interrupt request (INTIIC0) occurs when a local address has been set to slave address register 0 (SVA0) and when the address set to SVA0 matches the slave address sent by the master device, or when an extension code has been received. 18.5.10 Error detection In I2C bus mode, the status of the serial data bus (SDA0) during data transmission is captured by IIC shift register 0 (IIC0) of the transmitting device, so the IIC0 data prior to transmission can be compared with the transmitted IIC0 data to enable detection of transmission errors. A transmission error is judged as having occurred when the compared data values do not match. Note 468 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com 18.5.11 Extension code (1) When the higher 4 bits of the receive address are either "0000" or "1111", the extension code reception flag (EXC0) is set to 1 for extension code reception and an interrupt request (INTIIC0) is issued at the falling edge of the eighth clock. The local address stored in slave address register 0 (SVA0) is not affected. (2) If "11110xx0" is set to SVA0 by a 10-bit address transfer and "11110xx0" is transferred from the master device, the results are as follows. Note that INTIIC0 occurs at the falling edge of the eighth clock. * Higher four bits of data match: EXC0 = 1 * Seven bits of data match: Remark COI0 = 1 EXC0: Bit 5 of IIC status register 0 (IICS0) COI0: Bit 4 of IIC status register 0 (IICS0) (3) Since the processing after the interrupt request occurs differs according to the data that follows the extension code, such processing is performed by software. If the extension code is received while a slave device is operating, then the slave device is participating in communication even if its address does not match. For example, after the extension code is received, if you do not wish to operate the target device as a slave device, set bit 6 (LREL0) of the IIC control register 0 (IICC0) to 1 to set the standby mode for the next communication operation. Table 18-4. Extension Code Bit Definitions Slave Address 0000 000 0000 000 0000 001 0000 010 1111 0XX R/W Bit 0 1 x x x General call address Start byte C-BUS address Address that is reserved for different bus format 10-bit slave address specification Description User's Manual U17397EJ4V0UD 469 CHAPTER 18 SERIAL INTERFACE IIC0 www..com 18.5.12 Arbitration When several master devices simultaneously generate a start condition (when STT0 is set to 1 before STD0 is set to 1), communication among the master devices is performed as the number of clocks are adjusted until the data differs. This kind of operation is called arbitration. When one of the master devices loses in arbitration, an arbitration loss flag (ALD0) in IIC status register 0 (IICS0) is set (1) via the timing by which the arbitration loss occurred, and the SCL0 and SDA0 lines are both set to high impedance, which releases the bus. The arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a stop condition is detected, etc.) and the ALD0 = 1 setting that has been made by software. For details of interrupt request timing, see 18.5.17 Timing of I2C interrupt request (INTIIC0) occurrence. Remark STD0: Bit 1 of IIC status register 0 (IICS0) STT0: Bit 1 of IIC control register 0 (IICC0) Figure 18-19. Arbitration Timing Example Master 1 SCL0 Hi-Z SDA0 Master 2 SCL0 Hi-Z Master 1 loses arbitration SDA0 Transfer lines SCL0 SDA0 470 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com Table 18-5. Status During Arbitration and Interrupt Request Generation Timing Status During Arbitration During address transmission Read/write data after address transmission During extension code transmission Read/write data after extension code transmission During data transmission During ACK transfer period after data transmission When restart condition is detected during data transfer When stop condition is detected during data transfer When data is at low level while attempting to generate a restart condition When stop condition is detected while attempting to generate a restart condition When data is at low level while attempting to generate a stop condition When SCL0 is at low level while attempting to generate a restart condition At falling edge of eighth or ninth clock following byte transfer Note 1 Interrupt Request Generation Timing At falling edge of eighth or ninth clock following byte transfer Note 1 When stop condition is generated (when SPIE0 = 1) Note 2 At falling edge of eighth or ninth clock following byte transfer Note 2 Note 1 When stop condition is generated (when SPIE0 = 1) Notes 1. When WTIM0 (bit 3 of IIC control register 0 (IICC0)) = 1, an interrupt request occurs at the falling edge of the ninth clock. When WTIM0 = 0 and the extension code's slave address is received, an interrupt request occurs at the falling edge of the eighth clock. 2. When there is a chance that arbitration will occur, set SPIE0 = 1 for master device operation. Remark SPIE0: Bit 4 of IIC control register 0 (IICC0) 18.5.13 Wakeup function The I2C bus slave function is a function that generates an interrupt request signal (INTIIC0) when a local address and extension code have been received. This function makes processing more efficient by preventing unnecessary INTIIC0 signal from occurring when addresses do not match. When a start condition is detected, wakeup standby mode is set. This wakeup standby mode is in effect while addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has generated a start condition) to a slave device. However, when a stop condition is detected, bit 4 (SPIE0) of IIC control register 0 (IICC0) is set regardless of the wakeup function, and this determines whether interrupt requests are enabled or disabled. User's Manual U17397EJ4V0UD 471 CHAPTER 18 SERIAL INTERFACE IIC0 www..com 18.5.14 Communication reservation (1) When communication reservation function is enabled (bit 0 (IICRSV) of IIC flag register 0 (IICF0) = 0) To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes under which the bus is not used. * When arbitration results in neither master nor slave operation * When an extension code is received and slave operation is disabled (ACK is not returned and the bus was released when bit 6 (LREL0) of IIC control register 0 (IICC0) was set to 1). If bit 1 (STT0) of IICC0 is set to 1 while the bus is not used (after a stop condition is detected), a start condition is automatically generated and wait state is set. If an address is written to IIC shift register 0 (IIC0) after bit 4 (SPIE0) of IICC0 was set to 1, and it was detected by generation of an interrupt request signal (INTIIC0) that the bus was released (detection of the stop condition), then the device automatically starts communication as the master. Data written to IIC0 before the stop condition is detected is invalid. When STT0 has been set to 1, the operation mode (as start condition or as communication reservation) is determined according to the bus status. * If the bus has been released ........................................ a start condition is generated * If the bus has not been released (standby mode)......... communication reservation Check whether the communication reservation operates or not by using MSTS0 (bit 7 of IIC status register 0 (IICS0)) after STT0 is set to 1 and the wait time elapses. The wait periods, which should be set via software, are listed in Table 18-6. Table 18-6. Wait Periods CLX0 0 0 0 0 0 0 0 0 1 1 1 SMC0 0 0 0 0 1 1 1 1 1 1 1 CL01 0 0 1 1 0 0 1 1 0 0 1 CL00 0 1 0 1 0 1 0 1 0 1 0 36 clocks 60 clocks 12 clocks 18 clocks 46 clocks 86 clocks 172 clocks 34 clocks 30 clocks Wait Period Figure 18-20 shows the communication reservation timing. 472 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com Figure 18-20. Communication Reservation Timing Program processing STT0 = 1 Write to IIC0 CommuniHardware processing cation reservation Set SPD0 and INTIIC0 Set STD0 SCL0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 SDA0 Generate by master device with bus mastership Remark IIC0: STT0: STD0: IIC shift register 0 Bit 1 of IIC control register 0 (IICC0) Bit 1 of IIC status register 0 (IICS0) SPD0: Bit 0 of IIC status register 0 (IICS0) Communication reservations are accepted via the following timing. After bit 1 (STD0) of IIC status register 0 (IICS0) is set to 1, a communication reservation can be made by setting bit 1 (STT0) of IIC control register 0 (IICC0) to 1 before a stop condition is detected. Figure 18-21. Timing for Accepting Communication Reservations SCL0 SDA0 STD0 SPD0 Standby mode Figure 18-22 shows the communication reservation protocol. User's Manual U17397EJ4V0UD 473 CHAPTER 18 SERIAL INTERFACE IIC0 www..com Figure 18-22. Communication Reservation Protocol DI SET1 STT0 Sets STT0 flag (communication reservation) Define communication reservation Defines that communication reservation is in effect (defines and sets user flag to any part of RAM) Wait Secures wait period set by software (see Table 18-6). (Communication reservation)Note Yes MSTS0 = 0? No Confirmation of communication reservation (Generate start condition) Cancel communication reservation Clear user flag MOV IIC0, #xxH IIC0 write operation EI Note The communication reservation operation executes a write to IIC shift register 0 (IIC0) when a stop condition interrupt request occurs. Remark STT0: IIC0: Bit 1 of IIC control register 0 (IICC0) IIC shift register 0 MSTS0: Bit 7 of IIC status register 0 (IICS0) (2) When communication reservation function is disabled (bit 0 (IICRSV) of IIC flag register 0 (IICF0) = 1) When bit 1 (STT0) of IIC control register 0 (IICC0) is set to 1 when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated. The following two statuses are included in the status where bus is not used. * When arbitration results in neither master nor slave operation * When an extension code is received and slave operation is disabled (ACK is not returned and the bus was released when bit 6 (LREL0) of IICC0 was set to 1) To confirm whether the start condition was generated or request was rejected, check STCF (bit 7 of IICF0). The time shown in Table 18-7 is required until STCF is set to 1 after setting STT0 = 1. Therefore, secure the time by software. 474 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com Table 18-7. Wait Periods CL01 0 0 1 1 CL00 0 1 0 1 Wait Period 6 clocks 6 clocks 12 clocks 3 clocks 18.5.15 Cautions (1) When STCEN (bit 1 of IIC flag register 0 (IICF0)) = 0 Immediately after I2C operation is enabled (IICE0 = 1), the bus communication status (IICBSY (bit 6 of IICF0) = 1) is recognized regardless of the actual bus status. When changing from a mode in which no stop condition has been detected to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication. When using multiple masters, it is not possible to perform master device communication when the bus has not been released (when a stop condition has not been detected). Use the following sequence for generating a stop condition. <1> Set IIC clock selection register 0 (IICCL0). <2> Set bit 7 (IICE0) of IIC control register 0 (IICC0) to 1. <3> Set bit 0 (SPT0) of IICC0 to 1. (2) When STCEN = 1 Immediately after I2C operation is enabled (IICE0 = 1), the bus released status (IICBSY = 0) is recognized regardless of the actual bus status. To generate the first start condition (STT0 (bit 1 of IIC control register 0 (IICC0)) = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. (3) If other I2C communications are already in progress If I2C operation is enabled and the device participates in communication already in progress when the SDA0 pin is low and the SCL0 pin is high, the macro of I2C recognizes that the SDA0 pin has gone low (detects a start condition). If the value on the bus at this time can be recognized as an extension code, ACK is returned, but this interferes with other I2C communications. To avoid this, start I2C in the following sequence. <1> Clear bit 4 (SPIE0) of IICC0 to 0 to disable generation of an interrupt request signal (INTIIC0) when the stop condition is detected. <2> Set bit 7 (IICE0) of IICC0 to 1 to enable the operation of I2C. <3> Wait for detection of the start condition. <4> Set bit 6 (LREL0) of IICC0 to 1 before ACK is returned (4 to 80 clocks after setting IICE0 to 1), to forcibly disable detection. (4) Determine the transfer clock frequency by using SMC0, CL01, CL00 (bits 3, 1, and 0 of IICL0), and CLX0 (bit 0 of IICX0) before enabling the operation (IICE0 = 1). To change the transfer clock frequency, clear IICE0 to 0 once. User's Manual U17397EJ4V0UD 475 CHAPTER 18 SERIAL INTERFACE IIC0 www..com (5) Setting STT0 and SPT0 (bits 1 and 0 of IICC0) again after they are set and before they are cleared to 0 is prohibited. (6) When transmission is reserved, set SPIE0 (bit 4 of IICL0) to 1 so that an interrupt request is generated when the stop condition is detected. Transfer is started when communication data is written to IIC0 after the interrupt request is generated. Unless the interrupt is generated when the stop condition is detected, the device stops in the wait state because the interrupt request is not generated when communication is started. However, it is not necessary to set SPIE0 to 1 when MSTS0 (bit 7 of IICS0) is detected by software. 18.5.16 Communication operations The following shows three operation procedures with the flowchart. (1) Master operation in single master system The flowchart when using the 78K0/KF2 as the master in a single master system is shown below. This flowchart is broadly divided into the initial settings and communication processing. Execute the initial settings at startup. If communication with the slave is required, prepare the communication and then execute communication processing. (2) Master operation in multimaster system In the I2C bus multimaster system, whether the bus is released or used cannot be judged by the I2C bus specifications when the bus takes part in a communication. Here, when data and clock are at a high level for a certain period (1 frame), the 78K0/KF2 takes part in a communication with bus released state. This flowchart is broadly divided into the initial settings, communication waiting, and communication processing. The processing when the 78K0/KF2 looses in arbitration and is specified as the slave is omitted here, and only the processing as the master is shown. Execute the initial settings at startup to take part in a communication. Then, wait for the communication request as the master or wait for the specification as the slave. The actual communication is performed in the communication processing, and it supports the transmission/reception with the slave and the arbitration with other masters. (3) Slave operation An example of when the 78K0/KF2 is used as the I2C bus slave is shown below. When used as the slave, operation is started by an interrupt. Execute the initial settings at startup, then wait for the INTIIC0 interrupt occurrence (communication waiting). When an INTIIC0 interrupt occurs, the communication status is judged and its result is passed as a flag over to the main processing. By checking the flags, necessary communication processing is performed. 476 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com (1) Master operation in single-master system Figure 18-23. Master Operation in Single-Master System START Initializing I2C busNote Setting port IICX0 0XH IICCL0 XXH SVA0 XXH IICF0 0XH Setting STCEN, IICRSV = 0 Sets each pin in the I2C mode (see 18.3 (7) Port mode register 6 (PM6)). Selects a transfer clock. Sets a local address. Sets a start condition. Initial setting IICC0 XXH ACKE0 = WTIM0 = SPIE0 = 1 IICE0 = 1 Yes STCEN = 1? No SPT0 = 1 Prepares for starting communication (generates a stop condition). INTIIC0 Interrupt occurs? Yes No Waits for detection of the stop condition. STT0 = 1 Prepares for starting communication (generates a start condition). Starts communication (specifies an address and transfer direction). Writing IIC0 INTIIC0 interrupt occurs? Yes No ACKD0 = 1? Yes TRC0 = 1? No Waits for detection of acknowledge. No ACKE0 = 1 WTIM0 = 0 Starts transmission. WREL0 = 1 Starts reception. Communication processing Yes Writing IIC0 INTIIC0 interrupt occurs? Yes No Waits for data transmission. INTIIC0 interrupt occurs? Yes No Waits for data reception. ACKD0 = 1? Yes No No Reading IIC0 End of transfer? End of transfer? Yes Yes ACKE0 = 0 WTIM0 = WREL0 = 1 No SPT0 = 1 END INTIIC0 interrupt occurs? Yes No Restart? Yes No Waits for detection of acknowledge. 2 Note Release (SCL0 and SDA0 pins = high level) the I C bus in conformance with the specifications of the product that is communicating. If EEPROM is outputting a low level to the SDA0 pin, for example, set the SCL0 pin in the output port mode, and output a clock pulse from the output port until the SDA0 pin is constantly at high level. Remark Conform to the specifications of the product that is communicating, with respect to the transmission and reception formats. User's Manual U17397EJ4V0UD 477 CHAPTER 18 SERIAL INTERFACE IIC0 www..com (2) Master operation in multi-master system Figure 18-24. Master Operation in Multi-Master System (1/3) START Setting port IICX0 0XH IICCL0 XXH SVA0 XXH IICF0 0XH Setting STCEN and IICRSV IICC0 XXH ACKE0 = WTIM0 = SPIE0 = 1 IICE0 = 1 Sets each pin in the I2C mode (see 18.3 (7) Port mode register 6 (PM6)). Selects a transfer clock. Sets a local address. Sets a start condition. Initial setting Checking bus statusNote Releases the bus for a specific period. Bus status is being checked. No INTIIC0 interrupt occurs? Yes No STCEN = 1? Yes No SPT0 = 1 Prepares for starting communication (generates a stop condition). INTIIC0 interrupt occurs? Yes SPD0 = 1? Yes No Waits for detection of the stop condition. Slave operation SPD0 = 1? Yes No Slave operation 1 * Waiting to be specified as a slave by other master * Waiting for a communication start request (depends on user program) Waits for a communication Master operation starts? No (No communication start request) SPIE0 = 0 Yes (Communication start request) SPIE0 = 1 INTIIC0 interrupt occurs? Yes No Waits for a communication request. IICRSV = 0? Yes A No Slave operation B Enables reserving Disables reserving communication. communication. Note Confirm that the bus is released (CLD0 bit = 1, DAD0 bit = 1) for a specific period (for example, for a period of one frame). If the SDA0 pin is constantly at low level, decide whether to release the I2C bus (SCL0 and SDA0 pins = high level) in conformance with the specifications of the product that is communicating. 478 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com Figure 18-24. Master Operation in Multi-Master System (2/3) A Enables reserving communication. STT0 = 1 Prepares for starting communication (generates a start condition). Secure wait time by software (see Table 18-6). Wait Communication processing MSTS0 = 1? Yes No INTIIC0 interrupt occurs? Yes No Wait state after stop condition was detected and start condition was generated by the communication reservation function. No Waits for bus release (communication being reserved). EXC0 = 1 or COI0 =1? Yes Slave operation C B Disables reserving communication. IICBSY = 0? Yes No D Communication processing STT0 = 1 Prepares for starting communication (generates a start condition). Secure wait time by software (see Table 18-7). Wait STCF = 0? Yes No INTIIC0 interrupt occurs? Yes No Waits for bus release C EXC0 = 1 or COI0 =1? Yes Slave operation D No Detects a stop condition. User's Manual U17397EJ4V0UD 479 CHAPTER 18 SERIAL INTERFACE IIC0 www..com Figure 18-24. Master Operation in Multi-Master System (3/3) C Starts communication (specifies an address and transfer direction). Writing IIC0 INTIIC0 interrupt occurs? Yes MSTS0 = 1? Yes No ACKD0 = 1? Yes TRC0 = 1? Yes Communication processing No Waits for detection of ACK. No 2 No ACKE0 = 1 WTIM0 = 0 WTIM0 = 1 WREL0 = 1 Writing IIC0 Starts transmission. INTIIC0 interrupt occurs? INTIIC0 interrupt occurs? Yes MSTS0 = 1? Yes ACKD0 = 1? Yes Yes No Transfer end? Yes INTIIC0 interrupt occurs? Yes SPT0 = 1 MSTS0 = 1? STT0 = 1 END Yes C No 2 No Waits for detection of ACK. WTIM0 = WREL0 = 1 ACKE0 = 0 No Transfer end? No No Yes 2 Reading IIC0 2 No Waits for data transmission. Yes MSTS0 = 1? No No Waits for data reception. Starts reception. Restart? Yes No Communication processing 2 EXC0 = 1 or COI0 = 1? Yes Slave operation No 1 Does not participate in communication. Remarks 1. Conform to the specifications of the product that is communicating, with respect to the transmission and reception formats. 2. To use the device as a master in a multi-master system, read the MSTS0 bit each time interrupt INTIIC0 has occurred to check the arbitration result. 3. To use the device as a slave in a multi-master system, check the status by using the IICS0 and IICF0 registers each time interrupt INTIIC0 has occurred, and determine the processing to be performed next. 480 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com (3) Slave operation The processing procedure of the slave operation is as follows. Basically, the slave operation is event-driven. Therefore, processing by the INTIIC0 interrupt (processing that must substantially change the operation status such as detection of a stop condition during communication) is necessary. In the following explanation, it is assumed that the extension code is not supported for data communication. It is also assumed that the INTIIC0 interrupt servicing only performs status transition processing, and that actual data communication is performed by the main processing. INTIIC0 Interrupt servicing Setting IIC0 Data Flag Main processing Setting Therefore, data communication processing is performed by preparing the following three flags and passing them to the main processing instead of INTIIC0. <1> Communication mode flag This flag indicates the following two communication statuses. * Clear mode: Status in which data communication is not performed to stop condition detection, no detection of ACK from master, address mismatch) <2> Ready flag This flag indicates that data communication is enabled. Its function is the same as the INTIIC0 interrupt for ordinary data communication. This flag is set by interrupt servicing and cleared by the main processing. Clear this flag by interrupt servicing when communication is started. However, the ready flag is not set by interrupt servicing when the first data is transmitted. Therefore, the first data is transmitted without the flag being cleared (an address match is interpreted as a request for the next data). <3> Communication direction flag This flag indicates the direction of communication. Its value is the same as TRC0. * Communication mode: Status in which data communication is performed (from valid address detection User's Manual U17397EJ4V0UD 481 CHAPTER 18 SERIAL INTERFACE IIC0 www..com The main processing of the slave operation is explained next. Start serial interface IIC0 and wait until communication is enabled. When communication is enabled, execute communication by using the communication mode flag and ready flag (processing of the stop condition and start condition is performed by an interrupt. Here, check the status by using the flags). The transmission operation is repeated until the master no longer returns ACK. If ACK is not returned from the master, communication is completed. For reception, the necessary amount of data is received. When communication is completed, ACK is not returned as the next data. After that, the master generates a stop condition or restart condition. Exit from the communication status occurs in this way. Figure 18-25. Slave Operation Flowchart (1) START Setting port Sets each pin to the I2C mode (see 18.3 (7) Port mode register 6 (PM6)). IICX0 0XH IICCL0 XXH Initial setting Selects a transfer clock. SVA0 XXH Sets a local address. IICF0 0XH Setting IICRSV IICC0 XXH ACKE0 = WTIM0 = 1 SPIE0 = 0, IICE0 = 1 Sets a start condition. No Communication mode flag = 1? Yes Communication direction flag = 1? Yes WREL0 = 1 Writing IIC0 Starts transmission. Communication mode flag = 1? Communication mode flag = 1? Yes Yes Communication direction flag = 1? Yes No No Ready flag = 1? Yes Yes Reading IIC0 Clearing ready flag Clearing ready flag Ready flag = 1? No No No Starts reception. No Communication processing No Communication direction flag = 1? Yes Yes ACKD0 = 1? No Clearing communication mode flag WREL0 = 1 Remark Conform to the specifications of the product that is in communication, regarding the transmission and reception formats. 482 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com An example of the processing procedure of the slave with the INTIIC0 interrupt is explained below (processing is performed assuming that no extension code is used). The INTIIC0 interrupt checks the status, and the following operations are performed. <1> Communication is stopped if the stop condition is issued. <2> If the start condition is issued, the address is checked and communication is completed if the address does not match. If the address matches, the communication mode is set, wait is cancelled, and processing returns from the interrupt (the ready flag is cleared). <3> For data transmit/receive, only the ready flag is set. Processing returns from the interrupt with the I2C bus remaining in the wait state. Remark <1> to <3> above correspond to <1> to <3> in Figure 18-26 Slave Operation Flowchart (2). Figure 18-26. Slave Operation Flowchart (2) INTIIC0 generated Yes SPD0 = 1? No <1> Yes STD0 = 1? No <3> Set ready flag <2> No COI0 = 1? Yes Communication direction flag TRC0 Set communication mode flag Clear ready flag Clear communication direction flag, ready flag, and communication mode flag Interrupt servicing completed User's Manual U17397EJ4V0UD 483 CHAPTER 18 SERIAL INTERFACE IIC0 www..com 18.5.17 Timing of I2C interrupt request (INTIIC0) occurrence The timing of transmitting or receiving data and generation of interrupt request signal INTIIC0, and the value of the IICS0 register when the INTIIC0 signal is generated are shown below. Remark ST: R/W: ACK: D7 to D0: SP: Start condition Transfer direction specification Acknowledge Data Stop condition AD6 to AD0: Address 484 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com (1) Master device operation (a) Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception) (i) When WTIM0 = 0 SPT0 = 1 ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 D7 to D0 ACK 3 SP 4 5 1: IICS0 = 1000x110B 2: IICS0 = 1000x000B 3: IICS0 = 1000x000B (Sets WTIM0 to 1)Note 4: IICS0 = 1000xx00B (Sets SPT0 to 1)Note 5: IICS0 = 00000001B Note To generate a stop condition, set WTIM0 to 1 and change the timing for generating the INTIIC0 interrupt request signal. Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 SPT0 = 1 ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 D7 to D0 ACK SP 3 4 1: IICS0 = 1000x110B 2: IICS0 = 1000x100B 3: IICS0 = 1000xx00B (Sets SPT0 to 1) 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care User's Manual U17397EJ4V0UD 485 CHAPTER 18 SERIAL INTERFACE IIC0 www..com (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) (i) When WTIM0 = 0 STT0 = 1 ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 ST 3 AD6 to AD0 R/W ACK 4 D7 to D0 SPT0 = 1 ACK 5 SP 6 7 1: IICS0 = 1000x110B 2: IICS0 = 1000x000B (Sets WTIM0 to 1)Note 1 3: IICS0 = 1000xx00B (Clears WTIM0 to 0Note 2, sets STT0 to 1) 4: IICS0 = 1000x110B 5: IICS0 = 1000x000B (Sets WTIM0 to 1)Note 3 6: IICS0 = 1000xx00B (Sets SPT0 to 1) 7: IICS0 = 00000001B Notes 1. To generate a start condition, set WTIM0 to 1 and change the timing for generating the INTIIC0 interrupt request signal. 2. Clear WTIM0 to 0 to restore the original setting. 3. To generate a stop condition, set WTIM0 to 1 and change the timing for generating the INTIIC0 interrupt request signal. Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 STT0 = 1 ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK ST 2 AD6 to AD0 R/W ACK 3 D7 to D0 SPT0 = 1 ACK SP 4 5 1: IICS0 = 1000x110B 2: IICS0 = 1000xx00B (Sets STT0 to 1) 3: IICS0 = 1000x110B 4: IICS0 = 1000xx00B (Sets SPT0 to 1) 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care 486 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com (c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) (i) When WTIM0 = 0 SPT0 = 1 ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 D7 to D0 ACK 3 SP 4 5 1: IICS0 = 1010x110B 2: IICS0 = 1010x000B 3: IICS0 = 1010x000B (Sets WTIM0 to 1)Note 4: IICS0 = 1010xx00B (Sets SPT0 to 1) 5: IICS0 = 00000001B Note To generate a stop condition, set WTIM0 to 1 and change the timing for generating the INTIIC0 interrupt request signal. Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 SPT0 = 1 ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 D7 to D0 ACK SP 3 4 1: IICS0 = 1010x110B 2: IICS0 = 1010x100B 3: IICS0 = 1010xx00B (Sets SPT0 to 1) 4: IICS0 = 00001001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care User's Manual U17397EJ4V0UD 487 CHAPTER 18 SERIAL INTERFACE IIC0 www..com (2) Slave device operation (slave address data reception) (a) Start ~ Address ~ Data ~ Data ~ Stop (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 D7 to D0 ACK 3 SP 4 1: IICS0 = 0001x110B 2: IICS0 = 0001x000B 3: IICS0 = 0001x000B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 D7 to D0 ACK SP 3 4 1: IICS0 = 0001x110B 2: IICS0 = 0001x100B 3: IICS0 = 0001xx00B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care 488 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, matches with SVA0) ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 ST AD6 to AD0 R/W ACK 3 D7 to D0 ACK 4 SP 5 1: IICS0 = 0001x110B 2: IICS0 = 0001x000B 3: IICS0 = 0001x110B 4: IICS0 = 0001x000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 (after restart, matches with SVA0) ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK ST 2 AD6 to AD0 R/W ACK 3 D7 to D0 ACK SP 4 5 1: IICS0 = 0001x110B 2: IICS0 = 0001xx00B 3: IICS0 = 0001x110B 4: IICS0 = 0001xx00B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care User's Manual U17397EJ4V0UD 489 CHAPTER 18 SERIAL INTERFACE IIC0 www..com (c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= extension code)) ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 ST AD6 to AD0 R/W ACK 3 D7 to D0 ACK 4 SP 5 1: IICS0 = 0001x110B 2: IICS0 = 0001x000B 3: IICS0 = 0010x010B 4: IICS0 = 0010x000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 (after restart, does not match address (= extension code)) ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK ST 2 AD6 to AD0 R/W ACK 3 4 D7 to D0 ACK SP 5 6 1: IICS0 = 0001x110B 2: IICS0 = 0001xx00B 3: IICS0 = 0010x010B 4: IICS0 = 0010x110B 5: IICS0 = 0010xx00B 6: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care 490 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com (d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= not extension code)) ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 ST AD6 to AD0 R/W ACK 3 D7 to D0 ACK SP 4 1: IICS0 = 0001x110B 2: IICS0 = 0001x000B 3: IICS0 = 00000110B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 (after restart, does not match address (= not extension code)) ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK ST 2 AD6 to AD0 R/W ACK 3 D7 to D0 ACK SP 4 1: IICS0 = 0001x110B 2: IICS0 = 0001xx00B 3: IICS0 = 00000110B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care User's Manual U17397EJ4V0UD 491 CHAPTER 18 SERIAL INTERFACE IIC0 www..com (3) Slave device operation (when receiving extension code) The device is always participating in communication when it receives an extension code. (a) Start ~ Code ~ Data ~ Data ~ Stop (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 D7 to D0 ACK 3 SP 4 1: IICS0 = 0010x010B 2: IICS0 = 0010x000B 3: IICS0 = 0010x000B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK 1 2 D7 to D0 ACK 3 D7 to D0 ACK SP 4 5 1: IICS0 = 0010x010B 2: IICS0 = 0010x110B 3: IICS0 = 0010x100B 4: IICS0 = 0010xx00B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care 492 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com (b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, matches SVA0) ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 ST AD6 to AD0 R/W ACK 3 D7 to D0 ACK 4 SP 5 1: IICS0 = 0010x010B 2: IICS0 = 0010x000B 3: IICS0 = 0001x110B 4: IICS0 = 0001x000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 (after restart, matches SVA0) ST AD6 to AD0 R/W ACK 1 2 D7 to D0 ACK ST 3 AD6 to AD0 R/W ACK 4 D7 to D0 ACK SP 5 6 1: IICS0 = 0010x010B 2: IICS0 = 0010x110B 3: IICS0 = 0010xx00B 4: IICS0 = 0001x110B 5: IICS0 = 0001xx00B 6: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care User's Manual U17397EJ4V0UD 493 CHAPTER 18 SERIAL INTERFACE IIC0 www..com (c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, extension code reception) ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 ST AD6 to AD0 R/W ACK 3 D7 to D0 ACK 4 SP 5 1: IICS0 = 0010x010B 2: IICS0 = 0010x000B 3: IICS0 = 0010x010B 4: IICS0 = 0010x000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 (after restart, extension code reception) ST AD6 to AD0 R/W ACK 1 2 D7 to D0 ACK ST 3 AD6 to AD0 R/W ACK 4 5 D7 to D0 ACK SP 6 7 1: IICS0 = 0010x010B 2: IICS0 = 0010x110B 3: IICS0 = 0010xx00B 4: IICS0 = 0010x010B 5: IICS0 = 0010x110B 6: IICS0 = 0010xx00B 7: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care 494 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com (d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= not extension code)) ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 ST AD6 to AD0 R/W ACK 3 D7 to D0 ACK SP 4 1: IICS0 = 00100010B 2: IICS0 = 00100000B 3: IICS0 = 00000110B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 (after restart, does not match address (= not extension code)) ST AD6 to AD0 R/W ACK 1 2 D7 to D0 ACK ST 3 AD6 to AD0 R/W ACK 4 D7 to D0 ACK SP 5 1: IICS0 = 00100010B 2: IICS0 = 00100110B 3: IICS0 = 00100x00B 4: IICS0 = 00000110B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care User's Manual U17397EJ4V0UD 495 CHAPTER 18 SERIAL INTERFACE IIC0 www..com (4) Operation without communication (a) Start ~ Code ~ Data ~ Data ~ Stop ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 ACK SP 1 1: IICS0 = 00000001B Remark : Generated only when SPIE0 = 1 (5) Arbitration loss operation (operation as slave after arbitration loss) When the device is used as a master in a multi-master system, read the MSTS0 bit each time interrupt request signal INTIIC0 has occurred to check the arbitration result. (a) When arbitration loss occurs during transmission of slave address data (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 D7 to D0 ACK 3 SP 4 1: IICS0 = 0101x110B 2: IICS0 = 0001x000B 3: IICS0 = 0001x000B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care 496 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 D7 to D0 ACK SP 3 4 1: IICS0 = 0101x110B 2: IICS0 = 0001x100B 3: IICS0 = 0001xx00B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (b) When arbitration loss occurs during transmission of extension code (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 D7 to D0 ACK 3 SP 4 1: IICS0 = 0110x010B 2: IICS0 = 0010x000B 3: IICS0 = 0010x000B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care User's Manual U17397EJ4V0UD 497 CHAPTER 18 SERIAL INTERFACE IIC0 www..com (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK 1 2 D7 to D0 ACK 3 D7 to D0 ACK SP 4 5 1: IICS0 = 0110x010B 2: IICS0 = 0010x110B 3: IICS0 = 0010x100B 4: IICS0 = 0010xx00B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (6) Operation when arbitration loss occurs (no communication after arbitration loss) When the device is used as a master in a multi-master system, read the MSTS0 bit each time interrupt request signal INTIIC0 has occurred to check the arbitration result. (a) When arbitration loss occurs during transmission of slave address data (when WTIM0 = 1) ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK D7 to D0 ACK SP 2 1: IICS0 = 01000110B 2: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 498 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com (b) When arbitration loss occurs during transmission of extension code ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK D7 to D0 ACK SP 2 1: IICS0 = 0110x010B Sets LREL0 = 1 by software 2: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (c) When arbitration loss occurs during transmission of data (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 D7 to D0 ACK SP 3 1: IICS0 = 10001110B 2: IICS0 = 01000000B 3: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 User's Manual U17397EJ4V0UD 499 CHAPTER 18 SERIAL INTERFACE IIC0 www..com (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 D7 to D0 ACK SP 3 1: IICS0 = 10001110B 2: IICS0 = 01000100B 3: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 (d) When loss occurs due to restart condition during data transfer (i) Not extension code (Example: unmatches with SVA0) ST AD6 to AD0 R/W ACK 1 D7 to Dn ST AD6 to AD0 R/W ACK 2 D7 to D0 ACK SP 3 1: IICS0 = 1000x110B 2: IICS0 = 01000110B 3: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care n = 6 to 0 500 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com (ii) Extension code ST AD6 to AD0 R/W ACK 1 D7 to Dn ST AD6 to AD0 R/W ACK 2 D7 to D0 ACK SP 3 1: IICS0 = 1000x110B 2: IICS0 = 01100010B Sets LREL0 = 1 by software 3: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care n = 6 to 0 (e) When loss occurs due to stop condition during data transfer ST AD6 to AD0 R/W ACK 1 D7 to Dn SP 2 1: IICS0 = 10000110B 2: IICS0 = 01000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care n = 6 to 0 User's Manual U17397EJ4V0UD 501 CHAPTER 18 SERIAL INTERFACE IIC0 www..com (f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1 ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 3 D7 to D0 ACK 4 D7 to D0 ACK SP 5 1: IICS0 = 1000x110B 2: IICS0 = 1000x000B (Sets WTIM0 to 1) 3: IICS0 = 1000x100B (Clears WTIM0 to 0) 4: IICS0 = 01000000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 STT0 = 1 ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 D7 to D0 ACK 3 D7 to D0 ACK SP 4 1: IICS0 = 1000x110B 2: IICS0 = 1000x100B (Sets STT0 to 1) 3: IICS0 = 01000100B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care 502 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com (g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1 ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 SP 3 4 1: IICS0 = 1000x110B 2: IICS0 = 1000x000B (Sets WTIM0 to 1) 3: IICS0 = 1000xx00B (Sets STT0 to 1) 4: IICS0 = 01000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 STT0 = 1 ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK SP 2 3 1: IICS0 = 1000x110B 2: IICS0 = 1000xx00B (Sets STT0 to 1) 3: IICS0 = 01000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care User's Manual U17397EJ4V0UD 503 CHAPTER 18 SERIAL INTERFACE IIC0 www..com (h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition (i) When WTIM0 = 0 SPT0 = 1 ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 3 D7 to D0 ACK 4 D7 to D0 ACK SP 5 1: IICS0 = 1000x110B 2: IICS0 = 1000x000B (Sets WTIM0 to 1) 3: IICS0 = 1000x100B (Clears WTIM0 to 0) 4: IICS0 = 01000100B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 SPT0 = 1 ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 D7 to D0 ACK 3 D7 to D0 ACK SP 4 1: IICS0 = 1000x110B 2: IICS0 = 1000x100B (Sets SPT0 to 1) 3: IICS0 = 01000100B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care 504 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com 18.6 Timing Charts When using the I2C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRC0 bit (bit 3 of IIC status register 0 (IICS0)), which specifies the data transfer direction, and then starts serial communication with the slave device. Figures 18-27 and 18-28 show timing charts of the data communication. IIC shift register 0 (IIC0)'s shift operation is synchronized with the falling edge of the serial clock (SCL0). The transmit data is transferred to the SO0 latch and is output (MSB first) via the SDA0 pin. Data input via the SDA0 pin is captured into IIC0 at the rising edge of SCL0. User's Manual U17397EJ4V0UD 505 CHAPTER 18 SERIAL INTERFACE IIC0 www..com Figure 18-27. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (1) Start condition ~ address Processing by master device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 H L L H H IIC0 address IIC0 data Transmit Transfer lines SCL0 SDA0 1 2 3 4 5 6 7 8 W 9 ACK 1 D7 2 D6 3 D5 4 D4 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Start condition Processing by slave device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 H H L L L IIC0 FFH Note Note (When EXC0 = 1) TRC0 L Receive Note To cancel slave wait, write "FFH" to IIC0 or set WREL0. 506 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com Figure 18-27. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (2) Data Processing by master device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 H L L H H H L L L IIC0 data IIC0 data Transmit Transfer lines SCL0 SDA0 8 D0 9 ACK 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 D5 Processing by slave device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 L L L H H L L L IIC0 FFH Note IIC0 FFH Note Note Note Receive Note To cancel slave wait, write "FFH" to IIC0 or set WREL0. User's Manual U17397EJ4V0UD 507 CHAPTER 18 SERIAL INTERFACE IIC0 www..com Figure 18-27. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (3) Stop condition Processing by master device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 L H H IIC0 data IIC0 address (When SPIE0 = 1) TRC0 H Transmit Transfer lines SCL0 SDA0 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 ACK 1 2 AD6 AD5 Processing by slave device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 H H L L L Stop condition IIC0 FFH Note Start condition IIC0 FFH Note Note Note (When SPIE0 = 1) TRC0 L Receive Note To cancel slave wait, write "FFH" to IIC0 or set WREL0. 508 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com Figure 18-28. Example of Slave to Master Communication (When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/3) (1) Start condition ~ address Processing by master device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 L L H IIC0 address IIC0 FFH Note Note Transfer lines SCL0 SDA0 1 2 3 4 5 6 7 8 R 9 ACK 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Start condition Processing by slave device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 H H L L L L IIC0 data Note To cancel master wait, write "FFH" to IIC0 or set WREL0. User's Manual U17397EJ4V0UD 509 CHAPTER 18 SERIAL INTERFACE IIC0 www..com Figure 18-28. Example of Slave to Master Communication (When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/3) (2) Data Processing by master device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 L Receive L L L H H L L IIC0 FFH Note IIC0 FFH Note Note Note Transfer lines SCL0 SDA0 8 D0 9 ACK 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 D5 Processing by slave device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 H Transmit L L H H L L L L IIC0 data IIC0 data Note To cancel master wait, write "FFH" to IIC0 or set WREL0. 510 User's Manual U17397EJ4V0UD CHAPTER 18 SERIAL INTERFACE IIC0 www..com Figure 18-28. Example of Slave to Master Communication (When 8-Clock and 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/3) (3) Stop condition Processing by master device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 (When SPIE0 = 1) Note IIC0 FFH Note IIC0 address TRC0 Transfer lines SCL0 SDA0 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 NACK Stop condition 1 AD6 Start condition Processing by slave device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 (When SPIE0 = 1) IIC0 data H H L L L TRC0 Note To cancel master wait, write "FFH" to IIC0 or set WREL0. User's Manual U17397EJ4V0UD 511 www..com CHAPTER 19 MULTIPLIER/DIVIDER 19.1 Functions of Multiplier/Divider The multiplier/divider has the following functions. * 16 bits x 16 bits = 32 bits (multiplication) * 32 bits / 16 bits = 32 bits, 16-bit remainder (division) 19.2 Configuration of Multiplier/Divider The multiplier/divider includes the following hardware. Table 19-1. Configuration of Multiplier/Divider Item Registers Configuration Remainder data register 0 (SDR0) Multiplication/division data registers A0 (MDA0H, MDA0L) Multiplication/division data registers B0 (MDB0) Control register Multiplier/divider control register 0 (DMUC0) Figure 19-1 shows the block diagram of the multiplier/divider. 512 User's Manual U17397EJ4V0UD Figure 19-1. Block Diagram of Multiplier/Divider Internal bus Multiplier/divider control register 0 (DMUC0) Multiplication/division data register B0 (MDB0 (MDB0H + MDB0L) Remainder data register 0 (SDR0 (SDR0H + SDR0L) Multiplication/division data register A0 (MDA0H (MDA0HH + MDA0HL) + MDA0L (MDA0LH + MDA0LL) ) MDA000 DMUSEL0 DMUE Start INTDMU Clear CHAPTER 19 MULTIPLIER/DIVIDER Controller User's Manual U17397EJ4V0UD Controller 6-bit counter fPRS 17-bit adder Controller www..com 513 CHAPTER 19 MULTIPLIER/DIVIDER www..com (1) Remainder data register 0 (SDR0) SDR0 is a 16-bit register that stores a remainder. This register stores 0 in the multiplication mode and the remainder of an operation result in the division mode. SDR0 can be read by an 8-bit or 16-bit memory manipulation instruction. Reset signal generation clears SDR0 to 0000H. Figure 19-2. Format of Remainder Data Register 0 (SDR0) Address: FF60H, FF61H Symbol After reset: 0000H FF61H (SDR0H) R FF60H (SDR0L) SDR0 SDR 015 SDR 014 SDR 013 SDR 012 SDR 011 SDR 010 SDR 009 SDR 008 SDR 007 SDR 006 SDR 005 SDR 004 SDR 003 SDR 002 SDR 001 SDR 000 Cautions 1. The value read from SDR0 during operation processing (while bit 7 (DMUE) of multiplier/divider control register 0 (DMUC0) is 1) is not guaranteed. 2. SDR0 is reset when the operation is started (when DMUE is set to 1). (2) Multiplication/division data register A0 (MDA0H, MDA0L) MDA0 is a 32-bit register that sets a 16-bit multiplier A in the multiplication mode and a 32-bit dividend in the division mode, and stores the 32-bit result of the operation (higher 16 bits: MDA0H, lower 16 bits: MDA0L). Figure 19-3. Format of Multiplication/Division Data Register A0 (MDA0H, MDA0L) Address: FF62H, FF63H, FF64H, FF65H Symbol After reset: 0000H, 0000H R/W FF64H (MDA0HL) FF65H (MDA0HH) MDA0H MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA 031 030 029 028 027 026 025 024 023 022 021 020 019 018 017 016 Symbol FF63H (MDA0LH) FF62H (MDA0LL) MDA0L MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA 015 014 013 012 011 010 009 008 007 006 005 004 003 002 001 000 Cautions 1. MDA0H is cleared to 0 when an operation is started in the multiplication mode (when multiplier/divider control register 0 (DMUC0) is set to 81H). 2. Do not change the value of MDA0 during operation processing (while bit 7 (DMUE) of multiplier/divider control register 0 (DMUC0) is 1). executed, but the result is undefined. 3. The value read from MDA0 during operation processing (while DMUE is 1) is not guaranteed. Even in this case, the operation is 514 User's Manual U17397EJ4V0UD CHAPTER 19 MULTIPLIER/DIVIDER www..com The functions of MDA0 when an operation is executed are shown in the table below. Table 19-2. Functions of MDA0 During Operation Execution DMUSEL0 0 1 Operation Mode Division mode Multiplication mode Dividend Higher 16 bits: 0, Lower 16 bits: Multiplier A Setting Operation Result Division result (quotient) Multiplication result (product) The register configuration differs between when multiplication is executed and when division is executed, as follows. * Register configuration during multiplication Address: FF66H, FF67H Symbol After reset: 0000H FF67H (MDB0H) R/W FF66H (MDB0L) MDB0 MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB 015 014 013 012 011 010 009 008 007 006 005 004 003 002 001 000 Cautions 1. Do not change the value of MDB0 during operation processing (while bit 7 (DMUE) of multiplier/divider control register 0 (DMUC0) is 1). executed, but the result is undefined. 2. Do not clear MDB0 to 0000H in the division mode. If set, undefined operation results are stored in MDA0 and SDR0. Even in this case, the operation is User's Manual U17397EJ4V0UD 515 CHAPTER 19 MULTIPLIER/DIVIDER www..com 19.3 Register Controlling Multiplier/Divider The multiplier/divider is controlled by multiplier/divider control register 0 (DMUC0). (1) Multiplier/divider control register 0 (DMUC0) DMUC0 is an 8-bit register that controls the operation of the multiplier/divider. DMUC0 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears DMUC0 to 00H. Figure 19-5. Format of Multiplier/Divider Control Register 0 (DMUC0) Address: FF68H Symbol DMUC0 After reset: 00H <7> DMUE DMUENote 0 1 DMUSEL0 0 1 Division mode Multiplication mode Stops operation Starts operation Operation mode (multiplication/division) selection 6 0 R/W 5 0 4 0 3 0 Operation start/stop 2 0 1 0 0 DMUSEL0 Note When DMUE is set to 1, the operation is started. DMUE is automatically cleared to 0 after the operation is complete. Cautions 1. If DMUE is cleared to 0 during operation processing (when DMUE is 1), the operation result is not guaranteed. If the operation is completed while the clearing instruction is being executed, the operation result is guaranteed, provided that the interrupt flag is set. 2. Do not change the value of DMUSEL0 during operation processing (while DMUE is 1). If it is changed, undefined operation results are stored in multiplication/division data register A0 (MDA0) and remainder data register 0 (SDR0). 3. If DMUE is cleared to 0 during operation processing (while DMUE is 1), the operation processing is stopped. To execute the operation again, set multiplication/division data register A0 (MDA0), multiplication/division data register B0 (MDB0), and multiplier/divider control register 0 (DMUC0), and start the operation (by setting DMUE to 1). 516 User's Manual U17397EJ4V0UD CHAPTER 19 MULTIPLIER/DIVIDER www..com 19.4 Operations of Multiplier/Divider 19.4.1 Multiplication operation * Initial setting 1. Set operation data to multiplication/division data register A0L (MDA0L) and multiplication/division data register B0 (MDB0). 2. Set bits 0 (DMUSEL0) and 7 (DMUE) of multiplier/divider control register 0 (DMUC0) to 1. Operation will start. * During operation 3. The operation will be completed when 16 peripheral hardware clocks (fPRS) have been issued after the start of the operation (intermediate data is stored in the MDA0L and MDA0H registers during operation, and therefore the read values of these registers are not guaranteed). * End of operation 4. The operation result data is stored in the MDA0L and MDA0H registers. 5. DMUE is cleared to 0 (end of operation). 6. After the operation, an interrupt request signal (INTDMU) is generated. * Next operation 7. To execute multiplication next, start from the initial setting in 19.4.1 Multiplication operation. 8. To execute division next, start from the initial setting in 19.4.2 Division operation. User's Manual U17397EJ4V0UD 517 518 fPRS DMUE DMUSEL0 Internal clock User's Manual U17397EJ4V0UD Figure 19-6. Timing Chart of Multiplication Operation (00DAH x 0093H) CHAPTER 19 MULTIPLIER/DIVIDER Counter SDR0 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 0 XXXX XXXX XXXX XXXX 00DA 0000 0000 00DA 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0049 0024 005B 0077 003B 0067 007D 003E 001F 000F 0007 0003 0001 0000 0000 006D 8036 C01B E00D 7006 B803 5C01 2E00 9700 4B80 A5C0 D2E0 E970 F4B8 FA5C 7D2E MDA0 MDB0 XXXX 0093 INTDMU www..com CHAPTER 19 MULTIPLIER/DIVIDER www..com 19.4.2 Division operation * Initial setting 1. Set operation data to multiplication/division data register A0 (MDA0L and MDA0H) and multiplication/division data register B0 (MDB0). 2. Set bits 0 (DMUSEL0) and 7 (DMUE) of multiplier/divider control register 0 (DMUC0) to 0 and 1, respectively. Operation will start. * During operation 3. The operation will be completed when 32 peripheral hardware clocks (fPRS) have been issued after the start of the operation (intermediate data is stored in the MDA0L and MDA0H registers and remainder data register 0 (SDR0) during operation, and therefore the read values of these registers are not guaranteed). * End of operation 4. The result data is stored in the MDA0L, MDA0H, and SDR0 registers. 5. DMUE is cleared to 0 (end of operation). 6. After the operation, an interrupt request signal (INTDMU) is generated. * Next operation 7. To execute multiplication next, start from the initial setting in 19.4.1 Multiplication operation. 8. To execute division next, start from the initial setting in 19.4.2 Division operation. User's Manual U17397EJ4V0UD 519 520 fPRS DMUE DMUSEL0 "0" Internal clock User's Manual U17397EJ4V0UD Figure 19-7. Timing Chart of Division Operation (DCBA2586H / 0018H) CHAPTER 19 MULTIPLIER/DIVIDER Counter SDR0 0 1 2 3 4 5 6 7 8 19 1A 1B 1C 1D 1E 1F 20 0 XXXX XXXX XXXX DCBA 2586 0000 0001 0003 0006 000D 0003 0007 000E 0004 B974 4B0C 72E8 9618 E5D1 CBA2 2C30 5860 9744 B0C1 2E89 6182 5D12 C304 BA25 8609 000B 0016 0014 0010 0008 0011 000B 0016 0C12 64D8 1824 C9B0 3049 9361 6093 26C3 C126 4D87 824C 9B0E 0499 361D MDA0 MDB0 0932 6C3A XXXX 0018 INTDMU www..com www..com CHAPTER 20 INTERRUPT FUNCTIONS 20.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Maskable interrupts These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (PR0L, PR0H, PR1L, PR1H). Multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated. If two or more interrupt requests, each having the same priority, are simultaneously generated, then they are processed according to the priority of vectored interrupt servicing. For the priority order, see Table 20-1. A standby release signal is generated and STOP and HALT modes are released. External interrupt requests and internal interrupt requests are provided as maskable interrupts. External: 9, internal: 20 (2) Software interrupt This is a vectored interrupt generated by executing the BRK instruction. It is acknowledged even when interrupts are disabled. The software interrupt does not undergo interrupt priority control. 20.2 Interrupt Sources and Configuration The 78K0/KF2 has a total of 30 interrupt sources including maskable interrupts and software interrupts. In addition, they also have up to four reset sources (see Table 20-1). User's Manual U17397EJ4V0UD 521 CHAPTER 20 INTERRUPT FUNCTIONS www..com Table 20-1. Interrupt Source List (1/2) Interrupt Type Default Priority Note 1 Interrupt Source Name INTLVI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTSRE6 INTSR6 INTST6 INTCSI10/ INTST0 UART6 reception error generation End of UART6 reception End of UART6 transmission End of CSI10 communication/end of UART0 transmission Match between TMH1 and CMP01 (when compare register is specified) Trigger Low-voltage detection Note 3 Internal/ External Vector Table Address Basic Configuration Type Note 2 Maskable 0 1 2 3 4 5 6 7 8 9 10 Internal External 0004H 0006H 0008H 000AH 000CH 000EH 0010H (A) (B) Pin input edge detection Internal 0012H 0014H 0016H 0018H (A) 11 INTTMH1 001AH 12 INTTMH0 Match between TMH0 and CMP00 (when compare register is specified) 001CH 13 INTTM50 Match between TM50 and CR50 (when compare register is specified) 001EH 14 INTTM000 Match between TM00 and CR000 (when compare register is specified), TI010 pin valid edge detection (when capture register is specified) 0020H 15 INTTM010 Match between TM00 and CR010 (when compare register is specified), TI000 pin valid edge detection (when capture register is specified) 0022H 16 17 INTAD INTSR0 End of A/D conversion End of UART0 reception or reception error generation 0024H 0026H 18 19 INTWTI INTTM51 Note 4 Watch timer reference time interval signal Match between TM51 and CR51 (when compare register is specified) Key interrupt detection Watch timer overflow Pin input edge detection External Internal External 0028H 002AH 20 21 22 23 INTKR INTWT INTP6 INTP7 002CH 002EH 0030H 0032H (C) (A) (B) Notes 1. 2. 3. The default priority determines the sequence of processing vectored interrupts if two or more maskable interrupts occur simultaneously. Zero indicates the highest priority and 28 indicates the lowest priority. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 20-1. When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is cleared to 0. When the 8-bit timer/event counter 51 is used in the carrier generator mode, the interrupt source is INTTM5H1 (see Figure 9-13 Transfer Timing). 522 User's Manual U17397EJ4V0UD CHAPTER 20 INTERRUPT FUNCTIONS www..com Table 20-1. Interrupt Source List (2/2) Interrupt Type Default Priority Note 1 Interrupt Source Name INTIIC0/ INTDMU Trigger End of IIC0 communication/end of multiply/divide operation End of CSI11 communication Match between TM01 and CR001 (when compare register is specified), TI011 pin valid edge detection (when capture register is specified) Internal/ External Vector Table Address Basic Configuration Type Note 2 Maskable 24 Internal 0034H (A) 25 26 INTCSI11 INTTM001 0036H 0038H 27 INTTM011 Match between TM01 and CR011 (when compare register is specified), TI001 pin valid edge detection (when capture register is specified) 003AH 28 Software Reset - - INTACSI BRK RESET POC LVI WDT End of CSIA0 communication BRK instruction execution Reset input Power-on clear Low-voltage detection WDT overflow Note 3 003CH - - 003EH 0000H (D) - Notes 1. 2. 3. The default priority determines the sequence of processing vectored interrupts if two or more maskable interrupts occur simultaneously. Zero indicates the highest priority and 28 indicates the lowest priority. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 20-1. When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is set to 1. User's Manual U17397EJ4V0UD 523 CHAPTER 20 INTERRUPT FUNCTIONS www..com Figure 20-1. Basic Configuration of Interrupt Function (1/2) (A) Internal maskable interrupt Internal bus MK IE PR ISP Interrupt request IF Priority controller Vector table address generator Standby release signal (B) External maskable interrupt (INTP0 to INTP7) Internal bus External interrupt edge enable register (EGP, EGN) MK IE PR ISP Interrupt request Edge detector IF Priority controller Vector table address generator Standby release signal IF: IE: ISP: MK: PR: Interrupt request flag Interrupt enable flag In-service priority flag Interrupt mask flag Priority specification flag 524 User's Manual U17397EJ4V0UD CHAPTER 20 INTERRUPT FUNCTIONS www..com Figure 20-1. Basic Configuration of Interrupt Function (2/2) (C) External maskable interrupt (INTKR) Internal bus MK IE PR ISP Interrupt request Key interrupt detector IF Priority controller Vector table address generator 1 when KRMn = 1 (n = 0 to 7) Standby release signal (D) Software interrupt Internal bus Interrupt request Priority controller Vector table address generator IF: IE: ISP: MK: PR: Interrupt request flag Interrupt enable flag In-service priority flag Interrupt mask flag Priority specification flag KRM: Key return mode register User's Manual U17397EJ4V0UD 525 CHAPTER 20 INTERRUPT FUNCTIONS www..com 20.3 Registers Controlling Interrupt Functions The following 6 types of registers are used to control the interrupt functions. * Interrupt request flag register (IF0L, IF0H, IF1L, IF1H) * Interrupt mask flag register (MK0L, MK0H, MK1L, MK1H) * Priority specification flag register (PR0L, PR0H, PR1L, PR1H) * External interrupt rising edge enable register (EGP) * External interrupt falling edge enable register (EGN) * Program status word (PSW) Table 20-2 shows a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to interrupt request sources. Table 20-2. Flags Corresponding to Interrupt Request Sources (1/2) Interrupt Source INTLVI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTSRE6 INTSR6 INTST6 INTCSI10 LVIIF PIF0 PIF1 PIF2 PIF3 PIF4 PIF5 SREIF6 SRIF6 STIF6 CSIIF10 Note 1 Interrupt Request Flag Register IF0L LVIMK PMK0 PMK1 PMK2 PMK3 PMK4 PMK5 Interrupt Mask Flag Register MK0L Priority Specification Flag Register LVIPR PPR0 PPR1 PPR2 PPR3 PPR4 PPR5 SREPR6 PR0L SREMK6 IF0H SRMK6 STMK6 DUALIF0 Note 1 MK0H SRPR6 STPR6 PR0H CSIMK10 Note 2 DUALMK0 Note 2 CSIPR10 Note 3 DUALPR0 Note 3 INTST0 STIF0 Note 1 STMK0 Note 2 STPR0 Note 3 INTTMH1 INTTMH0 INTTM50 INTTM000 INTTM010 TMIFH1 TMIFH0 TMIF50 TMIF000 TMIF010 TMMKH1 TMMKH0 TMMK50 TMMK000 TMMK010 TMPRH1 TMPRH0 TMPR50 TMPR000 TMPR010 Notes 1. 2. 3. If either interrupt source INTCSI10 or INTST0 is generated, bit 2 of IF0H is set (1). Bit 2 of MK0H supports both interrupt sources INTCSI10 and INTST0. Bit 2 of PR0H supports both interrupt sources INTCSI10 and INTST0. 526 User's Manual U17397EJ4V0UD CHAPTER 20 INTERRUPT FUNCTIONS www..com Table 20-2. Flags Corresponding to Interrupt Request Sources (2/2) Interrupt Source INTAD INTSR0 INTWTI INTTM51 INTKR INTWT INTP6 INTP7 INTIIC0 Note 2 Note 1 Interrupt Request Flag Register ADIF SRIF0 WTIIF TMIF51 KRIF WTIF PIF6 PIF7 IICIF0 Note 3 Interrupt Mask Flag Register ADMK SRMK0 WTIMK TMMK51 KRMK WTMK PMK6 PMK7 MK1L Priority Specification Flag Register ADPR SRPR0 WTIPR TMPR51 KRPR WTPR PPR6 PPR7 PR1L IF1L IF1H IICMK0 Note 4 MK1H IICPR0 Note 5 PR1H INTDMU Note 2 DMUIF Note 3 DMUMK Note 4 DMUPR Note 5 INTCSI11 INTTM001 INTTM011 INTACSI CSIIF11 TMIF001 TMIF011 ACSIIF CSIMK11 TMMK001 TMMK011 ACSIMK CSIPR11 TMPR001 TMPR011 ACSIPR Notes 1. 2. When the 8-bit timer/event counter 51 is used in the carrier generator mode, the interrupt source is INTTM5H1 (see Figure 9-13 Transfer Timing). Do not use serial interface IIC0 and multiplier/divider simultaneously, because the flags corresponding to the interrupt request sources of serial interface IIC0 and multiplier/divider support both of these interrupt request sources. If software which operates serial interface IIC0 is developed by CC78K0 which is C compiler, do not select the check box of "Using Multiplier/Divider" on GUI of PM+. 3. 4. 5. If either interrupt source INTIIC0 or INTDMU is generated, bit 0 of IF1H is set (1). Bit 0 of MK1H supports both interrupt sources INTIIC0 and INTDMU. Bit 0 of PR1H supports both interrupt sources INTIIC0 and INTDMU. User's Manual U17397EJ4V0UD 527 CHAPTER 20 INTERRUPT FUNCTIONS www..com (1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset signal generation. When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is entered. IF0L, IF0H, IF1L, and IF1H are set by a 1-bit or 8-bit memory manipulation instruction. When IF0L and IF0H, and IF1L and IF1H are combined to form 16-bit registers IF0 and IF1, they are set by a 16-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 20-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H) Address: FFE0H After reset: 00H R/W Symbol IF0L <7> SREIF6 <6> PIF5 <5> PIF4 <4> PIF3 <3> PIF2 <2> PIF1 <1> PIF0 <0> LVIIF Address: FFE1H Symbol IF0H After reset: 00H <7> <6> TMIF000 R/W <5> TMIF50 <4> TMIFH0 <3> TMIFH1 <2> DUALIF0 CSIIF10 STIF0 <1> STIF6 <0> SRIF6 TMIF010 Address: FFE2H Symbol IF1L After reset: 00H <7> PIF7 <6> PIF6 R/W <5> WTIF <4> KRIF <3> TMIF51 <2> WTIIF <1> SRIF0 <0> ADIF Address: FFE3H Symbol IF1H After reset: 00H 7 0 6 0 R/W 5 0 <4> ACSIIF <3> TMIF011 <2> TMIF001 <1> CSIIF11 <0> IICIF0 DMUIF XXIFX 0 1 Interrupt request flag No interrupt request signal is generated Interrupt request is generated, interrupt request status Cautions 1. Be sure to clear bits 5 to 7 of IF1H to 0. 2. When operating a timer, serial interface, or A/D converter after standby release, operate it once after clearing the interrupt request flag. An interrupt request flag may be set by noise. 528 User's Manual U17397EJ4V0UD CHAPTER 20 INTERRUPT FUNCTIONS www..com Cautions 3. When manipulating a flag of the interrupt request flag register, use a 1-bit memory manipulation instruction (CLR1). When describing in C language, use a bit manipulation instruction such as "IF0L.0 = 0;" or "_asm("clr1 IF0L, 0");" because the compiled assembler must be a 1-bit memory manipulation instruction (CLR1). If a program is described in C language using an 8-bit memory manipulation instruction such as "IF0L &= 0xfe;" and compiled, it becomes the assembler of three instructions. mov a, IF0L and a, #0FEH mov IF0L, a In this case, even if the request flag of another bit of the same interrupt request flag register (IF0L) is set to 1 at the timing between "mov a, IF0L" and "mov IF0L, a", the flag is cleared to 0 at "mov IF0L, a". Therefore, care must be exercised when using an 8-bit memory manipulation instruction in C language. User's Manual U17397EJ4V0UD 529 CHAPTER 20 INTERRUPT FUNCTIONS www..com (2) Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. MK0L, MK0H, MK1L, and MK1H are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H, and MK1L and MK1H are combined to form 16-bit registers MK0 and MK1, they are set by a 16-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Figure 20-3. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H) Address: FFE4H Symbol MK0L After reset: FFH <7> SREMK6 <6> PMK5 R/W <5> PMK4 <4> PMK3 <3> PMK2 <2> PMK1 <1> PMK0 <0> LVIMK Address: FFE5H Symbol MK0H After reset: FFH <7> <6> TMMK000 R/W <5> TMMK50 <4> TMMKH0 <3> TMMKH1 <2> DUALMK0 CSIMK10 STMK0 <1> STMK6 <0> SRMK6 TMMK010 Address: FFE6H Symbol MK1L After reset: FFH <7> <6> PMK6 R/W <5> WTMK <4> KRMK <3> TMMK51 <2> WTIMK <1> SRMK0 <0> ADMK PMK7 Address: FFE7H Symbol MK1H After reset: FFH 7 1 6 1 R/W 5 1 <4> ACSIMK <3> TMMK011 <2> TMMK001 <1> CSIMK11 <0> IICMK0 DMUMK XXMKX 0 1 Interrupt servicing enabled Interrupt servicing disabled Interrupt servicing control Caution Be sure to set bits 5 to 7 of MK1H to 1. 530 User's Manual U17397EJ4V0UD CHAPTER 20 INTERRUPT FUNCTIONS www..com (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H) The priority specification flag registers are used to set the corresponding maskable interrupt priority order. PR0L, PR0H, PR1L, and PR1H are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H, and PR1L and PR1H are combined to form 16-bit registers PR0 and PR1, they are set by a 16-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Figure 20-4. Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L, PR1H) Address: FFE8H Symbol PR0L After reset: FFH <7> SREPR6 <6> PPR5 R/W <5> PPR4 <4> PPR3 <3> PPR2 <2> PPR1 <1> PPR0 <0> LVIPR Address: FFE9H Symbol PR0H After reset: FFH <7> <6> TMPR000 R/W <5> TMPR50 <4> TMPRH0 <3> TMPRH1 <2> DUALPR0 CSIPR10 STPR0 <1> STPR6 <0> SRPR6 TMPR010 Address: FFEAH Symbol PR1L After reset: FFH <7> <6> PPR6 R/W <5> WTPR <4> KRPR <3> TMPR51 <2> WTIPR <1> SRPR0 <0> ADPR PPR7 Address: FFEBH Symbol PR1H After reset: FFH 7 1 6 1 R/W 5 1 <4> ACSIPR <3> TMPR011 <2> TMPR001 <1> CSIPR11 <0> IICPR0 DMUPR XXPRX 0 1 High priority level Low priority level Priority level selection Caution Be sure to set bits 5 to 7 of PR1H to 1. User's Manual U17397EJ4V0UD 531 CHAPTER 20 INTERRUPT FUNCTIONS www..com (4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) These registers specify the valid edge for INTP0 to INTP7. EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 20-5. Format of External Interrupt Rising Edge Enable Register (EGP) and External Interrupt Falling Edge Enable Register (EGN) Address: FF48H Symbol EGP After reset: 00H 7 EGP7 6 EGP6 R/W 5 EGP5 4 EGP4 3 EGP3 2 EGP2 1 EGP1 0 EGP0 Address: FF49H Symbol EGN After reset: 00H 7 EGN7 6 EGN6 R/W 5 EGN5 4 EGN4 3 EGN3 2 EGN2 1 EGN1 0 EGN0 EGPn 0 0 1 1 EGNn 0 1 0 1 INTPn pin valid edge selection (n = 0 to 7) Edge detection disabled Falling edge Rising edge Both rising and falling edges Table 20-3 shows the ports corresponding to EGPn and EGNn. Table 20-3. Ports Corresponding to EGPn and EGNn Detection Enable Register EGP0 EGP1 EGP2 EGP3 EGP4 EGP5 EGP6 EGP7 EGN0 EGN1 EGN2 EGN3 EGN4 EGN5 EGN6 EGN7 P120 P30 P31 P32 P33 P16 P140 P141 Edge Detection Port Interrupt Request Signal INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTP7 Caution Select the port mode by clearing EGPn and EGNn to 0 because an edge may be detected when the external interrupt function is switched to the port function. Remark n = 0 to 7 532 User's Manual U17397EJ4V0UD CHAPTER 20 INTERRUPT FUNCTIONS www..com (5) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP flag that controls multiple interrupt servicing are mapped to the PSW. Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated instructions (EI and DI). When a vectored interrupt request is acknowledged, if the BRK instruction is executed, the contents of the PSW are automatically saved into a stack and the IE flag is reset to 0. If a maskable interrupt request is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are transferred to the ISP flag. The PSW contents are also saved into the stack with the PUSH PSW instruction. They are restored from the stack with the RETI, RETB, and POP PSW instructions. Reset signal generation sets PSW to 02H. Figure 20-6. Format of Program Status Word <7> PSW IE <6> Z <5> RBS1 <4> AC <3> RBS0 2 0 <1> ISP 0 CY After reset 02H Used when normal instruction is executed ISP 0 Priority of interrupt currently being serviced High-priority interrupt servicing (low-priority interrupt disabled) Interrupt request not acknowledged, or lowpriority interrupt servicing (all maskable interrupts enabled) 1 IE 0 1 Interrupt request acknowledgment enable/disable Disabled Enabled User's Manual U17397EJ4V0UD 533 CHAPTER 20 INTERRUPT FUNCTIONS www..com 20.4 Interrupt Servicing Operations 20.4.1 Maskable interrupt acknowledgment A maskable interrupt becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1). However, a low-priority interrupt request is not acknowledged during servicing of a higher priority interrupt request (when the ISP flag is reset to 0). The times from generation of a maskable interrupt request until vectored interrupt servicing is performed are listed in Table 20-4 below. For the interrupt request acknowledgment timing, see Figures 20-8 and 20-9. Table 20-4. Time from Generation of Maskable Interrupt Until Servicing Minimum Time When xxPR = 0 When xxPR = 1 7 clocks 8 clocks Maximum Time 32 clocks 33 clocks Note Note If an interrupt request is generated just before a divide instruction, the wait time becomes longer. Remark 1 clock: 1/fCPU (fCPU: CPU clock) If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level specified in the priority specification flag is acknowledged first. If two or more interrupts requests have the same priority level, the request with the highest default priority is acknowledged first. An interrupt request that is held pending is acknowledged when it becomes acknowledgeable. Figure 20-7 shows the interrupt request acknowledgment algorithm. If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then PC, the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged interrupt are transferred to the ISP flag. The vector table data determined for each interrupt request is the loaded into the PC and branched. Restoring from an interrupt is possible by using the RETI instruction. 534 User's Manual U17397EJ4V0UD CHAPTER 20 INTERRUPT FUNCTIONS www..com Figure 20-7. Interrupt Request Acknowledgment Processing Algorithm Start No xxIF = 1? Yes (interrupt request generation) No xxMK = 0? Yes Interrupt request held pending Yes (High priority) xxPR = 0? No (Low priority) Yes Any high-priority interrupt request among those simultaneously generated with xxPR = 0? Interrupt request held pending No No IE = 1? Yes Any high-priority interrupt request among those simultaneously generated with xxPR = 0? Yes No Any high-priority interrupt request among those simultaneously generated? Interrupt request held pending Yes Interrupt request held pending No Vectored interrupt servicing IE = 1? Yes ISP = 1? Yes Interrupt request held pending No Interrupt request held pending No Interrupt request held pending Vectored interrupt servicing xxIF: Interrupt request flag xxMK: Interrupt mask flag xxPR: Priority specification flag IE: ISP: Flag that controls acknowledgment of maskable interrupt request (1 = Enable, 0 = Disable) Flag that indicates the priority level of the interrupt currently being serviced (0 = high-priority interrupt servicing, 1 = No interrupt request acknowledged, or low-priority interrupt servicing) User's Manual U17397EJ4V0UD 535 CHAPTER 20 INTERRUPT FUNCTIONS www..com Figure 20-8. Interrupt Request Acknowledgment Timing (Minimum Time) 6 clocks CPU processing xxIF (xxPR = 1) 8 clocks xxIF (xxPR = 0) 7 clocks Instruction Instruction PSW and PC saved, jump to interrupt servicing Interrupt servicing program Remark 1 clock: 1/fCPU (fCPU: CPU clock) Figure 20-9. Interrupt Request Acknowledgment Timing (Maximum Time) 25 clocks 6 clocks PSW and PC saved, jump to interrupt servicing CPU processing xxIF (xxPR = 1) Instruction Divide instruction Interrupt servicing program 33 clocks xxIF (xxPR = 0) 32 clocks Remark 1 clock: 1/fCPU (fCPU: CPU clock) 20.4.2 Software interrupt request acknowledgment A software interrupt acknowledge is acknowledged by BRK instruction execution. Software interrupts cannot be disabled. If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (003EH, 003FH) are loaded into the PC and branched. Restoring from a software interrupt is possible by using the RETB instruction. Caution Do not use the RETI instruction for restoring from the software interrupt. 536 User's Manual U17397EJ4V0UD CHAPTER 20 INTERRUPT FUNCTIONS www..com 20.4.3 Multiple interrupt servicing Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected (IE = 1). When an interrupt request is acknowledged, interrupt request acknowledgment becomes disabled (IE = 0). Therefore, to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during interrupt servicing to enable interrupt acknowledgment. Moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to interrupt priority control. Two types of priority control are available: default priority control and programmable priority control. Programmable priority control is used for multiple interrupt servicing. In the interrupt enabled state, if an interrupt request with a priority equal to or higher than that of the interrupt currently being serviced is generated, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for multiple interrupt servicing. Interrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they have a lower priority are held pending. When servicing of the current interrupt ends, the pending interrupt request is acknowledged following execution of at least one main processing instruction execution. Table 20-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and Figure 20-10 shows multiple interrupt servicing examples. Table 20-5. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing During Interrupt Servicing Multiple Interrupt Request Maskable Interrupt Request PR = 0 Interrupt Being Serviced Maskable interrupt ISP = 0 ISP = 1 Software interrupt IE = 1 IE = 0 x x x IE = 1 x PR = 1 IE = 0 x x x Software Interrupt Request Remarks 1. : Multiple interrupt servicing enabled 2. x: Multiple interrupt servicing disabled 3. ISP and IE are flags contained in the PSW. ISP = 0: An interrupt with higher priority is being serviced. ISP = 1: No interrupt request has been acknowledged, or an interrupt with a lower priority is being serviced. IE = 0: IE = 1: Interrupt request acknowledgment is disabled. Interrupt request acknowledgment is enabled. 4. PR is a flag contained in PR0L, PR0H, PR1L, and PR1H. PR = 0: Higher priority level PR = 1: Lower priority level User's Manual U17397EJ4V0UD 537 CHAPTER 20 INTERRUPT FUNCTIONS www..com Figure 20-10. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing INTyy servicing INTzz servicing EI IE = 0 EI INTyy (PR = 0) IE = 0 EI INTzz (PR = 0) IE = 0 INTxx (PR = 1) RETI IE = 1 IE = 1 RETI IE = 1 RETI During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple interrupt servicing takes place. Before each interrupt request is acknowledged, the EI instruction must always be issued to enable interrupt request acknowledgment. Example 2. Multiple interrupt servicing does not occur due to priority control Main processing INTxx servicing INTyy servicing EI IE = 0 EI INTxx (PR = 0) INTyy (PR = 1) IE = 1 RETI 1 instruction execution IE = 0 RETI IE = 1 Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its priority is lower than that of INTxx, and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. PR = 0: Higher priority level PR = 1: Lower priority level IE = 0: Interrupt request acknowledgment disabled 538 User's Manual U17397EJ4V0UD CHAPTER 20 INTERRUPT FUNCTIONS www..com Figure 20-10. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing IE = 0 EI INTyy (PR = 0) RETI IE = 1 INTxx servicing INTyy servicing INTxx (PR = 0) 1 instruction execution IE = 0 RETI IE = 1 Interrupts are not enabled during servicing of interrupt INTxx (EI instruction is not issued), therefore, interrupt request INTyy is not acknowledged and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. PR = 0: Higher priority level IE = 0: Interrupt request acknowledgment disabled User's Manual U17397EJ4V0UD 539 CHAPTER 20 INTERRUPT FUNCTIONS www..com 20.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgment is held pending until the end of execution of the next instruction. instructions (interrupt request hold instructions) are listed below. * MOV PSW, #byte * MOV A, PSW * MOV PSW, A * MOV1 PSW. bit, CY * MOV1 CY, PSW. bit * AND1 CY, PSW. bit * OR1 CY, PSW. bit * XOR1 CY, PSW. bit * SET1 PSW. bit * CLR1 PSW. bit * RETB * RETI * PUSH PSW * POP PSW * BT PSW. bit, $addr16 * BF PSW. bit, $addr16 * BTCLR PSW. bit, $addr16 * EI * DI * Manipulation instructions for the IF0L, IF0H, IF1L, IF1H, MK0L, MK0H, MK1L, MK1H, PR0L, PR0H, PR1L, and PR1H registers. Caution The BRK instruction is not one of the above-listed interrupt request hold instructions. However, the software interrupt activated by executing the BRK instruction causes the IE flag to be cleared. Therefore, even if a maskable interrupt request is generated during execution of the BRK instruction, the interrupt request is not acknowledged. Figure 20-11 shows the timing at which interrupt requests are held pending. Figure 20-11. Interrupt Request Hold PSW and PC saved, jump to interrupt servicing Interrupt servicing program These CPU processing Instruction N Instruction M xxIF Remarks 1. Instruction N: Interrupt request hold instruction 2. Instruction M: Instruction other than interrupt request hold instruction 3. The xxPR (priority level) values do not affect the operation of xxIF (interrupt request). 540 User's Manual U17397EJ4V0UD www..com CHAPTER 21 KEY INTERRUPT FUNCTION 21.1 Functions of Key Interrupt A key interrupt (INTKR) can be generated by setting the key return mode register (KRM) and inputting a falling edge to the key interrupt input pins (KR0 to KR7). Table 21-1. Assignment of Key Interrupt Detection Pins Flag KRM0 KRM1 KRM2 KRM3 KRM4 KRM5 KRM6 KRM7 Description Controls KR0 signal in 1-bit units. Controls KR1 signal in 1-bit units. Controls KR2 signal in 1-bit units. Controls KR3 signal in 1-bit units. Controls KR4 signal in 1-bit units. Controls KR5 signal in 1-bit units. Controls KR6 signal in 1-bit units. Controls KR7 signal in 1-bit units. 21.2 Configuration of Key Interrupt The key interrupt includes the following hardware. Table 21-2. Configuration of Key Interrupt Item Control register Configuration Key return mode register (KRM) Figure 21-1. Block Diagram of Key Interrupt KR7 KR6 KR5 KR4 INTKR KR3 KR2 KR1 KR0 KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0 Key return mode register (KRM) User's Manual U17397EJ4V0UD 541 CHAPTER 21 KEY INTERRUPT FUNCTION www..com 21.3 Register Controlling Key Interrupt (1) Key return mode register (KRM) This register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals, respectively. KRM is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears KRM to 00H. Figure 21-2. Format of Key Return Mode Register (KRM) Address: FF6EH Symbol KRM 7 KRM7 After reset: 00H 6 KRM6 5 KRM5 R/W 4 KRM4 3 KRM3 2 KRM2 KRM1 0 KRM0 KRMn 0 1 Key interrupt mode control Does not detect key interrupt signal Detects key interrupt signal Cautions 1. If any of the KRM0 to KRM7 bits used is set to 1, set bits 0 to 7 (PU70 to PU77) of the corresponding pull-up resistor register 7 (PU7) to 1. 2. If KRM is changed, the interrupt request flag may be set. Therefore, disable interrupts and then change the KRM register. Clear the interrupt request flag and enable interrupts. 3. The bits not used in the key interrupt mode can be used as normal ports. 542 User's Manual U17397EJ4V0UD www..com CHAPTER 22 STANDBY FUNCTION 22.1 Standby Function and Configuration 22.1.1 Standby function The standby function is designed to reduce the operating current of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the high-speed system clock oscillator, internal high-speed oscillator, internal low-speed oscillator, or subsystem clock oscillator is operating before the HALT mode is set, oscillation of each clock continues. In this mode, the operating current is not decreased as much as in the STOP mode, but the HALT mode is effective for restarting operation immediately upon interrupt request generation and carrying out intermittent operations frequently. (2) STOP mode STOP instruction execution sets the STOP mode. In the STOP mode, the high-speed system clock oscillator and internal high-speed oscillator stop, stopping the whole system, thereby considerably reducing the CPU operating current. Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out. However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is released when the X1 clock is selected, select the HALT mode if it is necessary to start processing immediately upon interrupt request generation. In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is set are held. The I/O port output latches and output buffer statuses are also held. Cautions 1. The STOP mode can be used only when the CPU is operating on the main system clock. The subsystem clock oscillation cannot be stopped. The HALT mode can be used when the CPU is operating on either the main system clock or the subsystem clock. 2. When shifting to the STOP mode, be sure to stop the peripheral hardware operation operating with main system clock before executing STOP instruction. 3. The following sequence is recommended for operating current reduction of the A/D converter when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 to stop the A/D conversion operation, and then execute the STOP instruction. 22.1.2 Registers controlling standby function The standby function is controlled by the following two registers. * Oscillation stabilization time counter status register (OSTC) * Oscillation stabilization time select register (OSTS) Remark For the registers that start, stop, or select the clock, see CHAPTER 6 CLOCK GENERATOR. User's Manual U17397EJ4V0UD 543 CHAPTER 22 STANDBY FUNCTION www..com (1) Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. When X1 clock oscillation starts with the internal high-speed oscillation clock or subsystem clock used as the CPU clock, the X1 clock oscillation stabilization time can be checked. OSTC can be read by a 1-bit or 8-bit memory manipulation instruction. When reset is released (reset by RESET input, POC, LVI, and WDT), the STOP instruction and MSTOP (bit 7 of MOC register) = 1 clear OSTC to 00H. Figure 22-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFA3H Symbol OSTC 7 0 After reset: 00H 6 0 R 5 0 4 MOST11 3 MOST13 2 MOST14 1 MOST15 0 MOST16 MOST11 MOST13 MOST14 MOST15 MOST16 Oscillation stabilization time status fX = 10 MHz fX = 20 MHz 1 1 1 1 1 0 1 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 0 0 1 2 /fX min. 2 /fX min. 2 /fX min. 2 /fX min. 2 /fX min. 16 15 14 13 11 204.8 s min. 102.4 s min. 819.2 s min. 409.6 s min. 1.64 ms min. 819.2 s min. 3.27 ms min. 1.64 ms min. 6.55 ms min. 3.27 ms min. Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and remain 1. 2. The oscillation stabilization time counter counts up to the oscillation stabilization time set by OSTS. If the STOP mode is entered and then released while the internal high-speed oscillation clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. 3. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts ("a" below). STOP mode release X1 pin voltage waveform a Remark fX: X1 clock oscillation frequency 544 User's Manual U17397EJ4V0UD CHAPTER 22 STANDBY FUNCTION www..com (2) Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP mode is released. When the internal high-speed oscillation clock is selected as the CPU clock, confirm with OSTC that the desired oscillation stabilization time has elapsed after the STOP mode is released. The oscillation stabilization time can be checked up to the time set using OSTC. OSTS can be set by an 8-bit memory manipulation instruction. Reset signal generation sets OSTS to 05H. Figure 22-2. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFA4H Symbol OSTS 7 0 After reset: 05H 6 0 R/W 5 0 4 0 3 0 2 OSTS2 1 OSTS1 0 OSTS0 OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection fX = 10 MHz fX = 20 MHz 102.4 s 409.6 s 819.2 s 1.64 ms 3.27 ms 0 0 0 1 1 0 1 1 0 0 Other than above 1 0 1 0 1 2 /fX 2 /fX 2 /fX 2 /fX 2 /fX Setting prohibited 16 15 14 13 11 204.8 s 819.2 s 1.64 ms 3.27 ms 6.55 ms Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS before executing the STOP instruction. 2. Do not change the value of the OSTS register during the X1 clock oscillation stabilization time. 3. The oscillation stabilization time counter counts up to the oscillation stabilization time set by OSTS. If the STOP mode is entered and then released while the internal high-speed oscillation clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. 4. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts ("a" below). STOP mode release X1 pin voltage waveform a Remark fX: X1 clock oscillation frequency User's Manual U17397EJ4V0UD 545 CHAPTER 22 STANDBY FUNCTION www..com 22.2 Standby Function Operation 22.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU clock before the setting was the high-speed system clock, internal high-speed oscillation clock, or subsystem clock. The operating statuses in the HALT mode are shown below. 546 User's Manual U17397EJ4V0UD CHAPTER 22 STANDBY FUNCTION www..com Table 22-1. Operating Statuses in HALT Mode (1/2) HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on Internal High-Speed Oscillation Clock (fRH) When CPU Is Operating on X1 Clock (fX) When CPU Is Operating on External Main System Clock (fEXCLK) Item System clock Main system clock fRH fX fEXCLK Subsystem clock fXT fEXCLKS fRL CPU Flash memory RAM Port (latch) 16-bit timer/event counter 8-bit timer/event counter 8-bit timer 00 01 50 51 H0 H1 Watch timer Watchdog timer Clock output Buzzer output A/D converter Serial interface UART0 UART6 CSI10 CSI11 CSIA0 IIC0 Multiplier/divider Power-on-clear function Low-voltage detection function External interrupt Clock supply to the CPU is stopped Operation continues (cannot be stopped) Status before HALT mode was set is retained Status before HALT mode was set is retained Operation continues (cannot be stopped) Status before HALT mode was set is retained Operation continues (cannot be stopped) Operates or stops by external clock input Status before HALT mode was set is retained Operates or stops by external clock input Status before HALT mode was set is retained Operation stopped Operation stopped Status before HALT mode was set is retained Status before HALT mode was set is retained Operable Operable. Clock supply to watchdog timer stops when "internal low-speed oscillator can be stopped by software" is set by option byte. Operable Remark fRH: fX: fEXCLK: fXT: fRL: Internal high-speed oscillation clock X1 clock External main system clock XT1 clock Internal low-speed oscillation clock fEXCLKS: External subsystem clock User's Manual U17397EJ4V0UD 547 CHAPTER 22 STANDBY FUNCTION www..com Table 22-1. Operating Statuses in HALT Mode (2/2) HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock When CPU Is Operating on XT1 Clock (fXT) Item System clock Main system clock fRH fX fEXCLK Subsystem clock fXT fEXCLKS fRL CPU Flash memory RAM Port (latch) 16-bit timer/event counter 8-bit timer/event counter 8-bit timer 00 01 50 51 Note Note When CPU Is Operating on External Subsystem Clock (fEXCLKS) Clock supply to the CPU is stopped Status before HALT mode was set is retained Operates or stops by external clock input Operation continues (cannot be stopped) Operates or stops by external clock input Status before HALT mode was set is retained Operation stopped Operation stopped Status before HALT mode was set is retained Status before HALT mode was set is retained Operable Status before HALT mode was set is retained Operation continues (cannot be stopped) Note Note H0 H1 Watch timer Watchdog timer Clock output Buzzer output A/D converter Serial interface UART0 UART6 CSI10 CSI11 Note Note Operable. Clock supply to watchdog timer stops when "internal low-speed oscillator can be stopped by software" is set by option byte. Operable Operable. However, operation disabled when peripheral hardware clock (fPRS) is stopped. Operable CSIA0 IIC0 Multiplier/divider Power-on-clear function Note Note Low-voltage detection function External interrupt Note When the CPU is operating on the subsystem clock and the internal high-speed oscillation clock has been stopped, do not start operation of these functions on the external clock input from peripheral hardware pins. Remark fRH: fX: fEXCLK: fXT: fRL: Internal high-speed oscillation clock X1 clock External main system clock XT1 clock Internal low-speed oscillation clock fEXCLKS: External subsystem clock 548 User's Manual U17397EJ4V0UD CHAPTER 22 STANDBY FUNCTION www..com (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. Figure 22-3. HALT Mode Release by Interrupt Request Generation Interrupt request HALT instruction Standby release signal Normal operation Status of CPU High-speed system clock, internal high-speed oscillation clock, or subsystem clock HALT mode WaitNote Oscillation Normal operation Note The wait time is as follows: * When vectored interrupt servicing is carried out: 8 or 9 clocks * When vectored interrupt servicing is not carried out: 2 or 3 clocks Remark The broken lines indicate the case when the interrupt request which has released the standby mode is acknowledged. User's Manual U17397EJ4V0UD 549 CHAPTER 22 STANDBY FUNCTION www..com (b) Release by reset signal generation When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 22-4. HALT Mode Release by Reset (1) When high-speed system clock is used as CPU clock HALT instruction Reset signal Normal operation (high-speed system clock) Reset Reset processing period (11 to 45 s) Oscillation Oscillation stopped stopped Normal operation (internal high-speed oscillation clock) Oscillates Oscillation stabilization time (211/fX to 216/fX) Status of CPU High-speed system clock (X1 oscillation) HALT mode Oscillates Starting X1 oscillation is specified by software. (2) When internal high-speed oscillation clock is used as CPU clock HALT instruction Reset signal Normal operation (internal high-speed oscillation clock) Status of CPU Internal high-speed oscillation clock Reset Reset processing period (11 to 45 s) Oscillation stopped Normal operation (internal high-speed oscillation clock) Oscillates HALT mode Oscillates Wait for oscillation accuracy stabilization (86 to 361 s) (3) When subsystem clock is used as CPU clock HALT instruction Reset signal Normal operation (subsystem clock) Reset period Reset Normal operation mode processing (internal high-speed (11 to 45 s) oscillation clock) Status of CPU Subsystem clock (XT1 oscillation) HALT mode Oscillates Oscillation Oscillation stopped stopped Oscillates Starting XT1 oscillation is specified by software. Remark fX: X1 clock oscillation frequency 550 User's Manual U17397EJ4V0UD CHAPTER 22 STANDBY FUNCTION www..com Table 22-2. Operation in Response to Interrupt Request in HALT Mode Release Source Maskable interrupt request 0 0 1 x 1 0 1 x x MKxx 0 PRxx 0 IE 0 ISP x Operation Next address instruction execution Interrupt servicing execution 0 0 0 1 1 1 x - 0 x 1 x x Next address instruction execution Interrupt servicing execution 1 Reset - HALT mode held Reset processing x: don't care 22.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the setting was the main system clock. Caution Because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. Thus, the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction and the system returns to the operating mode as soon as the wait time set using the oscillation stabilization time select register (OSTS) has elapsed. The operating statuses in the STOP mode are shown below. User's Manual U17397EJ4V0UD 551 CHAPTER 22 STANDBY FUNCTION www..com Table 22-3. Operating Statuses in STOP Mode STOP Mode Setting When STOP Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on Internal High-Speed Oscillation Clock (fRH) When CPU Is Operating on X1 Clock (fX) When CPU Is Operating on External Main System Clock (fEXCLK) Item System clock Main system clock fRH fX fEXCLK Subsystem clock fXT fEXCLKS fRL CPU Flash memory RAM Port (latch) 16-bit timer/event counter 8-bit timer/event counter 8-bit timer 00 01 50 51 Note Note Clock supply to the CPU is stopped Stopped Input invalid Status before STOP mode was set is retained Operates or stops by external clock input Status before STOP mode was set is retained Operation stopped Operation stopped Status before STOP mode was set is retained Status before STOP mode was set is retained Operation stopped Note Operable only when TI50 is selected as the count clock Operable only when TI51 is selected as the count clock Operable only when TM50 output is selected as the count clock during 8-bit timer/event counter 50 operation Operable only when fRL, fRL/2 , fRL/2 is selected as the count clock Operable only when subsystem clock is selected as the count clock Operable. Clock supply to watchdog timer stops when "internal low-speed oscillator can be stopped by software" is set by option byte. Operable only when subsystem clock is selected as the count clock Operation stopped 7 9 Note H0 H1 Watch timer Watchdog timer Clock output Buzzer output A/D converter Serial interface UART0 UART6 CSI10 CSI11 Note Note Operable only when TM50 output is selected as the serial clock during 8-bit timer/event counter 50 operation Operable only when external clock is selected as the serial clock Multiplier/divider CSIA0 IIC0 Note Operation stopped Operable only when the external clock from EXSCL0/P62 pin is selected as the serial clock Operation stopped Operable Note Power-on-clear function Low-voltage detection function External interrupt fEXCLKS: External subsystem clock 552 User's Manual U17397EJ4V0UD CHAPTER 22 STANDBY FUNCTION www..com Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral hardware for which the clock that stops oscillating in the STOP mode after the STOP mode is released, restart the peripheral hardware. 2. Even if "internal low-speed oscillator can be stopped by software" is selected by the option byte, the internal low-speed oscillation clock continues in the STOP mode in the status before the STOP mode is set. To stop the internal low-speed oscillator's oscillation in the STOP mode, stop it by software and then execute the STOP instruction. 3. To shorten oscillation stabilization time after the STOP mode is released when the CPU operates with the high-speed system clock (X1 oscillation), temporarily switch the CPU clock to the internal high-speed oscillation clock before the next execution of the STOP instruction. Before changing the CPU clock from the internal high-speed oscillation clock to the high-speed system clock (X1 oscillation) after the STOP mode is released, check the oscillation stabilization time with the oscillation stabilization time counter status register (OSTC). STOP mode release STOP mode High-speed system clock (X1 oscillation) High-speed system clock (external clock input) Internal high-speed oscillation clock Wait for oscillation accuracy stabilization (86 to 361 s) HALT status (oscillation stabilization time set by OSTS) High-speed system clock Clock switched by software High-speed system clock WaitNote2 Supply of the CPU clock is stopped (160 external clocks)Note1 Internal high-speed oscillation clock WaitNote2 High-speed system clock Clock switched by software High-speed system clock (X1 oscillation) is selected as CPU clock when STOP instruction is executed High-speed system clock (external clock input) is selected as CPU clock when STOP instruction is executed Internal high-speed oscillation clock is selected as CPU clock when STOP instruction is executed Supply of the CPU clock is stopped (4.06 to 16.12 s)Note1 Notes 1. When AMPH = 1 2. The wait time is as follows: * When vectored interrupt servicing is carried out: * When vectored interrupt servicing is not carried out: 8 or 9 clocks 2 or 3 clocks User's Manual U17397EJ4V0UD 553 CHAPTER 22 STANDBY FUNCTION www..com (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. out. If interrupt acknowledgment is disabled, the next address instruction is executed. Interrupt request Wait (set by OSTS) After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried STOP instruction Standby release signal Status of CPU High-speed system clock (X1 oscillation) Normal operation (high-speed system clock) Oscillates STOP mode Oscillation stopped Oscillation stabilization wait (HALT mode status) Oscillates Normal operation (high-speed system clock) Oscillation stabilization time (set by OSTS) (2) When high-speed system clock (external clock input) is used as CPU clock (1/2) * When AMPH = 1 STOP instruction Standby release signal Normal operation (high-speed system clock) Oscillates Supply of the CPU clock is stopped (160 external clocks) Note Interrupt request Status of CPU High-speed system clock (external clock input) STOP mode Oscillation stopped Wait Normal operation (high-speed system clock) Oscillates Note The wait time is as follows: * When vectored interrupt servicing is carried out: * When vectored interrupt servicing is not carried out: 8 or 9 clocks 2 or 3 clocks Remark The broken lines indicate the case when the interrupt request that has released the standby mode is acknowledged. 554 User's Manual U17397EJ4V0UD CHAPTER 22 STANDBY FUNCTION www..com Figure 21-6. STOP Mode Release by Interrupt Request Generation (2/2) (2) When high-speed system clock (external clock input) is used as CPU clock (2/2) * When AMPH = 0 STOP instruction Standby release signal Normal operation (high-speed system clock) Oscillates Normal operation (high-speed system clock) Oscillates Interrupt request Status of CPU High-speed system clock (external clock input) STOP mode Oscillation stopped WaitNote (3) When internal high-speed oscillation clock is used as CPU clock * When AMPH = 1 STOP instruction Standby release signal Normal operation (internal high-speed oscillation clock) Oscillates Supply of the CPU clock is stopped (4.06 to 16.12 s) Interrupt request STOP mode Oscillation stopped Status of CPU Internal high-speed oscillation clock Wait Note Normal operation (internal high-speed oscillation clock) Oscillates Wait for oscillation accuracy stabilization (86 to 361 s) * When AMPH = 0 STOP instruction Standby release signal Normal operation (internal high-speed oscillation clock) Oscillates Normal operation (internal high-speed oscillation clock) Oscillates Wait for oscillation accuracy stabilization (86 to 361 s) Interrupt request Status of CPU Internal high-speed oscillation clock STOP mode Oscillation stopped WaitNote Note The wait time is as follows: * When vectored interrupt servicing is carried out: * When vectored interrupt servicing is not carried out: 8 or 9 clocks 2 or 3 clocks Remark The broken lines indicate the case when the interrupt request that has released the standby mode is acknowledged. User's Manual U17397EJ4V0UD 555 CHAPTER 22 STANDBY FUNCTION www..com (b) Release by reset signal generation When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 22-7. STOP Mode Release by Reset (1) When high-speed system clock is used as CPU clock STOP instruction Reset signal Normal operation (high-speed system clock) Oscillates Reset period Reset processing (11 to 45 s) Normal operation (internal high-speed oscillation clock) Oscillates Status of CPU High-speed system clock (X1 oscillation) STOP mode Oscillation stopped Oscillation Oscillation stopped stopped Oscillation stabilization time (211/fX to 216/fX) Starting X1 oscillation is specified by software. (2) When internal high-speed oscillation clock is used as CPU clock STOP instruction Reset signal Normal operation (internal high-speed oscillation clock) Oscillates Reset Reset processing period (11 to 45 s) Normal operation (internal high-speed oscillation clock) Oscillates Status of CPU Internal high-speed oscillation clock STOP mode Oscillation Oscillation stopped stopped Wait for oscillation accuracy stabilization (86 to 361 s) Remark fX: X1 clock oscillation frequency Table 22-4. Operation in Response to Interrupt Request in STOP Mode Release Source Maskable interrupt request 0 0 1 x 1 0 1 x x MKxx 0 PRxx 0 IE 0 ISP x Operation Next address instruction execution Interrupt servicing execution 0 0 0 1 1 1 x - 0 x 1 x x Next address instruction execution Interrupt servicing execution 1 Reset - STOP mode held Reset processing x: don't care 556 User's Manual U17397EJ4V0UD www..com CHAPTER 23 RESET FUNCTION The following four operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit (4) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI) External and internal resets have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H when the reset signal is generated. A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, or by POC and LVI circuit voltage detection, and each item of hardware is set to the status shown in Tables 23-1 and 23-2. Each pin is high impedance during reset signal generation or during the oscillation stabilization time just after a reset release, except for P130, which is low-level output. When a low level is input to the RESET pin, the device is reset. It is released from the reset status when a high level is input to the RESET pin and program execution is started with the internal high-speed oscillation clock after reset processing. A reset by the watchdog timer is automatically released, and program execution starts using the internal high-speed oscillation clock (see Figures 23-2 to 23-4) after reset processing. Reset by POC and LVI circuit power supply detection is automatically released when VDD VPOC or VDD VLVI after the reset, and program execution starts using the internal high-speed oscillation clock (see CHAPTER 24 POWER-ON-CLEAR CIRCUIT and CHAPTER 25 LOW-VOLTAGE DETECTOR) after reset processing. Cautions 1. For an external reset, input a low level for 10 s or more to the RESET pin. 2. During reset input, the X1 clock, XT1 clock, internal high-speed oscillation clock, and internal low-speed oscillation clock stop oscillating. External main system clock input and external subsystem clock input become invalid. 3. When the STOP mode is released by a reset, the STOP mode contents are held during reset input. However, the port pins become high-impedance, except for P130, which is set to lowlevel output. User's Manual U17397EJ4V0UD 557 558 Watchdog timer reset signal User's Manual U17397EJ4V0UD Figure 23-1. Block Diagram of Reset Function Internal bus Reset control flag register (RESF) WDTRF Set Clear LVIRF Set Clear CHAPTER 23 RESET FUNCTION RESET Reset signal to LVIM/LVIS register Power-on-clear circuit reset signal Low-voltage detector reset signal Reset signal Caution An LVI circuit internal reset does not reset the LVI circuit. Remarks 1. LVIM: Low-voltage detection register 2. LVIS: Low-voltage detection level selection register www..com CHAPTER 23 RESET FUNCTION www..com Figure 23-2. Timing of Reset by RESET Input Wait for oscillation accuracy stabilization (86 to 361 s) Internal high-speed oscillation clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected) CPU clock RESET Normal operation Reset period (oscillation stop) Reset processing (11 to 45 s) Normal operation (internal high-speed oscillation clock) Internal reset signal Delay Port pin (except P130) Port pin (P130) Delay (5 s (TYP.)) Hi-Z Note Note Set P130 to high-level output by software. Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected, the output signal of P130 can be dummy-output as the CPU reset signal. Figure 23-3. Timing of Reset Due to Watchdog Timer Overflow Wait for oscillation accuracy stabilization (86 to 361 s) Internal high-speed oscillation clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected) CPU clock Watchdog timer overflow Normal operation Reset period (oscillation stop) Reset processing (11 to 45 s) Normal operation (internal high-speed oscillation clock) Internal reset signal Port pin (except P130) Port pin (P130) Hi-Z Note Note Set P130 to high-level output by software. Caution A watchdog timer internal reset resets the watchdog timer. Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected, the output signal of P130 can be dummy-output as the CPU reset signal. User's Manual U17397EJ4V0UD 559 CHAPTER 23 RESET FUNCTION www..com Figure 23-4. Timing of Reset in STOP Mode by RESET Input STOP instruction execution Wait for oscillation accuracy stabilization (86 to 361 s) Internal high-speed oscillation clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected) Reset processing (11 to 45 s) CPU clock RESET Normal operation Stop status (oscillation stop) Reset period (oscillation stop) Normal operation (internal high-speed oscillation clock) Internal reset signal Delay Port pin (except P130) Port pin (P130) Delay (5 s (TYP.)) Hi-Z Note Note Set P130 to high-level output by software. Remarks 1. When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected, the output signal of P130 can be dummy-output as the CPU reset signal. 2. For the reset timing of the power-on-clear circuit and low-voltage detector, see CHAPTER 24 POWER-ON-CLEAR CIRCUIT and CHAPTER 25 LOW-VOLTAGE DETECTOR. 560 User's Manual U17397EJ4V0UD CHAPTER 23 RESET FUNCTION www..com Table 23-1. Operation Statuses During Reset Period Item System clock Main system clock fRH fX fEXCLK Subsystem clock fXT fEXCLKS fRL CPU Flash memory RAM Port (latch) 16-bit timer/event counter 8-bit timer/event counter 8-bit timer 00 01 50 51 H0 H1 Watch timer Watchdog timer Clock output Buzzer output A/D converter Serial interface UART0 UART6 CSI10 CSI11 CSIA0 IIC0 Multiplier/divider Power-on-clear function Low-voltage detection function External interrupt Operable Operation stopped Operation stopped Clock supply to the CPU is stopped. Operation stopped Operation stopped (pin is I/O port mode) Clock input invalid (pin is I/O port mode) Operation stopped (pin is I/O port mode) Clock input invalid (pin is I/O port mode) Operation stopped During Reset Period Remark fRH: fX: fEXCLK: fXT: fRL: Internal high-speed oscillation clock X1 oscillation clock External main system clock XT1 oscillation clock Internal low-speed oscillation clock fEXCLKS: External subsystem clock User's Manual U17397EJ4V0UD 561 CHAPTER 23 RESET FUNCTION www..com Table 23-2. Hardware Statuses After Reset Acknowledgment (1/3) Hardware Program counter (PC) After Reset Note 1 Acknowledgment The contents of the reset vector table (0000H, 0001H) are set. Undefined 02H Undefined Undefined 00H FFH 00H 0CH Note 3 Note 3 Note 2 Note 2 Stack pointer (SP) Program status word (PSW) RAM Data memory General-purpose registers Port registers (P0 to P7, P12 to P14) (output latches) Port mode registers (PM0 to PM7, PM12, PM14) Pull-up resistor option registers (PU0, PU1, PU3 to PU7, PU12, PU14) Internal expansion RAM size switching register (IXS) Internal memory size switching register (IMS) Memory bank select register (BANK) Clock operation mode select register (OSCCTL) Processor clock control register (PCC) Internal oscillation mode register (RCM) Main OSC control register (MOC) Main clock mode register (MCM) Oscillation stabilization time counter status register (OSTC) Oscillation stabilization time select register (OSTS) 16-bit timer/event counters 00, 01 Timer counters 00, 01 (TM00, TM01) Capture/compare registers 000, 010, 001, 011 (CR000, CR010, CR001, CR011) Mode control registers 00, 01 (TMC00, TMC01) Prescaler mode registers 00, 01 (PRM00, PRM01) Capture/compare control registers 00, 01 (CRC00, CRC01) Timer output control registers 00, 01 (TOC00, TOC01) CFH 00H 00H 01H 80H 80H 00H 00H 05H 0000H 0000H 00H 00H 00H 00H Notes 1. 2. 3. During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remain unchanged after reset. When a reset is executed in the standby mode, the pre-reset status is held even after reset. The initial values of the internal memory size switching register (IMS) and internal expansion RAM size switching register (IXS) after a reset release are constant (IMS = CFH, IXS = 0CH) in all the 78K0/KF2 products, regardless of the internal memory capacity. Therefore, after a reset is released, be sure to set the following values for each product. Flash Memory Version (78K0/KF2) IMS CCH CFH CCH Note 4 IXS 0AH 08H 04H 00H PD78F0544 PD78F0545 PD78F0546 PD78F0547, 78F0547D CCH 4. The ROM and RAM capacities of the products with the on-chip debug function can be debugged according to the debug target products. Set IMS and IXS according to the debug target products. 562 User's Manual U17397EJ4V0UD CHAPTER 23 RESET FUNCTION www..com Table 23-2. Hardware Statuses After Reset Acknowledgment (2/3) Hardware 8-bit timer/event counters 50, 51 Timer counters 50, 51 (TM50, TM51) Compare registers 50, 51 (CR50, CR51) Timer clock selection registers 50, 51 (TCL50, TCL51) Mode control registers 50, 51 (TMC50, TMC51) 8-bit timers H0, H1 Compare registers 00, 10, 01, 11 (CMP00, CMP10, CMP01, CMP11) Mode registers (TMHMD0, TMHMD1) Carrier control register 1 (TMCYC1) Watch timer Clock output/buzzer output controller Watchdog timer A/D converter Operation mode register (WTM) Clock output selection register (CKS) Enable register (WDTE) 10-bit A/D conversion result register (ADCR) 8-bit A/D conversion result register (ADCRH) Mode register (ADM) Analog input channel specification register (ADS) A/D port configuration register (ADPC) Serial interface UART0 Receive buffer register 0 (RXB0) Transmit shift register 0 (TXS0) Asynchronous serial interface operation mode register 0 (ASIM0) Asynchronous serial interface reception error status register 0 (ASIS0) Baud rate generator control register 0 (BRGC0) Serial interface UART6 Receive buffer register 6 (RXB6) Transmit buffer register 6 (TXB6) Asynchronous serial interface operation mode register 6 (ASIM6) Asynchronous serial interface reception error status register 6 (ASIS6) Asynchronous serial interface transmission status register 6 (ASIF6) Clock selection register 6 (CKSR6) Baud rate generator control register 6 (BRGC6) Asynchronous serial interface control register 6 (ASICL6) Input switch control register (ISC) Serial interfaces CSI10, CSI11 Transmit buffer registers 10, 11 (SOTB10, SOTB11) Serial I/O shift registers 10, 11 (SIO10, SIO11) Serial operation mode registers 10, 11 (CSIM10, CSIM11) Serial clock selection registers 10, 11 (CSIC10, CSIC11) Note 2 Status After Reset Acknowledgment 00H 00H 00H 00H 00H 00H 00H 00H 00H 1AH/9AH 0000H 00H 00H 00H 00H FFH FFH 01H 00H 1FH FFH FFH 01H 00H 00H 00H FFH 16H 00H 00H 00H 00H 00H Note 3 Note 1 Notes 1. 2. 3. During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remain unchanged after reset. 8-bit timer H1 only. The reset value of WDTE is determined by the option byte setting. User's Manual U17397EJ4V0UD 563 CHAPTER 23 RESET FUNCTION www..com Table 23-2. Hardware Statuses After Reset Acknowledgment (3/3) Hardware Status After Reset Acknowledgment Serial interface CSIA0 Serial operation mode specification register 0 (CSIMA0) Serial status register 0 (CSIS0) Serial trigger register 0 (CSIT0) Divisor value selection register 0 (BRGCA0) Automatic data transfer address point specification register 0 (ADTP0) Automatic data transfer interval specification register 0 (ADTI0) Serial I/O shift register 0 (SIOA0) Automatic data transfer address count register 0 (ADTC0) Serial interface IIC0 Shift register 0 (IIC0) Control register 0 (IICC0) Slave address register 0 (SVA0) Clock selection register 0 (IICCL0) Function expansion register 0 (IICX0) Status register 0 (IICS0) Flag register 0 (IICF0) Multiplier/divider Remainder data register 0 (SDR0) Multiplication/division data register A0 (MDA0H, MDA0L) Multiplication/division data register B0 (MDB0) Multiplier/divider control register 0 (DMUC0) Key interrupt Reset function Low-voltage detector Key return mode register (KRM) Reset control flag register (RESF) Low-voltage detection register (LVIM) Low-voltage detection level selection register (LVIS) Interrupt Request flag registers 0L, 0H, 1L, 1H (IF0L, IF0H, IF1L, IF1H) Mask flag registers 0L, 0H, 1L, 1H (MK0L, MK0H, MK1L, MK1H) Priority specification flag registers 0L, 0H, 1L, 1H (PR0L, PR0H, PR1L, PR1H) External interrupt rising edge enable register (EGP) External interrupt falling edge enable register (EGN) 00H 00H 00H 00H 00H 03H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 0000H 0000H 0000H 00H 00H 00H 00H Note 2 Note 1 Note 2 00H 00H Note 2 FFH FFH Notes 1. 2. During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remain unchanged after reset. These values vary depending on the reset source. Reset Source Register RESF WDTRF bit LVIRF bit LVIM LVIS Cleared (00H) Cleared (00H) Cleared (0) Cleared (0) Set (1) Held Cleared (00H) Held Set (1) Held RESET Input Reset by POC Reset by WDT Reset by LVI 564 User's Manual U17397EJ4V0UD CHAPTER 23 RESET FUNCTION www..com 23.1 Register for Confirming Reset Source Many internal reset generation sources exist in the 78K0/KF2. The reset control flag register (RESF) is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction. RESET input, reset by power-on-clear (POC) circuit, and reading RESF set RESF to 00H. Figure 23-5. Format of Reset Control Flag Register (RESF) Address: FFACH Symbol RESF After reset: 00H 7 0 6 0 Note R 5 0 4 WDTRF 3 0 2 0 1 0 0 LVIRF WDTRF 0 1 Internal reset request by watchdog timer (WDT) Internal reset request is not generated, or RESF is cleared. Internal reset request is generated. LVIRF 0 1 Internal reset request by low-voltage detector (LVI) Internal reset request is not generated, or RESF is cleared. Internal reset request is generated. Note The value after reset varies depending on the reset source. Caution Do not read data by a 1-bit memory manipulation instruction. The status of RESF when a reset request is generated is shown in Table 23-3. Table 23-3. RESF Status When Reset Request Is Generated Reset Source Flag WDTRF LVIRF Cleared (0) Cleared (0) Set (1) Held Held Set (1) RESET Input Reset by POC Reset by WDT Reset by LVI User's Manual U17397EJ4V0UD 565 www..com CHAPTER 24 POWER-ON-CLEAR CIRCUIT 24.1 Functions of Power-on-Clear Circuit The power-on-clear circuit (POC) has the following functions. * Generates internal reset signal at power on. In the 1.59 V POC mode (option byte: POCMODE = 0), the reset signal is released when the supply voltage (VDD) exceeds 1.59 V 0.15 V. In the 2.7 V/1.59 V POC mode (option byte: POCMODE = 1), the reset signal is released when the supply voltage (VDD) exceeds 2.7 V 0.2 V. * Compares supply voltage (VDD) and detection voltage (VPOC = 1.59 V 0.15 V), generates internal reset signal when VDD < VPOC. Caution If an internal reset signal is generated in the POC circuit, the reset control flag register (RESF) is cleared to 00H. Remark 78K0/KF2 incorporates multiple hardware functions that generate an internal reset signal. A flag that indicates the reset source is located in the reset control flag register (RESF) for when an internal reset signal is generated by the watchdog timer (WDT) or low-voltage-detector (LVI). RESF is not cleared to 00H and the flag is set to 1 when an internal reset signal is generated by WDT or LVI. For details of RESF, see CHAPTER 23 RESET FUNCTION. 566 User's Manual U17397EJ4V0UD CHAPTER 24 POWER-ON-CLEAR CIRCUIT www..com 24.2 Configuration of Power-on-Clear Circuit The block diagram of the power-on-clear circuit is shown in Figure 24-1. Figure 24-1. Block Diagram of Power-on-Clear Circuit VDD VDD + - Internal reset signal Reference voltage source 24.3 Operation of Power-on-Clear Circuit (1) In 1.59 V POC mode (option byte: POCMODE = 0) * An internal reset signal is generated on power application. When the supply voltage (VDD) exceeds the detection voltage (VPOC = 1.59 V 0.15 V), the reset status is released. * The supply voltage (VDD) and detection voltage (VPOC = 1.59 V 0.15 V) are compared. When VDD < VPOC, the internal reset signal is generated. It is released when VDD VPOC. (2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) * An internal reset signal is generated on power application. When the supply voltage (VDD) exceeds the detection voltage (VDDPOC = 2.7 V 0.2 V), the reset status is released. * The supply voltage (VDD) and detection voltage (VPOC = 1.59 V 0.15 V) are compared. When VDD < VPOC, the internal reset signal is generated. It is released when VDD VDDPOC. The timing of generation of the internal reset signal by the power-on-clear circuit and low-voltage detector is shown below. User's Manual U17397EJ4V0UD 567 CHAPTER 24 POWER-ON-CLEAR CIRCUIT www..com Figure 24-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector (1/2) (1) In 1.59 V POC mode (option byte: POCMODE = 0) Set LVI to be used for reset Supply voltage (VDD) VLVI 1.8 VNote 1 VPOC = 1.59 V (TYP.) 0.5 V/ms (MIN.)Note 2 Set LVI to be used for interrupt Set LVI to be used for reset 0V Wait for oscillation accuracy stabilization (86 to 361 s) Note 3 Internal high-speed oscillation clock (fRH) High-speed system clock (fXH) (when X1 oscillation is selected) Starting oscillation is specified by software. Note 3 Starting oscillation is specified by software. Starting oscillation is specified by software. Operation CPU stops Wait for voltage stabilization (1.93 to 5.39 ms) Normal operation Reset period (internal high-speed (oscillation oscillation clock)Note 4 stop) Normal operation Reset period Wait for voltage (internal high-speed (oscillation stabilization oscillation clock)Note 4 (1.93 to 5.39 ms) stop) Reset processing (11 to 45 s) Normal operation (internal high-speed oscillation clock)Note 4 Operation stops Reset processing (11 to 45 s) Internal reset signal Reset processing (11 to 45 s) Notes 1. The operation guaranteed range is 1.8 V VDD 5.5 V. To make the state at lower than 1.8 V reset state when the supply voltage falls, use the reset function of the low-voltage detector, or input the low level to the RESET pin. 2. If the voltage rises to 1.8 V at a rate slower than 0.5 V/ms (MIN.) on power application, input a low level to the RESET pin after power application and before the voltage reaches 1.8 V, or set the 2.7 V/1.59 V POC mode by using an option byte (POCMODE = 1). 3. 4. The internal voltage stabilization time includes the oscillation accuracy stabilization time of the internal high-speed oscillation clock. The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse of the stabilization time. Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 25 LOW-VOLTAGE DETECTOR). Remark VLVI: LVI detection voltage VPOC: POC detection voltage 568 User's Manual U17397EJ4V0UD CHAPTER 24 POWER-ON-CLEAR CIRCUIT www..com Figure 24-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector (2/2) (2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) Set LVI to be used for reset Supply voltage (VDD) VLVI VDDPOC = 2.7 V (TYP.) 1.8 VNote 1 VPOC = 1.59 V (TYP.) Set LVI to be used for interrupt Set LVI to be used for reset 0V Wait for oscillation accuracy stabilization (86 to 361 s) Internal high-speed oscillation clock (fRH) High-speed system clock (fXH) (when X1 oscillation is selected) Starting oscillation is specified by software. Starting oscillation is specified by software. Starting oscillation is specified by software. Wait for oscillation accuracy stabilization (86 to 361 s) Wait for oscillation accuracy stabilization (86 to 361 s) CPU Operation stops Normal operation Reset period (internal high-speed (oscillation stop) oscillation clock)Note 2 Reset processing (11 to 45 s) Normal operation (internal high-speed oscillation clock)Note 2 Reset processing (11 to 45 s) Reset period (oscillation stop) Normal operation (internal high-speed oscillation clock)Note 2 Reset processing (11 to 45 s) Operation stops Internal reset signal Notes 1. The operation guaranteed range is 1.8 V VDD 5.5 V. To make the state at lower than 1.8 V reset state when the supply voltage falls, use the reset function of the low-voltage detector, or input the low level to the RESET pin. 2. The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse of the stabilization time. Cautions 1. Set the low-voltage detector by software after the reset status is released (see CHAPTER 25 LOW-VOLTAGE DETECTOR). 2. A voltage oscillation stabilization time of 1.93 to 5.39 ms is required after the supply voltage reaches 1.59 V (TYP.). If the supply voltage rises from 1.59 V (TYP.) to 2.7 V (TYP.) within 1.93 ms, the power supply oscillation stabilization time of 0 to 5.39 ms is automatically generated before reset processing. Remark VLVI: LVI detection voltage VPOC: POC detection voltage User's Manual U17397EJ4V0UD 569 CHAPTER 24 POWER-ON-CLEAR CIRCUIT www..com 24.4 Cautions for Power-on-Clear Circuit In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection voltage (VPOC), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action. Reset Initialization processing <1> Power-on-clear ; Check the reset sourceNote 2 Initialize the port. Setting 8-bit timer H1 (to measure 50 ms) ; fPRS = Internal high-speed oscillation clock (8.4 MHz (MAX.)) (default) Source: fPRS (8.4 MHz (MAX.))/212, where comparison value = 102: 50 ms Timer starts (TMHE1 = 1). Note 1 Clearing WDT No 50 ms has passed? (TMIFH1 = 1?) Yes ; Setting of division ratio of system clock, such as setting of timer or A/D converter Initialization processing <2> Notes 1. 2. If reset is generated again during this period, initialization processing <2> is not started. A flowchart is shown on the next page. 570 User's Manual U17397EJ4V0UD CHAPTER 24 POWER-ON-CLEAR CIRCUIT www..com Figure 24-3. Example of Software Processing After Reset Release (2/2) * Checking reset source Check reset source WDTRF of RESF register = 1? Yes No Reset processing by watchdog timer LVIRF of RESF register = 1? Yes No Reset processing by low-voltage detector Power-on-clear/external reset generated User's Manual U17397EJ4V0UD 571 www..com CHAPTER 25 LOW-VOLTAGE DETECTOR 25.1 Functions of Low-Voltage Detector The low-voltage detector (LVI) has the following functions. * The LVI circuit compares the supply voltage (VDD) with the detection voltage (VLVI) or the input voltage from an external input pin (EXLVI) with the detection voltage (VEXLVI = 1.21 V (TYP.): fixed), and generates an internal reset or internal interrupt signal. * The supply voltage (VDD) or input voltage from an external input pin (EXLVI) can be selected by software. * Reset or interrupt function can be selected by software. * Detection levels (16 levels) of supply voltage can be changed by software. * Operable in STOP mode. The reset and interrupt signals are generated as follows depending on selection by software. Selection of Level Detection of Supply Voltage (VDD) (LVISEL = 0) Selects reset (LVIMD = 1). Generates an internal reset signal when VDD < VLVI and releases the reset signal when VDD VLVI. Selects interrupt (LVIMD = 0). Generates an internal interrupt signal when VDD drops lower than VLVI (VDD < VLVI) or when VDD becomes VLVI or higher (VDD VLVI). Selection Level Detection of Input Voltage from External Input Pin (EXLVI) (LVISEL = 1) Selects reset (LVIMD = 1). Generates an internal reset signal when EXLVI < VEXLVI and releases the reset signal when EXLVI VEXLVI. Selects interrupt (LVIMD = 0). Generates an internal interrupt signal when EXLVI drops lower than VEXLVI (EXLVI < VEXLVI) or when EXLVI becomes VEXLVI or higher (EXLVI VEXLVI). Remark LVISEL: Bit 2 of low-voltage detection register (LVIM) LVIMD: Bit 1 of LVIM While the low-voltage detector is operating, whether the supply voltage or the input voltage from an external input pin is more than or less than the detection level can be checked by reading the low-voltage detection flag (LVIF: bit 0 of LVIM). When the low-voltage detector is used to reset, bit 0 (LVIRF) of the reset control flag register (RESF) is set to 1 if reset occurs. For details of RESF, see CHAPTER 23 RESET FUNCTION. 572 User's Manual U17397EJ4V0UD CHAPTER 25 LOW-VOLTAGE DETECTOR www..com 25.2 Configuration of Low-Voltage Detector The block diagram of the low-voltage detector is shown in Figure 25-1. Figure 25-1. Block Diagram of Low-Voltage Detector VDD VDD Low-voltage detection level selector N-ch Internal reset signal Selector EXLVI/P120/ INTP0 + - Selector INTLVI 4 Reference voltage source LVIS3 LVIS2 LVIS1 LVIS0 Low-voltage detection level selection register (LVIS) Internal bus LVION LVISEL LVIMD LVIF Low-voltage detection register (LVIM) 25.3 Registers Controlling Low-Voltage Detector The low-voltage detector is controlled by the following registers. * Low-voltage detection register (LVIM) * Low-voltage detection level selection register (LVIS) * Port mode register 12 (PM12) (1) Low-voltage detection register (LVIM) This register sets low-voltage detection and the operation mode. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears LVIM to 00H. User's Manual U17397EJ4V0UD 573 CHAPTER 25 LOW-VOLTAGE DETECTOR www..com Figure 25-2. Format of Low-Voltage Detection Register (LVIM) Address: FFBEH Symbol LVIM <7> LVION After reset: 00H 6 0 R/WNote 1 5 0 4 0 3 0 <2> LVISEL <1> LVIMD <0> LVIF LVION 0 1 Notes 2, 3 Enables low-voltage detection operation Disables operation Enables operation LVISEL 0 1 Note 2 Voltage detection selection Detects level of supply voltage (VDD) Detects level of input voltage from external input pin (EXLVI) LVIMD 0 Note 2 Low-voltage detection operation mode (interrupt/reset) selection * LVISEL = 0: Generates an internal interrupt signal when the supply voltage (VDD) drops lower than the detection voltage (VLVI) (VDD < VLVI) or when VDD becomes VLVI or higher (VDD VLVI). * LVISEL = 1: Generates an interrupt signal when the input voltage from an external input pin (EXLVI) drops lower than the detection voltage (VEXLVI) (EXLVI < VEXLVI) or when EXLVI becomes VEXLVI or higher (EXLVI VEXLVI). 1 * LVISEL = 0: Generates an internal reset signal when the supply voltage (VDD) < detection voltage (VLVI) and releases the reset signal when VDD VLVI. * LVISEL = 1: Generates an internal reset signal when the input voltage from an external input pin (EXLVI) < detection voltage (VEXLVI) and releases the reset signal when EXLVI VEXLVI. LVIF 0 Note 4 Low-voltage detection flag * LVISEL = 0: Supply voltage (VDD) detection voltage (VLVI), or when operation is disabled * LVISEL = 1: Input voltage from external input pin (EXLVI) detection voltage (VEXLVI), or when operation is disabled 1 * LVISEL = 0: Supply voltage (VDD) < detection voltage (VLVI) * LVISEL = 1: Input voltage from external input pin (EXLVI) < detection voltage (VEXLVI) Notes 1. 2. 3. Bit 0 is read-only. LVION, LVIMD, and LVISEL are cleared to 0 in the case of a reset other than an LVI reset. These are not cleared to 0 in the case of an LVI reset. When LVION is set to 1, operation of the comparator in the LVI circuit is started. the voltage is confirmed at LVIF. Use software to wait for an operation stabilization time (10 s (MAX.)) when LVION is set to 1 until 4. The value of LVIF is output as the interrupt request signal INTLVI when LVION = 1 and LVIMD = 0. Cautions 1. To stop LVI, follow either of the procedures below. * When using 8-bit memory manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVION to 0. 2. Input voltage from external input pin (EXLVI) must be EXLVI < VDD. 574 User's Manual U17397EJ4V0UD CHAPTER 25 LOW-VOLTAGE DETECTOR www..com (2) Low-voltage detection level selection register (LVIS) This register selects the low-voltage detection level. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation input clears LVIS to 00H. Figure 25-3. Format of Low-Voltage Detection Level Selection Register (LVIS) Address: FFBFH Symbol LVIS 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 LVIS3 2 LVIS2 1 LVIS1 0 LVIS0 LVIS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 LVIS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 LVIS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LVIS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Detection level VLVI0 (4.24 V 0.1 V) VLVI1 (4.09 V 0.1 V) VLVI2 (3.93 V 0.1 V) VLVI3 (3.78 V 0.1 V) VLVI4 (3.62 V 0.1 V) VLVI5 (3.47 V 0.1 V) VLVI6 (3.32 V 0.1 V) VLVI7 (3.16 V 0.1 V) VLVI8 (3.01 V 0.1 V) VLVI9 (2.85 V 0.1 V) VLVI10 (2.70 V 0.1 V) VLVI11 (2.55 V 0.1 V) VLVI12 (2.39 V 0.1 V) VLVI13 (2.24 V 0.1 V) VLVI14 (2.08 V 0.1 V) VLVI15 (1.93 V 0.1 V) Cautions 1. Be sure to clear bits 4 to 7 to "0". 2. Do not change the value of LVIS during LVI operation. 3. When an input voltage from the external input pin (EXLVI) is detected, the detection voltage (VEXLVI = 1.21 V (TYP.)) is fixed. Therefore, setting of LVIS is not necessary. User's Manual U17397EJ4V0UD 575 CHAPTER 25 LOW-VOLTAGE DETECTOR www..com (3) Port mode register 12 (PM12) When using the P120/EXLVI/INTP0 pin for external low-voltage detection potential input, set PM120 to 1. At this time, the output latch of P120 may be 0 or 1. PM12 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PM12 to FFH. Figure 25-4. Format of Port Mode Register 12 (PM12) Address: FF2CH Symbol PM12 7 1 After reset: FFH 6 1 R/W 5 1 4 PM124 3 PM123 2 PM122 1 PM121 0 PM120 PM12n 0 1 P12n pin I/O mode selection (n = 0 to 4) Output mode (output buffer on) Input mode (output buffer off) 25.4 Operation of Low-Voltage Detector The low-voltage detector can be used in the following two modes. (1) Used as reset (LVIMD = 1) * If LVISEL = 0, compares the supply voltage (VDD) and detection voltage (VLVI), generates an internal reset signal when VDD < VLVI, and releases internal reset when VDD VLVI. * If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and detection voltage (VEXLVI = 1.21 V (TYP.)), generates an internal reset signal when EXLVI < VEXLVI, and releases internal reset when EXLVI VEXLVI. (2) Used as interrupt (LVIMD = 0) * If LVISEL = 0, compares the supply voltage (VDD) and detection voltage (VLVI). When VDD drops lower than VLVI (VDD < VLVI) or when VDD becomes VLVI or higher (VDD VLVI), generates an interrupt signal (INTLVI). * If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and detection voltage (VEXLVI = 1.21 V (TYP.)). When EXLVI drops lower than VEXLVI (EXLVI < VEXLVI) or when EXLVI becomes VEXLVI or higher (EXLVI VEXLVI), generates an interrupt signal (INTLVI). While the low-voltage detector is operating, whether the supply voltage or the input voltage from an external input pin is more than or less than the detection level can be checked by reading the low-voltage detection flag (LVIF: bit 0 of LVIM). Remark LVIMD: Bit 1 of low-voltage detection register (LVIM) LVISEL: Bit 2 of LVIM 576 User's Manual U17397EJ4V0UD CHAPTER 25 LOW-VOLTAGE DETECTOR www..com 25.4.1 When used as reset (1) When detecting level of supply voltage (VDD) * When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage (VDD)) (default value). <3> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection register (LVIS). <4> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <5> Use software to wait for an operation stabilization time (10 s (MAX.)). <6> Wait until it is checked that (supply voltage (VDD) detection voltage (VLVI)) by bit 0 (LVIF) of LVIM. <7> Set bit 1 (LVIMD) of LVIM to 1 (generates reset when the level is detected). Figure 25-5 shows the timing of the internal reset signal generated by the low-voltage detector. The numbers in this timing chart correspond to <1> to <7> above. Cautions 1. <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately after the processing in <4>. 2. If supply voltage (VDD) detection voltage (VLVI) when LVIMD is set to 1, an internal reset signal is not generated. * When stopping operation Either of the following procedures must be executed. * When using 8-bit memory manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVIMD to 0 and then LVION to 0. User's Manual U17397EJ4V0UD 577 CHAPTER 25 LOW-VOLTAGE DETECTOR www..com Figure 25-5. Timing of Low-Voltage Detector Internal Reset Signal Generation (Detects Level of Supply Voltage (VDD)) (1/2) (1) In 1.59 V POC mode (option byte: POCMODE = 0) Supply voltage (VDD) VLVI VPOC = 1.59 V (TYP.) Time LVIMK flag Note 1 (set by software) H <1> <3> LVISEL flag (set by software) L <2> LVION flag (set by software) Not cleared <4> Not cleared Clear <5> Wait time LVIF flag <6> LVIMD flag (set by software) Note 2 Clear Not cleared Not cleared Clear <7> LVIRF flagNote 3 LVI reset signal Cleared by software POC reset signal Cleared by software Internal reset signal Notes 1. 2. 3. The LVIMK flag is set to "1" by reset signal generation. The LVIF flag may be set (1). LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 23 RESET FUNCTION. Remark <1> to <7> in Figure 25-5 above correspond to <1> to <7> in the description of "When starting operation" in 25.4.1 (1) When detecting level of supply voltage (VDD). 578 User's Manual U17397EJ4V0UD CHAPTER 25 LOW-VOLTAGE DETECTOR www..com Figure 25-5. Timing of Low-Voltage Detector Internal Reset Signal Generation (Detects Level of Supply Voltage (VDD)) (2/2) (2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) Supply voltage (VDD) VLVI 2.7 V (TYP.) VPOC = 1.59 V (TYP.) Time LVIMK flag (set by software) HNote 1 <1> <3> L <2> Not cleared <4> Clear <5> Wait time LVIF flag <6> LVIMD flag (set by software) Note 2 LVISEL flag (set by software) LVION flag (set by software) Not cleared Clear Not cleared Not cleared Clear <7> LVIRF flagNote 3 LVI reset signal Cleared by software POC reset signal Cleared by software Internal reset signal Notes 1. 2. 3. The LVIMK flag is set to "1" by reset signal generation. The LVIF flag may be set (1). LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 23 RESET FUNCTION. Remark <1> to <7> in Figure 25-5 above correspond to <1> to <7> in the description of "When starting operation" in 25.4.1 (1) When detecting level of supply voltage (VDD). User's Manual U17397EJ4V0UD 579 CHAPTER 25 LOW-VOLTAGE DETECTOR www..com (2) When detecting level of input voltage from external input pin (EXLVI) * When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 1 (detects level of input voltage from external input pin (EXLVI)). <3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <4> Use software to wait for an operation stabilization time (10 s (MAX.)Note). <5> Wait until it is checked that (input voltage from external input pin (EXLVI) detection voltage (VEXLVI = 1.21 V (TYP.))) by bit 0 (LVIF) of LVIM. <6> Set bit 1 (LVIMD) of LVIM to 1 (generates reset signal when the level is detected). Figure 25-6 shows the timing of the internal reset signal generated by the low-voltage detector. The numbers in this timing chart correspond to <1> to <6> above. Cautions 1. <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately after the processing in <3>. 2. If input voltage from external input pin (EXLVI) detection voltage (VEXLVI = 1.21 V (TYP.)) when LVIMD is set to 1, an internal reset signal is not generated. 3. Input voltage from external input pin (EXLVI) must be EXLVI < VDD. * When stopping operation Either of the following procedures must be executed. * When using 8-bit memory manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVIMD to 0 and then LVION to 0. 580 User's Manual U17397EJ4V0UD CHAPTER 25 LOW-VOLTAGE DETECTOR www..com Figure 25-6. Timing of Low-Voltage Detector Internal Reset Signal Generation (Detects Level of Input Voltage from External Input Pin (EXLVI)) Input voltage from external input pin (EXLVI) LVI detection voltage (VEXLVI) Time LVIMK flag (set by software) HNote 1 <1> Not cleared <2> Not cleared Not cleared LVISEL flag (set by software) LVION flag (set by software) <3> Not cleared Not cleared Not cleared <4> Wait time LVIF flag <5> LVIMD flag (set by software) Note 2 Not cleared <6> Not cleared Not cleared LVIRF flagNote 3 LVI reset signal Cleared by software Internal reset signal Cleared by software Notes 1. 2. 3. The LVIMK flag is set to "1" by reset signal generation. The LVIF flag may be set (1). LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 23 RESET FUNCTION. Remark <1> to <6> in Figure 25-6 above correspond to <1> to <6> in the description of "When starting operation" in 25.4.1 (2) When detecting level of input voltage from external input pin (EXLVI). User's Manual U17397EJ4V0UD 581 CHAPTER 25 LOW-VOLTAGE DETECTOR www..com 25.4.2 When used as interrupt (1) When detecting level of supply voltage (VDD) * When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage (VDD)) (default value). <3> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection register (LVIS). <4> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <5> Use software to wait for an operation stabilization time (10 s (MAX.)). <6> Confirm that "supply voltage (VDD) detection voltage (VLVI)" when detecting the falling edge of VDD, or "supply voltage (VDD) < detection voltage (VLVI)" when detecting the rising edge of VDD, at bit 0 (LVIF) of LVIM. <7> Clear the interrupt request flag of LVI (LVIIF) to 0. <8> Release the interrupt mask flag of LVI (LVIMK). <9> Clear bit 1 (LVIMD) of LVIM to 0 (generates interrupt signal when the level is detected) (default value). <10> Execute the EI instruction (when vector interrupts are used). Figure 25-7 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in this timing chart correspond to <1> to <9> above. * When stopping operation Either of the following procedures must be executed. * When using 8-bit memory manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVION to 0. 582 User's Manual U17397EJ4V0UD CHAPTER 25 LOW-VOLTAGE DETECTOR www..com Figure 25-7. Timing of Low-Voltage Detector Interrupt Signal Generation (Detects Level of Supply Voltage (VDD)) (1/2) (1) In 1.59 V POC mode (option byte: POCMODE = 0) Supply voltage (VDD) VLVI VPOC = 1.59 V (TYP.) Time LVIMK flag (set by software) <1> Note 1 <8> Cleared by software <3> LVISEL flag (set by software) LVION flag (set by software) L <2> <4> <5> Wait time LVIF flag <6> Note 2 INTLVI Note 2 LVIIF flag Note 2 LVIMD flag (set by software) L <7> Cleared by software <9> Internal reset signal Notes 1. 2. Remark The LVIMK flag is set to "1" by reset signal generation. The interrupt request signal (INTLVI) is generated and the LVIF and LVIIF flags may be set (1). <1> to <9> in Figure 25-7 above correspond to <1> to <9> in the description of "When starting operation" in 25.4.2 (1) When detecting level of supply voltage (VDD). User's Manual U17397EJ4V0UD 583 CHAPTER 25 LOW-VOLTAGE DETECTOR www..com Figure 25-7. Timing of Low-Voltage Detector Interrupt Signal Generation (Detects Level of Supply Voltage (VDD)) (2/2) (2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) Supply voltage (VDD) VLVI 2.7 V(TYP.) VPOC = 1.59 V (TYP.) Time LVIMK flag (set by software) <1> Note 1 <8> Cleared by software <3> LVISEL flag (set by software) LVION flag (set by software) L <2> <4> <5> Wait time LVIF flag <6> Note 2 INTLVI Note 2 LVIIF flag <7> Cleared by software LVIMD flag (set by software) Note 2 L <9> Internal reset signal Notes 1. 2. Remark The LVIMK flag is set to "1" by reset signal generation. The interrupt request signal (INTLVI) is generated and the LVIF and LVIIF flags may be set (1). <1> to <9> in Figure 25-7 above correspond to <1> to <9> in the description of "When starting operation" in 25.4.2 (1) When detecting level of supply voltage (VDD). 584 User's Manual U17397EJ4V0UD CHAPTER 25 LOW-VOLTAGE DETECTOR www..com (2) When detecting level of input voltage from external input pin (EXLVI) * When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 1 (detects level of input voltage from external input pin (EXLVI)). <3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <4> Use software to wait for an operation stabilization time (10 s (MAX.)). <5> Confirm that "input voltage from external input pin (EXLVI) detection voltage (VEXLVI = 1.21 V (TYP.)" when detecting the falling edge of EXLVI, or "input voltage from external input pin (EXLVI) < detection voltage (VEXLVI = 1.21 V (TYP.)" when detecting the rising edge of EXLVI, at bit 0 (LVIF) of LVIM. <6> Clear the interrupt request flag of LVI (LVIIF) to 0. <7> Release the interrupt mask flag of LVI (LVIMK). <8> Clear bit 1 (LVIMD) of LVIM to 0 (generates interrupt signal when the level is detected) (default value). <9> Execute the EI instruction (when vector interrupts are used). Figure 25-8 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in this timing chart correspond to <1> to <8> above. Caution Input voltage from external input pin (EXLVI) must be EXLVI < VDD. * When stopping operation Either of the following procedures must be executed. * When using 8-bit memory manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVION to 0. User's Manual U17397EJ4V0UD 585 CHAPTER 25 LOW-VOLTAGE DETECTOR www..com Figure 25-8. Timing of Low-Voltage Detector Interrupt Signal Generation (Detects Level of Input Voltage from External Input Pin (EXLVI)) Input voltage from external input pin (EXLVI) VEXLVI Time LVIMK flag (set by software) <1> Note 1 <7> Cleared by software LVISEL flag (set by software) LVION flag (set by software) <2> <3> <4> Wait time LVIF flag <5> Note 2 INTLVI Note 2 LVIIF flag Note 2 LVIMD flag (set by software) L <6> Cleared by software <8> Notes 1. 2. Remark The LVIMK flag is set to "1" by reset signal generation. The interrupt request signal (INTLVI) is generated and the LVIF and LVIIF flags may be set (1). <1> to <8> in Figure 25-8 above correspond to <1> to <8> in the description of "When starting operation" in 25.4.2 (2) When detecting level of input voltage from external input pin (EXLVI). 586 User's Manual U17397EJ4V0UD CHAPTER 25 LOW-VOLTAGE DETECTOR www..com 25.5 Cautions for Low-Voltage Detector In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVI detection voltage (VLVI), the operation is as follows depending on how the low-voltage detector is used. (1) When used as reset The system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action (1) below. (2) When used as interrupt Interrupt requests may be frequently generated. Take (b) of action (2) below. User's Manual U17397EJ4V0UD 587 CHAPTER 25 LOW-VOLTAGE DETECTOR www..com Figure 25-9. Example of Software Processing After Reset Release (1/2) * If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage Reset Initialization processing <1> LVI reset Setting LVI ; Check the reset sourceNote Initialize the port. ; Setting of detection level by LVIS The low-voltage detector operates (LVION = 1). Setting 8-bit timer H1 (to measure 50 ms) ; fPRS = Internal high-speed oscillation clock (8.4 MHz (MAX.)) (default) Source: fPRS (8.4 MHz (MAX.))/212, Where comparison value = 102: 50 ms Timer starts (TMHE1 = 1). Clearing WDT Detection voltage or higher (LVIF = 0?) Yes No LVIF = 0 ; The low-voltage detection flag is cleared. Restarting timer H1 (TMHE1 = 0 TMHE1 = 1) ; The timer counter is cleared and the timer is started. No 50 ms has passed? (TMIFH1 = 1?) Yes ; Setting of division ratio of system clock, such as setting of timer or A/D converter Initialization processing <2> Note A flowchart is shown on the next page. 588 User's Manual U17397EJ4V0UD CHAPTER 25 LOW-VOLTAGE DETECTOR www..com Figure 25-9. Example of Software Processing After Reset Release (2/2) * Checking reset source Check reset source WDTRF of RESF register = 1? Yes No Reset processing by watchdog timer LVIRF of RESF register = 1? No Yes Power-on-clear/external reset generated Reset processing by low-voltage detector User's Manual U17397EJ4V0UD 589 www..com CHAPTER 26 OPTION BYTE 26.1 Functions of Option Bytes The flash memory at 0080H to 0084H of the 78K0/KF2 is an option byte area. When power is turned on or when the device is restarted from the reset status, the device automatically references the option bytes and sets specified functions. When using the product, be sure to set the following functions by using the option bytes. When the boot swap operation is used during self-programming, 0080H to 0084H are switched to 1080H to 1084H. Therefore, set values that are the same as those of 0080H to 0084H to 1080H to 1084H in advance. Caution Be sure to set 00H to 0082H and 0083H (0082H/1082H and 0083H/1083H when the boot swap function is used). (1) 0080H/1080H Internal low-speed oscillator operation * Can be stopped by software * Cannot be stopped Watchdog timer interval time setting Watchdog timer counter operation * Enabled counter operation * Disabled counter operation Watchdog timer window open period setting Caution Set a value that is the same as that of 0080H to 1080H because 0080H and 1080H are switched during the boot swap operation. (2) 0081H/1081H Selecting POC mode * During 2.7 V/1.59 V POC mode operation (POCMODE = 1) The device is in the reset state upon power application and until the supply voltage reaches 2.7 V (TYP.). It is released from the reset state when the voltage exceeds 2.7 V (TYP.). After that, POC is not detected at 2.7 V but is detected at 1.59 V (TYP.). If the supply voltage rises to 1.8 V after power application at a pace slower than 0.5 V/ms (MIN.), use of the 2.7 V/1.59 V POC mode is recommended. * During 1.59 V POC mode operation (POCMODE = 0) The device is in the reset state upon power application and until the supply voltage reaches 1.59 V (TYP.). It is released from the reset state when the voltage exceeds 1.59 V (TYP.). After that, POC is detected at 1.59 V (TYP.), in the same manner as on power application. Caution POCMODE can only be written by using a dedicated flash memory programmer. It cannot be set during self-programming or boot swap operation during self-programming (at this time, 1.59 V POC mode (default) is set). However, because the value of 1081H is copied to 0081H during the boot swap operation, it is recommended to set a value that is the same as that of 0081H to 1081H when the boot swap function is used. 590 User's Manual U17397EJ4V0UD CHAPTER 26 OPTION BYTE www..com (3) 0084H/1084H On-chip debug operation control * Disabling on-chip debug operation * Enabling on-chip debug operation and erasing data of the flash memory in case authentication of the onchip debug security ID fails * Enabling on-chip debug operation and not erasing data of the flash memory even in case authentication of the on-chip debug security ID fails Cautions 1. Be sure to set 00H (disabling on-chip debug operation) to 0084H for products not equipped with the on-chip debug function (PD78F0544, 78F0545, 78F0546, and 78F0547). Also set 00H to 1084H because 0084H and 1084H are switched during the boot operation. 2. To use the on-chip debug function with a product equipped with the on-chip debug function (PD78F0547D), set 02H or 03H to 0084H. Set a value that is the same as that of 0084H to 1084H because 0084H and 1084H are switched during the boot operation. User's Manual U17397EJ4V0UD 591 CHAPTER 26 OPTION BYTE www..com 26.2 Format of Option Byte The format of the option byte is shown below. Figure 26-1. Format of Option Byte (1/2) Address: 0080H/1080H 7 0 WINDOW1 0 0 1 1 WDTON 0 1 WDCS2 0 0 0 0 1 1 1 1 LSROSC 0 1 Note 6 WINDOW1 WINDOW0 0 1 0 1 25% 50% 75% 5 WINDOW0 4 WDTON 3 WDCS2 2 WDCS1 1 WDCS0 0 LSROSC Watchdog timer window open period 100% Operation control of watchdog timer counter/illegal access detection Counter operation disabled (counting stopped after reset), illegal access detection operation disabled Counter operation enabled (counting started after reset), illegal access detection operation enabled WDCS1 0 0 1 1 0 0 1 1 WDCS0 0 1 0 1 0 1 0 1 2 /fRL (3.88 ms) 2 /fRL (7.76 ms) 2 /fRL (15.52 ms) 2 /fRL (31.03 ms) 2 /fRL (62.06 ms) 2 /fRL (124.12 ms) 2 /fRL (248.24 ms) 2 /fRL (496.48 ms) Internal low-speed oscillator operation Can be stopped by software (stopped when 1 is written to bit 0 (LSRSTOP) of RCM register) Cannot be stopped (not stopped even if 1 is written to LSRSTOP bit) 17 16 15 14 13 12 11 10 Watchdog timer overflow time Note Set a value that is the same as that of 0080H to 1080H because 0080H and 1080H are switched during the boot swap operation. Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0 is prohibited. 2. The watchdog timer continues its operation during self-programming and EEPROM emulation of the flash memory. During processing, the interrupt acknowledge time is delayed. Set the overflow time and window size taking this delay into consideration. 3. If LSROSC = 0 (oscillation can be stopped by software), the count clock is not supplied to the watchdog timer in the HALT and STOP modes, regardless of the setting of bit 0 (LSRSTOP) of the internal oscillation mode register (RCM). When 8-bit timer H1 operates with the internal low-speed oscillation clock, the count clock is supplied to 8-bit timer H1 even in the HALT/STOP mode. 4. Be sure to clear bit 7 to 0. Remarks 1. 2. fRL: Internal low-speed oscillation clock frequency ( ): fRL = 264 kHz (MAX.) 592 User's Manual U17397EJ4V0UD CHAPTER 26 OPTION BYTE www..com Figure 26-1. Format of Option Byte (2/2) Address: 0081H/1081H 7 0 POCMODE 0 1 1.59 V POC mode (default) 2.7 V/1.59 V POC mode Notes 1, 2 6 0 5 0 4 0 3 0 POC mode selection 2 0 1 0 0 POCMODE Notes 1. POCMODE can only be written by using a dedicated flash memory programmer. It cannot be set during self-programming or boot swap operation during self-programming (at this time, 1.59 V POC mode (default) is set). However, because the value of 1081H is copied to 0081H during the boot swap operation, it is recommended to set a value that is the same as that of 0081H to 1081H when the boot swap function is used. 2. To change the setting for the POC mode, set the value to 0081H again after batch erasure (chip erasure) of the flash memory. The setting cannot be changed after the memory of the specified block is erased. Caution Be sure to clear bits 7 to 1 to "0". Address: 0082H/1082H, 0083H/1083H 7 0 6 0 Note 5 0 4 0 3 0 2 0 1 0 0 0 Note Be sure to set 00H to 0082H and 0083H, as these addresses are reserved areas. Also set 00H to 1082H and 1083H because 0082H and 0083H are switched with 1082H and 1083H when the boot swap operation is used. Address: 0084H/1084H 7 0 OCDEN1 0 0 1 1 Notes1, 2 6 0 OCDEN0 0 1 0 1 5 0 4 0 3 0 2 0 1 OCDEN1 0 OCDEN0 On-chip debug operation control Operation disabled Setting prohibited Operation enabled. Does not erase data of the flash memory in case authentication of the on-chip debug security ID fails. Operation enabled. Erases data of the flash memory in case authentication of the on-chip debug security ID fails. Notes 1. Be sure to set 00H (on-chip debug operation disabled) to 0084H for products not equipped with the onchip debug function (PD78F0544, 78F0545, 78F0546, and 78F0547). because 0084H and 1084H are switched during the boot swap operation. Also set 00H to 1084H 2. To use the on-chip debug function with a product equipped with the on-chip debug function (PD78F0547D), set 02H or 03H to 0084H. Set a value that is the same as that of 0084H to 1084H because 0084H and 1084H are switched during the boot swap operation. Remark For the on-chip debug security ID, see CHAPTER 28 ON-CHIP DEBUG FUNCTION (PD78F0547D ONLY). User's Manual U17397EJ4V0UD 593 CHAPTER 26 OPTION BYTE www..com Here is an example of description of the software for setting the option bytes. OPT CSEG AT 0080H 30H ; Enables watchdog timer operation (illegal access detection operation), ; Window open period of watchdog timer: 50%, ; Overflow time of watchdog timer: 210/fRL, ; Internal low-speed oscillator can be stopped by software. OPTION: DB DB DB DB DB 00H 00H 00H 00H ; 1.59 V POC mode ; Reserved area ; Reserved area ; On-chip debug operation disabled Remark Referencing of the option byte is performed during reset processing. For the reset processing timing, see CHAPTER 23 RESET FUNCTION. 594 User's Manual U17397EJ4V0UD www..com CHAPTER 27 FLASH MEMORY The 78K0/KF2 incorporates the flash memory to which a program can be written, erased, and overwritten while mounted on the board. 27.1 Internal Memory Size Switching Register The internal memory capacity can be selected using the internal memory size switching register (IMS). IMS is set by an 8-bit memory manipulation instruction. Reset signal generation sets IMS to CFH. Caution Be sure to set each product to the values shown in Table 27-1 after a reset release. Figure 27-1. Format of Internal Memory Size Switching Register (IMS) Address: FFF0H Symbol IMS After reset: CFH 7 RAM2 6 RAM1 R/W 5 RAM0 4 0 3 ROM3 2 ROM2 1 ROM1 0 ROM0 RAM2 1 RAM1 1 Other than above RAM0 0 Internal high-speed RAM capacity selection 1024 bytes Setting prohibited ROM3 1 1 ROM2 1 1 ROM1 0 1 ROM0 0 1 48 KB 60 KB Internal ROM capacity selection Other than above Setting prohibited Caution To set the memory size, set IMS and then IXS. Set the memory size so that the internal ROM and internal expansion RAM areas do not overlap. Table 27-1. Internal Memory Size Switching Register Settings Flash Memory Versions (78K0/KF2) IMS Setting CCH CFH CCH Note1 Note2 Note2 PD78F0544 PD78F0545 PD78F0546 PD78F0547, 78F0547D CCH Notes 1. 2. The internal ROM capacity of the products with the on-chip debug function can be debugged according to the debug target products. Set IMS according to the debug target products. The PD78F0546, 78F0547, and 78F0547D have internal ROMs of 96 KB and 128 KB, respectively. However, the set value of IMS of these devices is the same as those of the 48 KB product because memory banks are used. For how to set the memory banks, see 4.2 Memory Bank Select Register (BANK). User's Manual U17397EJ4V0UD 595 CHAPTER 27 FLASH MEMORY www..com 27.2 Internal Expansion RAM Size Switching Register The internal expansion RAM capacity can be selected using the internal expansion RAM size switching register (IXS). IXS is set by an 8-bit memory manipulation instruction. Reset signal generation sets IXS to 0CH. Caution Be sure to set each product to the values shown in Table 27-2 after a reset release. Figure 27-2. Format of Internal Expansion RAM Size Switching Register (IXS) Address: FFF4H Symbol IXS After reset: 0CH 7 0 6 0 R/W 5 0 4 IXRAM4 3 IXRAM3 2 IXRAM2 1 IXRAM1 0 IXRAM0 IXRAM4 0 0 0 0 IXRAM3 1 1 0 0 IXRAM2 0 0 1 0 Other than above IXRAM1 1 0 0 0 IXRAM0 0 0 0 0 Internal expansion RAM capacity selection 1024 bytes 2048 bytes 4096 bytes 6144 bytes Setting prohibited Caution To set memory size, set IMS and then IXS. Set memory size so that the internal ROM area and internal expansion RAM area do not overlap. Table 27-2. Internal Expansion RAM Size Switching Register Settings Flash Memory Versions (78K0/KF2) IXS Setting 0AH 08H 04H Note PD78F0544 PD78F0545 PD78F0546 PD78F0547, 78F0547D 00H Note The internal expansion RAM capacity of the products with the on-chip debug function can be debugged according to the debug target products. Set IXS according to the debug target products. 596 User's Manual U17397EJ4V0UD CHAPTER 27 FLASH MEMORY www..com 27.3 Writing with Flash memory programmer Data can be written to the flash memory on-board or off-board, by using a dedicated flash memory programmer. (1) On-board programming The contents of the flash memory can be rewritten after the 78K0/KF2 has been mounted on the target system. The connectors that connect the dedicated flash memory programmer must be mounted on the target system. (2) Off-board programming Data can be written to the flash memory with a dedicated program adapter (FA series) before the 78K0/KF2 is mounted on the target system. Remark The FA series is a product of Naito Densei Machida Mfg. Co., Ltd. Table 27-3. Wiring Between 78K0/KF2 and Dedicated Flash memory programmer Pin Configuration of Dedicated Flash memory programmer Signal Name SI/RxD SO/TxD SCK CLK I/O Input Output Output Output Pin Function Receive signal Transmit signal Transfer clock Clock to 78K0/KF2 With CSI10 Pin Name SO10/P12 SI10/RxD0/P11 SCK10/TxD0/P10 - Note 1 With UART6 Pin No. 52 53 54 - Pin Name TxD6/P13 RxD6/P14 - Note 2 Pin No. 51 50 - Note 2 /RESET FLMD0 VDD Output Output I/O Reset signal Mode signal VDD voltage generation/ power monitoring RESET FLMD0 VDD EVDD AVREF 10 13 19 20 59 17 18 60 RESET FLMD0 VDD EVDD AVREF VSS EVSS AVSS 10 13 19 20 59 17 18 60 GND - Ground VSS EVSS AVSS Notes 1. 2. Only the internal high-speed oscillation clock (fRH) can be used when CSI10 is used. Only the X1 clock (fX) or external main system clock (fEXCLK) can be used when UART6 is used. When using the clock output of the dedicated flash memory programmer, pin connection varies depending on the type of the dedicated flash memory programmer used. * PG-FP4, FL-PR4: * PG-FPL3, FP-LITE3: Connect CLK of the programmer to EXCLK/X2/P122 (pin 14). Connect CLK of the programmer to X1/P121 (pin 15), and connect its inverted signal to X2/EXCLK/P122 (pin 14). User's Manual U17397EJ4V0UD 597 CHAPTER 27 FLASH MEMORY www..com Examples of the recommended connection when using the adapter for flash memory writing are shown below. Figure 27-3. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10) Mode VDD (2.7 to 5.5 V) GND 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10 50 11 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GND VDD VDD2 SI SO SCK CLK /RESET FLMD0 WRITER INTERFACE 598 User's Manual U17397EJ4V0UD CHAPTER 27 FLASH MEMORY www..com Figure 27-4. Example of Wiring Adapter for Flash Memory Writing in UART (UART6) Mode VDD (2.7 to 5.5 V) GND 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10 50 11 49 12 48 13 47 14 Note 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GND VDD VDD2 SI SO SCK CLKNote /RESET FLMD0 WRITER INTERFACE Note The above figure illustrates an example of wiring when using the clock output from the PG-FP4 or FL-PR4. When using the clock output from the PG-FPL3 or FP-LITE3, connect CLK to X1/P121 (pin 15), and connect its inverted signal to X2/EXCLK/P122 (pin 14). User's Manual U17397EJ4V0UD 599 CHAPTER 27 FLASH MEMORY www..com 27.4 Programming Environment The environment required for writing a program to the flash memory of the 78K0/KF2 is illustrated below. Figure 27-5. Environment for Writing Program to Flash Memory FLMD0 XXXX YYYY Bxxxxx Cxxxxxx XXXX XXXXXX RS-232C USB Axxxx VDD PG-FP4 (Flash Pro4) XXXXX XXX YYY STATVE VSS RESET 78K0/KF2 Dedicated flash memory programmer Host machine CSI10/UART6 A host machine that controls the dedicated flash memory programmer is necessary. To interface between the dedicated flash memory programmer and the 78K0/KF2, CSI10 or UART6 is used for manipulation such as writing and erasing. To write the flash memory off-board, a dedicated program adapter (FA series) is necessary. 27.5 Communication Mode Communication between the dedicated flash memory programmer and the 78K0/KF2 is established by serial communication via CSI10 or UART6 of the 78K0/KF2. (1) CSI10 Transfer rate: 2.4 kHz to 2.5 MHz Figure 27-6. Communication with Dedicated Flash memory programmer (CSI10) FLMD0 VDD GND XXXX YYYY FLMD0 VDD/EVDD/AVREF VSS/EVSS/AVSS RESET SO10 SI10 SCK10 78K0/KF2 Bxxxxx Cxxxxxx XXXXXX Axxxx XXX YYY PG-FP4 (Flash Pro4) XXXXX STATVE /RESET SI/RxD XXXX Dedicated flash memory programmer SO/TxD SCK 600 User's Manual U17397EJ4V0UD CHAPTER 27 FLASH MEMORY www..com (2) UART6 Transfer rate: 115200 bps Figure 27-7. Communication with Dedicated Flash memory programmer (UART6) FLMD0 VDD GND XXXX YYYY FLMD0 VDD/EVDD/AVREF VSS/EVSS/AVSS RESET TxD6 RxD6 EXCLKNote 78K0/KF2 Bxxxxx Cxxxxxx XXXXXX Axxxx XXX YYY PG-FP4 (Flash Pro4) XXXXX STATVE /RESET SI/RxD XXXX Dedicated flash memory programmer SO/TxD CLKNote Note The above figure illustrates an example of wiring when using the clock output from the PG-FP4 or FL-PR4. When using the clock output from the PG-FPL3 or FP-LITE3, connect CLK to X1/P121 (pin 15), and connect its inverted signal to X2/EXCLK/P122 (pin 14). CLK X1 X2 The dedicated flash memory programmer generates the following signals for the 78K0/KF2. For details, refer to the user's manual for the PG-FP4, FL-PR4, PG-FPL3, or FP-LITE3. Table 27-4. Pin Connection Dedicated Flash memory programmer Signal Name FLMD0 VDD GND CLK /RESET SI/RxD SO/TxD SCK Output Output Input Output Output I/O Output I/O - Mode signal VDD voltage generation/power monitoring Ground Clock output to 78K0/KF2 Reset signal Receive signal Transmit signal Transfer clock Pin Function 78K0/KF2 Pin Name FLMD0 VDD, EVDD, AVREF VSS, EVSS, AVSS Note 1 RESET SO10/TxD6 SI10/RxD6 SCK10 x x Note 2 Note 1 Connection CSI10 UART6 Notes 1. Only the X1 clock (fX) or external main system clock (fEXCLK) can be used when UART6 is used. When using the clock output of the dedicated flash memory programmer, pin connection varies depending on the type of the dedicated flash memory programmer used. * PG-FP4, FL-PR4: * PG-FPL3, FP-LITE3: Connect CLK of the programmer to EXCLK/X2/P122 (pin 14). Connect CLK of the programmer to X1/P121 (pin 15), and connect its inverted signal to X2/EXCLK/P122 (pin 14). 2. Remark Only the internal high-speed oscillation clock (fRH) can be used when CSI10 is used. : Be sure to connect the pin. : The pin does not have to be connected if the signal is generated on the target board. x: The pin does not have to be connected. User's Manual U17397EJ4V0UD 601 CHAPTER 27 FLASH MEMORY www..com 27.6 Connection of Pins on Board To write the flash memory on-board, connectors that connect the dedicated flash memory programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board. When the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after reset. Therefore, if the external device does not recognize the state immediately after reset, the pins must be handled as described below. 27.6.1 FLMD0 pin In the normal operation mode, 0 V is input to the FLMD0 pin. In the flash memory programming mode, the VDD write voltage is supplied to the FLMD0 pin. An FLMD0 pin connection example is shown below. Figure 27-8. FLMD0 Pin Connection Example 78K0/KF2 Dedicated flash memory programmer connection pin FLMD0 10 k (recommended) 27.6.2 Serial interface pins The pins used by each serial interface are listed below. Table 27-5. Pins Used by Each Serial Interface Serial Interface CSI10 UART6 Pins Used SO10, SI10, SCK10 TxD6, RxD6 To connect the dedicated flash memory programmer to the pins of a serial interface that is connected to another device on the board, care must be exercised so that signals do not collide or that the other device does not malfunction. 602 User's Manual U17397EJ4V0UD CHAPTER 27 FLASH MEMORY www..com (1) Signal collision If the dedicated flash memory programmer (output) is connected to a pin (input) of a serial interface connected to another device (output), signal collision takes place. To avoid this collision, either isolate the connection with the other device, or make the other device go into an output high-impedance state. Figure 27-9. Signal Collision (Input Pin of Serial Interface) 78K0/KF2 Signal collision Input pin Dedicated flash memory programmer connection pin Other device Output pin In the flash memory programming mode, the signal output by the device collides with the signal sent from the dedicated flash programmer. Therefore, isolate the signal of the other device. (2) Malfunction of other device If the dedicated flash memory programmer (output or input) is connected to a pin (input or output) of a serial interface connected to another device (input), a signal may be output to the other device, causing the device to malfunction. To avoid this malfunction, isolate the connection with the other device. Figure 27-10. Malfunction of Other Device 78K0/KF2 Dedicated flash memory programmer connection pin Other device Input pin Pin If the signal output by the 78K0/KF2 in the flash memory programming mode affects the other device, isolate the signal of the other device. 78K0/KF2 Dedicated flash memory programmer connection pin Other device Input pin Pin If the signal output by the dedicated flash memory programmer in the flash memory programming mode affects the other device, isolate the signal of the other device. User's Manual U17397EJ4V0UD 603 CHAPTER 27 FLASH MEMORY www..com 27.6.3 RESET pin If the reset signal of the dedicated flash memory programmer is connected to the RESET pin that is connected to the reset signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the reset signal generator. If the reset signal is input from the user system while the flash memory programming mode is set, the flash memory will not be correctly programmed. Do not input any signal other than the reset signal of the dedicated flash memory programmer. Figure 27-11. Signal Collision (RESET Pin) 78K0/KF2 Signal collision RESET Dedicated flash memory programmer connection signal Reset signal generator Output pin In the flash memory programming mode, the signal output by the reset signal generator collides with the signal output by the dedicated flash memory programmer. Therefore, isolate the signal of the reset signal 27.6.4 Port pins When the flash memory programming mode is set, all the pins not used for flash memory programming enter the same status as that immediately after reset. If external devices connected to the ports do not recognize the port status immediately after reset, the port pin must be connected to VDD or VSS via a resistor. 27.6.5 REGC pin Connect the REGC pin to GND via a capacitor (0.47 to 1 F: recommended) in the same manner as during normal operation. 604 User's Manual U17397EJ4V0UD CHAPTER 27 FLASH MEMORY www..com 27.6.6 Other signal pins Connect X1 and X2 in the same status as in the normal operation mode when using the on-board clock. To input the operating clock from the dedicated flash memory programmer, however, connect as follows. * PG-FP4, FL-PR4: * PG-FPL3, FP-LITE3: Connect CLK of the programmer to EXCLK/X2/P122. Connect CLK of the programmer and X1/P121, and connect its inverted signal to X2/EXCLK/P122. Cautions 1. Only the internal high-speed oscillation clock (fRH) can be used when CSI10 is used. 2. Only the X1 clock (fX) or external main system clock (fEXCLK) can be used when UART6 is used. 3. For products without an on-chip debug function (other than the PD78F0547D) and having a product rank of "I", "K", or "E", and for the product with an on-chip debug function (PD78F0547D), connect P31/INTP2/OCD1ANote and P121/X1/OCD0ANote as follows when writing the flash memory with a flash memory programmer. * P31/INTP2/OCD1ANote: Connect to EVSS via a resistor (10 k: recommended). * P121/X1/OCD0ANote: When using this pin as a port, connect it to VSS via a resistor (10 k: recommended) (in the input mode) or leave it open (in the output mode). The above connection is not necessary when writing the flash memory by means of self programming. Note OCD0A and OCD1A are provided to the PD78F0547D only. Remark For the product ranks, consult an NEC Electronics sales representative. 27.6.7 Power supply To use the supply voltage output of the flash memory programmer, connect the VDD pin to VDD of the flash p memory rogrammer, and the VSS pin to GND of the flash memory programmer. To use the on-board supply voltage, connect in compliance with the normal operation mode. However, be sure to connect the VDD and VSS pins to VDD and GND of the flash memory programmer to use the power monitor function with the flash memory programmer, even when using the on-board supply voltage. Supply the same other power supplies (EVDD, EVSS, AVREF, and AVSS) as those in the normal operation mode. User's Manual U17397EJ4V0UD 605 CHAPTER 27 FLASH MEMORY www..com 27.7 Programming Method 27.7.1 Controlling flash memory The following figure illustrates the procedure to manipulate the flash memory. Figure 27-12. Flash Memory Manipulation Procedure Start FLMD0 pulse supply Flash memory programming mode is set Selecting communication mode Manipulate flash memory End? Yes End No 27.7.2 Flash memory programming mode To rewrite the contents of the flash memory by using the dedicated flash memory programmer, set the 78K0/KF2 in the flash memory programming mode. To set the mode, set the FLMD0 pin to VDD and clear the reset signal. Change the mode by using a jumper when writing the flash memory on-board. Figure 27-13. Flash Memory Programming Mode 5.5 V 0V VDD VDD RESET 0V FLMD0 pulse VDD FLMD0 0V Flash memory programming mode Table 27-6. Relationship Between FLMD0 Pin and Operation Mode After Reset Release FLMD0 0 VDD Operation Mode Normal operation mode Flash memory programming mode 606 User's Manual U17397EJ4V0UD CHAPTER 27 FLASH MEMORY www..com 27.7.3 Selecting communication mode In the 78K0/KF2, a communication mode is selected by inputting pulses (up to 11 pulses) to the FLMD0 pin after the dedicated flash memory programming mode is entered. These FLMD0 pulses are generated by the flash memory programmer. The following table shows the relationship between the number of pulses and communication modes. Table 27-7. Communication Modes Communication Mode UART (UART6) 3-wire serial I/O (CSI10) Standard Setting Port UART-Ext-Osc UART-Ext-FP4CK CSI-Internal-OSC 2.4 kHz to 2.5 MHz - SO10, SI10, SCK10 Speed 115,200 bps Note 3 Note 1 Pins Used Multiply Rate 1.0 TxD6, RxD6 Frequency 2 to 20 MHz Note 2 Peripheral Number of Clock FLMD0 Pulses fX fEXCLK fRH 0 3 8 Notes 1. Selection items for Standard settings on GUI of the flash memory programmer. 2. The possible setting range differs depending on the voltage. For details, refer to the chapter of electrical specifications. 3. Because factors other than the baud rate error, such as the signal waveform slew, also affect UART communication, thoroughly evaluate the slew as well as the baud rate error. Caution When UART6 is selected, the receive clock is calculated based on the reset command sent from the dedicated flash memory programmer after the FLMD0 pulse has been received. Remark fX: fRH: X1 clock Internal high-speed oscillation clock fEXCLK: External main system clock User's Manual U17397EJ4V0UD 607 CHAPTER 27 FLASH MEMORY www..com 27.7.4 Communication commands The 78K0/KF2 communicates with the dedicated flash memory programmer by using commands. The signals sent from the flash memory programmer to the 78K0/KF2 are called commands, and the signals sent from the 78K0/KF2 to the dedicated flash memory programmer are called response. Figure 27-14. Communication Commands XXXX YYYY Axxxx Bxxxxx Cxxxxxx STATVE XXX YYY PG-FP4 (Flash Pro4) XXXXX XXXX XXXXXX Command Response 78K0/KF2 Dedicated flash memory programmer The flash memory control commands of the 78K0/KF2 are listed in the table below. All these commands are issued from the programmer and the 78K0/KF2 perform processing corresponding to the respective commands. Table 27-8. Flash Memory Control Commands Classification Verify Verify Command Name Function Compares the contents of a specified area of the flash memory with data transmitted from the programmer. Erase Chip Erase Block Erase Blank check Block Blank Check Erases the entire flash memory. Erases a specified area in the flash memory. Checks if a specified block in the flash memory has been correctly erased. Write Getting information Programming Status Silicon Signature Writes data to a specified area in the flash memory. Gets the current operating status (status data). Gets 78K0/Kx2 information (such as the part number and flash memory configuration). Version Get Checksum Security Others Security Set Reset Oscillating Frequency Set Gets the 78K0/Kx2 version and firmware version. Gets the checksum data for a specified area. Sets security information. Used to detect synchronization status of communication. Specifies an oscillation frequency. The 78K0/KF2 return a response for the command issued by the dedicated flash memory programmer. The response names sent from the 78K0/KF2 are listed below. Table 27-9. Response Names Response Name ACK NAK Function Acknowledges command/data. Acknowledges illegal command/data. 608 User's Manual U17397EJ4V0UD CHAPTER 27 FLASH MEMORY www..com 27.8 Security Settings User's Manual U17397EJ4V0UD 609 CHAPTER 27 FLASH MEMORY www..com Table 27-10. Relationship Between Enabling Security Function and Command (1) During on-board/off-board programming Valid Security Batch Erase (Chip Erase) Prohibition of batch erase (chip erase) Prohibition of block erase Prohibition of writing Prohibition of rewriting boot cluster 0 Cannot be erased in batch Boot cluster 0 cannot be erased. Cannot be erased in batch Can be erased in batch. Executed Command Block Erase Blocks cannot be erased. Write Can be performed Note . Can be performed. Cannot be performed. Boot cluster 0 cannot be written. Note Confirm that no data has been written to the write area. Because data cannot be erased after batch erase (chip erase) is prohibited, do not write data if the data has not been erased. (2) During self programming Valid Security Block Erase Prohibition of batch erase (chip erase) Prohibition of block erase Prohibition of writing Prohibition of rewriting boot cluster 0 Boot cluster 0 cannot be erased. Boot cluster 0 cannot be written. Blocks can be erased. Executed Command Write Can be performed. Table 27-11 shows how to perform security settings in each programming mode. Table 27-11. Setting Security in Each Programming Mode (1) On-board/off-board programming Security Prohibition of batch erase (chip erase) Prohibition of block erase Prohibition of writing Prohibition of rewriting boot cluster 0 Security Setting Set via GUI of dedicated flash memory programmer, etc. How to Disable Security Setting Cannot be disabled after set. Execute batch erase (chip erase) command Cannot be disabled after set. (2) Self programming Security Prohibition of batch erase (chip erase) Prohibition of block erase Prohibition of writing Security Setting Set by using information library. How to Disable Security Setting Cannot be disabled after set. Execute batch erase (chip erase) command during on-board/off-board programming (cannot be disabled during self programming) Prohibition of rewriting boot cluster 0 Cannot be disabled after set. 610 User's Manual U17397EJ4V0UD CHAPTER 27 FLASH MEMORY www..com 27.9 Processing Time for Each Command When PG-FP4 Is Used (Reference) The following table shows the processing time for each command (reference) when the PG-FP4 is used as a dedicated flash memory programmer. Table 27-12. Processing Time for Each Command When PG-FP4 Is Used (Reference) * PD78F0547, 78F0547D (internal ROM capacity: 128 KB) Command of PG-FP4 Port: CSI-Internal-OSC (Internal high-speed oscillation clock (fRH)), Speed: 2.5 MHz Frequency: 2.0 MHz Signature Blankcheck Erase Program Verify E.P.V Checksum Security 0.5 s (TYP.) 1 s (TYP.) 1.5 s (TYP.) 9.5 s (TYP.) 4.5 s (TYP.) 11 s (TYP.) 1 s (TYP.) 0.5 s (TYP.) 0.5 s (TYP.) 1 s (TYP.) 1 s (TYP.) 18 s (TYP.) 13.5 s (TYP.) 19.5 s (TYP.) 1 s (TYP.) 0.5 s (TYP.) Frequency: 20 MHz 0.5 s (TYP.) 1 s (TYP.) 1.5 s (TYP.) 18 s (TYP.) 13.5 s (TYP.) 19.5 s (TYP.) 1 s (TYP.) 0.5 s (TYP.) Port: UART-Ext-Osc (X1 clock (fX)), Speed: 115,200 bps Port: UART-Ext-FP4CK (External main system clock (fEXCLK)), Speed: 115,200 bps Frequency: 2.0 MHz 0.5 s (TYP.) 1 s (TYP.) 1 s (TYP.) 18 s (TYP.) 13.5 s (TYP.) 19.5 s (TYP.) 1 s (TYP.) 0.5 s (TYP.) Frequency: 20 MHz 0.5 s (TYP.) 1 s (TYP.) 1.5 s (TYP.) 18 s (TYP.) 13.5 s (TYP.) 19.5 s (TYP.) 1 s (TYP.) 0.5 s (TYP.) User's Manual U17397EJ4V0UD 611 CHAPTER 27 FLASH MEMORY www..com 27.10 Flash Memory Programming by Self-Programming The 78K0/KF2 supports a self-programming function that can be used to rewrite the flash memory via a user program. Because this function allows a user application to rewrite the flash memory by using the 78K0/KF2 selfprogramming sample library, it can be used to upgrade the program in the field. If an interrupt occurs during self-programming, self-programming can be temporarily stopped and interrupt servicing can be executed. To execute interrupt servicing, restore the normal operation mode after self-programming has been stopped, and execute the EI instruction. programming can be resumed. Remark For details of the self-programming function and the 78K0/KF2 self-programming sample library, refer to 78K0/Kx2 Flash Memory Self Programming User's Manual (U17516E). Cautions 1. The self-programming function cannot be used when the CPU operates with the subsystem clock. 2. Input a high level to the FLMD0 pin during self-programming. 3. Be sure to execute the DI instruction before starting self-programming. The self-programming function checks the interrupt request flags (IF0L, IF0H, IF1L, and IF1H). If an interrupt request is generated, self-programming is stopped. 4. Self-programming is also stopped by an interrupt request that is not masked even in the DI status. To prevent this, mask the interrupt by using the interrupt mask flag registers (MK0L, MK0H, MK1L, and MK1H). 5. Allocate the entry program for self-programming in the common area of 0000H to 7FFFH. Figure 27-15. Operation Mode and Memory Map for Self-Programming (PD78F0547) FFFFH FF00H FEFFH FB00H FA F F H FA 2 0 H FA 1 F H FA 0 0 H F9FFH F800H F7FFH SFR Internal highspeed RAM Reserved Buffer RAM Reserved Memory bank 4 Memory bank 2 After the self-programming mode is later restored, self- FFFFH FF00H FEFFH FB00H FA F F H FA 2 0 H FA 1 F H FA 0 0 H F9FFH F800H F7FFH SFR Internal highspeed RAM Reserved Buffer RAM Reserved Memory bank 4 Memory bank 2 Internal expansion RAM E000H DFFFH C000H BFFFH Reserved Flash memory control firmware ROM Internal expansion RAM E000H DFFFH C000H BFFFH Reserved Flash memory control firmware ROM Flash memory (memory bank 0) 8000H 7FFFH Disable accessing 8000H 7FFFH Disable accessing Enable accessing Memory bank 5 Memory bank 3 Memory bank 5 Memory bank 3 Memory bank 1 Flash memory (common area) 0000H Memory bank 1 Instructions can be fetched from common area and selected memory bank. 0000H Flash memory (common area) Instructions can be fetched from common area and firmware ROM. Normal mode Self-programming mode 612 User's Manual U17397EJ4V0UD CHAPTER 27 FLASH MEMORY www..com The following figure illustrates a flow of rewriting the flash memory by using a self programming sample library. Figure 27-16. Flow of Self Programming (Rewriting Flash Memory) Start of self programming FLMD0 pin Low level High level FlashStart Setting operating environment FlashEnv CheckFLMD Normal completion? No Yes FlashBlockBlankCheck Erased? No Yes FlashBlockErase FlashWordWrite Normal completion? Yes Normal completion? No No Yes FlashBlockVerify Normal completion? No Yes FlashEnd FLMD0 pin High level Low level End of self programming Remark For details of the self programming sample library, refer to 78K0/Kx2 Flash Memory Self Programming User's Manual (U17516E). User's Manual U17397EJ4V0UD 613 CHAPTER 27 FLASH MEMORY www..com The following table shows the processing time and interrupt response time for the self programming sample library. Table 27-13. Processing Time and Interrupt Response Time for Self Programming Sample Library (1/4) (1) When internal high-speed oscillation clock is used and entry RAM is located outside short direct addressing range Library Name Processing Time (s) Normal Model of C Compiler Static Model of C Compiler/Assembler Min. Self programming start library Initialize library Mode check library Block blank check library Block erase library Word write library 753.875 12770.875 36909.5 1214 (1214.375) Program verify library Self programming end library Get information library (option value: 03H) Get information library (option value: 04H) Get information library (option value: 05H) Set information library EEPROM write library 871.25 (871.375) 863.375 (863.5) 1024.75 (1043.625) 105524.75 1496.5 (1496.875) 790809.375 2691.5 (2691.875) 356318 2409 (2409.375) Max. 4.25 977.75 753.125 12765.875 36904.5 1207 (1207.375) 356296.25 2402 (2402.375) 390.25 - 866 (866.125) 858.125 (858.25) 1037.5 (1038.375) 105523.75 1489.5 (1489.875) 790808.375 2684.5 (2684.875) 387 399.75 852.5 1395.5 - - - - - 1324.5 - - Min. Max. Min. - - - 391.25 389.25 394.75 Max. - - - 1300.5 1393.5 1289.5 Interrupt Response Time (s) 25618.875 4.25 25613.875 Remark The value in the parentheses indicates the value when a write start address structure is located at a place other than the internal high-speed RAM. 614 User's Manual U17397EJ4V0UD CHAPTER 27 FLASH MEMORY www..com Table 27-13. Processing Time and Interrupt Response Time for Self Programming Sample Library (2/4) (2) When internal high-speed oscillation clock is used and entry RAM is located in short direct addressing range (FE20H) Library Name Processing Time (s) Normal Model of C Compiler Static Model of C Compiler/Assembler Min. Self programming start library Initialize library Mode check library Block blank check library Block erase library Word write library 219.625 12236.625 36363.25 679.75 (680.125) Program verify library Self programming end library Get information library (option value: 03H) Get information library (option value: 04H) Get information library (option value: 05H) Set information library EEPROM write library 337 (337.125) 329.125 (239.25) 502.25 (503.125) 104978.5 962.25 (962.625) 541143.125 2157.25 (2157.625) 355771.75 1874.75 (1875.125) Max. 4.25 443.5 218.875 12231.625 36358.25 672.75 (673.125) 355750 1867.75 (1868.125) 80.25 ( 331.75 (331.875) 323.875 (324) 497 (497.875) 104977.5 955.25 (955.625) 541142.125 2150.25 (2150.625) 77 89.75 279.5 822.5 ( ( ( ( ( 751.5 ( ( Min. Max. Min. - - - 81.25 79.25 84.75 Max. - - ( 727.5 820.5 716.5 Interrupt Response Time (s) 25072.625 4.25 25067.625 Remark The value in the parentheses indicates the value when a write start address structure is located at a place other than the internal high-speed RAM. User's Manual U17397EJ4V0UD 615 CHAPTER 27 FLASH MEMORY www..com Table 27-13. Processing Time and Interrupt Response Time for Self Programming Sample Library (3/4) (3) When high-speed system clock (X1 oscillation or external clock input) is used and entry RAM is located outside short direct addressing range Library Name Processing Time (s) Normal Model of C Compiler Static Model of C Compiler/Assembler Min. Self programming start library Initialize library Mode check library Block blank check library Block erase library Max. 34/fXH 49/fXH + 485.8125 35/fXH + 374.75 174/fXH + 6382.0625 174/fXH + 31093.875 Word write library 318 (321)/fXH + 644.125 Program verify library Self programming end library Get information library (option value: 03H) Get information library (option value: 04H) Get information library (option value: 05H) Set information library 75/fXH + 79157.6875 EEPROM write library 318 (321)/fXH + 799.875 75/fXH + 652400 318 (321)/fXH + 1647.375 67/fXH + 79157.6875 262 (265)/fXH + 799.875 67/fXH + 652400 262 (265)/fXH + 1647.375 22/fXH + 191 28/fXH + 783 16/fXH + 190 28/fXH + 454 404 (411)/fXH + 496.125 362 (369)/fXH + 496.125 - - 181 (182)/fXH + 427.875 139 (140)/fXH + 427.875 - - 171 (172)/fXH + 432.4375 174/fXH + 298948.125 318 (321)/fXH + 1491.625 29/fXH + 374.75 134/fXH + 6382.0625 134/fXH + 31093.875 262 (265)/fXH + 644.125 134/fXH + 298948.125 262 (265)/fXH + 1491.625 18/fXH + 192 - 129 (130)/fXH + 432.4375 - 28/fXH + 709 - - 22/fXH + 189 28/fXH + 693 Min. Max. Min. - - - 18/fXH + 192 18/fXH + 186 Max. - - - 28/fXH + 698 28/fXH + 745 Interrupt Response Time (s) 174/fXH + 13448.5625 34/fXH 134/fXH + 13448.5625 Remarks 1. The value in the parentheses indicates the value when a write start address structure is located at a place other than the internal high-speed RAM. 2. fXH: High-speed system clock frequency 616 User's Manual U17397EJ4V0UD CHAPTER 27 FLASH MEMORY www..com Table 27-13. Processing Time and Interrupt Response Time for Self Programming Sample Library (4/4) (4) When high-speed system clock (X1 oscillation or external clock input) is used and entry RAM is located in short direct addressing range (FE20H) Library Name Processing Time (s) Normal Model of C Compiler Static Model of C Compiler/Assembler Min. Self programming start library Initialize library Mode check library Block blank check library Block erase library Max. 34/fXH 49/fXH + 224.6875 35/fXH + 113.625 174/fXH + 6120.9375 174/fXH + 30820.75 Word write library 318 (321)/fXH + 383 Program verify library Self programming end library Get information library (option value: 03H) Get information library (option value: 04H) Get information library (option value: 05H) Set information library 75/fXH + 78884.5625 EEPROM write library 318 (321)/fXH + 538.75 75/fXH + 527566.875 318 (321)/fXH + 1386.25 67/fXH + 78884.5625 262 (265)/fXH + 538.75 67/fXH + 527566.875 262 (265)/fXH + 1386.25 22/fXH +54 28/fXH +547 16/fXH +53 28/fXH +218 404 (411)/fXH + 231.875 362 (369)/fXH + 231.875 - - 181 (182)/fXH + 166.75 139 (140)/fXH + 166.75 - - 171 (172)/fXH + 171.3125 174/fXH + 298675 318 (321)/fXH + 1230.5 29/fXH + 113.625 134/fXH + 6120.9375 134/fXH + 30820.75 262 (265)/fXH + 383 134/fXH + 298675 262 (265)/fXH + 1230.5 18/fXH + 55 - 129 (130)/fXH + 171.3125 - 28/fXH + 473 - - 22/fXH + 52 28/fXH + 457 Min. Max. Min. - - - 18/fXH + 55 18/fXH + 49 Max. - - - 28/fXH + 462 28/fXH + 509 Interrupt Response Time (s) 174/fXH + 13175.4375 34/fXH 134/fXH + 13175.4375 Remarks 1. The value in the parentheses indicates the value when a write start address structure is located at a place other than the internal high-speed RAM. 2. fXH: High-speed system clock frequency User's Manual U17397EJ4V0UD 617 CHAPTER 27 FLASH MEMORY www..com 27.10.1 Boot swap function If rewriting the boot area has failed during self-programming due to a power failure or some other cause, the data in the boot area may be lost and the program may not be restarted by resetting. The boot swap function is used to avoid this problem. Before erasing boot cluster 0Note, which is a boot program area, by self-programming, write a new boot program to boot cluster 1 in advance. When the program has been correctly written to boot cluster 1, swap this boot cluster 1 and boot cluster 0 by using the set information function of the firmware of the 78K0/KF2, so that boot cluster 1 is used as a boot area. After that, erase or write the original boot program area, boot cluster 0. As a result, even if a power failure occurs while the boot programming area is being rewritten, the program is executed correctly because it is booted from boot cluster 1 to be swapped when the program is reset and started next. If the program has been correctly written to boot cluster 0, restore the original boot area by using the set information function of the firmware of the 78K0/KF2. Note A boot cluster is a 4 KB area and boot clusters 0 and 1 are swapped by the boot swap function. Boot cluster 0 (0000H to 0FFFH): Original boot program area Boot cluster 1 (1000H to 1FFFH): Area subject to boot swap function Figure 27-17. Boot Swap Function XXXXH User program Self-programming to boot cluster 1 User program Execution of boot swap by firmware User program 2000H User program 1000H 0000H Boot program (boot cluster 0) Boot New boot program (boot cluster 1) Boot program (boot cluster 0) Boot New boot program (boot cluster 1) Boot Boot program (boot cluster 0) XXXXH Self-programming to boot cluster 0 User program Execution of boot swap by firmware User program 2000H 1000H 0000H New boot program (boot cluster 1) Boot New boot program (boot cluster 1) New boot program (boot cluster 0) Boot New boot program (boot cluster 0) 618 User's Manual U17397EJ4V0UD CHAPTER 27 FLASH MEMORY www..com Figure 27-18. Example of Executing Boot Swapping Block number Erasing block 4 Boot cluster 1 Erasing block 5 7 6 5 4 3 2 1 0 Program Program Erasing block 6 7 6 5 4 3 2 1 0 Program Erasing block 7 7 6 5 4 3 2 1 0 Boot cluster 0 7 6 5 4 3 2 1 0 Program Program Program Program Boot program Boot program Boot program Boot program 1000H 0000H 7 6 5 4 3 2 1 0 Program Program Program Boot program Boot program Boot program Boot program Boot program Boot program Boot program Boot program Boot program Boot program Boot program Boot program Boot program Boot program Boot program Boot program Booted by boot cluster 0 Writing blocks 5 to 7 7 New boot program 6 New boot program 5 New boot program 4 New boot program 3 Boot program 2 Boot program 1 Boot program 0 Boot program Boot swap 7 6 5 4 3 2 1 0 New boot program New boot program New boot program New boot program Boot program Boot program Boot program Boot program Erasing block 0 7 6 5 4 3 2 1 0 New boot program New boot program New boot program New boot program Boot program Boot program Boot program Erasing block 1 7 6 5 4 3 2 1 0 New boot program New boot program New boot program New boot program Boot program Boot program 0000H 1000H Booted by boot cluster 1 Erasing block 2 7 6 5 4 3 2 1 0 New boot program New boot program New boot program New boot program Boot program Erasing block 3 7 6 5 4 3 2 1 0 New boot program New boot program New boot program New boot program Writing blocks 0 to 3 7 6 5 4 3 2 1 0 New boot program New boot program New boot program New boot program New boot program New boot program New boot program New boot program Boot swap canceled 7 New boot program 6 New boot program 5 New boot program 4 New boot program 1 0 0 0 H 3 New boot program 2 New boot program 1 New boot program 0 New boot program 0 0 0 0 H Booted by boot cluster 0 User's Manual U17397EJ4V0UD 619 www..com CHAPTER 28 ON-CHIP DEBUG FUNCTION (PD78F0547D ONLY) 28.1 Connecting QB-78K0MINI to PD78F0547D The PD78F0547D uses the VDD, FLMD0, RESET, OCD0A/X1 (or OCD1A/P31), OCD0B/X2 (or OCD1B/P32), and VSS pins to communicate with the host machine via an on-chip debug emulator (QB-78K0MINI). Whether OCD0A/X1 and OCD1A/P31, or OCD0B/X2 and OCD1B/P32 are used can be selected. Caution The PD78F0547D has an on-chip debug function. Do not use this product for mass production because its reliability cannot be guaranteed after the on-chip debug function has been used, given the issue of the number of times the flash memory can be rewritten. NEC Electronics does not accept complaints concerning this product. Figure 28-1. Connection Example of QB-78K0MINI and PD78F0547D (When OCD0A/X1 and OCD0B/X2 Are Used) QB-78K0MINI target connector FLMD0 PD78F0547D FLMD0 Note RESET_IN RESET_OUT X1 Target reset RESET OCD0A/X1 X2 OCD0B/X2 GND VDD GND VDD P31 Note Note Make pull-down resistor 470 or more (10 k: recommended). Cautions 1. Input the clock from the OCD0A/X1 pin during on-chip debugging. 2. Control the OCD0A/X1 and OCD0B/X2 pins by externally pulling down the OCD1A/P31 pin or by using an external circuit using the P130 pin (that outputs a low level when the device is reset). 620 User's Manual U17397EJ4V0UD CHAPTER 28 ON-CHIP DEBUG FUNCTION (PD78F0547D ONLY) www..com Figure 28-2. Connection Example of QB-78K0MINI and PD78F0547D (When OCD1A and OCD1B Are Used) QB-78K0MINI target connector FLMD0 PD78F0547D FLMD0 Note RESET_IN RESET_OUT X1 Target reset RESET OCD1A/P31 Note X2 OCD1B/P32 GND VDD GND VDD X1 X2 Note Make pull-down resistor 470 or more (10 k: recommended). Connect the FLMD0 pin as follows when performing self programming by means of on-chip debugging. Figure 28-3. Connection of FLMD0 Pin for Self Programming by Means of On-Chip Debugging QB-78K0MINI target connector PD78F0547D Port 1 k (recommended) FLMD0 10 k (recommended) FLMD0 User's Manual U17397EJ4V0UD 621 CHAPTER 28 ON-CHIP DEBUG FUNCTION (PD78F0547D ONLY) www..com 28.2 On-Chip Debug Security ID The PD78F0547D has an on-chip debug operation control flag in the flash memory at 0084H (see CHAPTER 26 OPTION BYTE) and an on-chip debug security ID setting area at 0085H to 008EH. When the boot swap function is used, also set a value that is the same as that of 1084H and 1085H to 108EH in advance, because 0084H, 0085H to 008EH and 1084H, and 1085H to 108EH are switched. For details on the on-chip debug security ID, refer to the QB-78K0MINI User's Manual (U17029E). Table 28-1. On-Chip Debug Security ID Address 0085H to 008EH 1085H to 108EH On-Chip Debug Security ID Any ID code of 10 bytes 622 User's Manual U17397EJ4V0UD www..com CHAPTER 29 INSTRUCTION SET This chapter lists each instruction set of the 78K0/KF2 in table form. For details of each operation and operation code, refer to the separate document 78K/0 Series Instructions User's Manual (U12326E). 29.1 Conventions Used in Operation List 29.1.1 Operand identifiers and specification methods Operands are written in the "Operand" column of each instruction in accordance with the specification method of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more methods, select one of them. Uppercase letters and the symbols #, !, $ and [ ] are keywords and must be written as they are. Each symbol has the following meaning. * #: Immediate data specification * !: Absolute address specification * $: Relative address specification * [ ]: Indirect address specification In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to write the #, !, $, and [ ] symbols. For operand register identifiers r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for specification. Table 29-1. Operand Identifiers and Specification Methods Identifier r rp sfr sfrp saddr saddrp addr16 addr11 addr5 word byte bit RBn Specification Method X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special function register symbol Note Note Special function register symbol (16-bit manipulatable register even addresses only) FE20H to FF1FH Immediate data or labels FE20H to FF1FH Immediate data or labels (even address only) 0000H to FFFFH Immediate data or labels (Only even addresses for 16-bit data transfer instructions) 0800H to 0FFFH Immediate data or labels 0040H to 007FH Immediate data or labels (even address only) 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label RB0 to RB3 Note Addresses from FFD0H to FFDFH cannot be accessed with these operands. Remark For special function register symbols, see Table 3-6 Special Function Register List. User's Manual U17397EJ4V0UD 623 CHAPTER 29 INSTRUCTION SET www..com 29.1.2 Description of operation column A: X: B: C: D: E: H: L: AX: BC: DE: HL: PC: SP: PSW: CY: AC: Z: RBS: IE: ( ): : : : A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Register bank select flag Interrupt request enable flag Memory contents indicated by address or register contents in parentheses Logical product (AND) Logical sum (OR) Exclusive logical sum (exclusive OR) : Inverted data Signed 8-bit data (displacement value) XH, XL: Higher 8 bits and lower 8 bits of 16-bit register addr16: 16-bit immediate data or label jdisp8: 29.1.3 Description of flag operation column (Blank): Not affected 0: 1: x: R: Cleared to 0 Set to 1 Set/cleared according to the result Previously saved value is restored 624 User's Manual U17397EJ4V0UD CHAPTER 29 INSTRUCTION SET www..com 29.2 Operation List Instruction Group 8-bit data transfer Clocks Note 1 Note 2 Mnemonic MOV Operands r, #byte saddr, #byte sfr, #byte A, r r, A A, saddr saddr, A A, sfr sfr, A A, !addr16 !addr16, A PSW, #byte A, PSW PSW, A A, [DE] [DE], A A, [HL] [HL], A A, [HL + byte] [HL + byte], A A, [HL + B] [HL + B], A A, [HL + C] [HL + C], A Note 3 Bytes 2 3 3 1 1 2 2 2 2 3 3 3 2 2 1 1 1 1 2 2 1 1 1 1 Note 3 Operation r byte (saddr) byte sfr byte Ar rA A (saddr) (saddr) A A sfr sfr A A (addr16) (addr16) A PSW byte A PSW PSW A A (DE) (DE) A A (HL) (HL) A A (HL + byte) (HL + byte) A A (HL + B) (HL + B) A A (HL + C) (HL + C) A Ar A (saddr) A (sfr) A (addr16) A (DE) A (HL) A (HL + byte) A (HL + B) A (HL + C) x x Flag Z AC CY 4 6 - 2 2 4 4 - - 8 8 - - - 4 4 4 4 8 8 6 6 6 6 2 4 - 8 4 4 8 8 8 - 7 7 - - 5 5 5 5 9 9 7 5 5 5 5 5 5 9 9 7 7 7 7 - 6 6 10 6 6 10 10 10 Note 3 x x x x XCH A, r A, saddr A, sfr A, !addr16 A, [DE] A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] 1 2 2 3 1 1 2 2 2 Notes 1. 2. 3. When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. User's Manual U17397EJ4V0UD 625 CHAPTER 29 INSTRUCTION SET www..com Instruction Group 16-bit data transfer Mnemonic MOVW Operands rp, #word saddrp, #word sfrp, #word AX, saddrp saddrp, AX AX, sfrp sfrp, AX AX, rp rp, AX AX, !addr16 !addr16, AX Note 3 Bytes 3 4 4 2 2 2 2 1 1 3 3 Note 3 Clocks Note 1 Note 2 Operation rp word (saddrp) word sfrp word AX (saddrp) (saddrp) AX AX sfrp sfrp AX AX rp rp AX AX (addr16) (addr16) AX AX rp A, CY A + byte (saddr), CY (saddr) + byte A, CY A + r r, CY r + A A, CY A + (saddr) A, CY A + (addr16) A, CY A + (HL) A, CY A + (HL + byte) A, CY A + (HL + B) A, CY A + (HL + C) A, CY A + byte + CY (saddr), CY (saddr) + byte + CY A, CY A + r + CY r, CY r + A + CY A, CY A + (saddr) + CY A, CY A + (addr16) + C A, CY A + (HL) + CY A, CY A + (HL + byte) + CY A, CY A + (HL + B) + CY A, CY A + (HL + C) + CY x x x x x x x x x x x x x x x x x x x x Flag Z AC CY 6 8 - 6 6 - - 4 4 10 10 4 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 - 10 10 8 8 8 8 - - 12 12 - - 8 - - 5 9 5 9 9 9 - 8 - - 5 9 5 9 9 9 Note 3 XCHW 8-bit operation ADD AX, rp A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] 1 2 3 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Note 4 2 2 2 3 1 2 2 2 2 3 ADDC A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] Note 4 2 2 2 3 1 2 2 2 Notes 1. 2. 3. 4. When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Only when rp = BC, DE or HL Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 626 User's Manual U17397EJ4V0UD CHAPTER 29 INSTRUCTION SET www..com Instruction Group 8-bit operation Mnemonic SUB Operands A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] Note 3 Bytes 2 3 2 2 2 3 1 2 2 2 2 3 Note 3 Clocks Note 1 Note 2 Operation A, CY A - byte (saddr), CY (saddr) - byte A, CY A - r r, CY r - A A, CY A - (saddr) A, CY A - (addr16) A, CY A - (HL) A, CY A - (HL + byte) A, CY A - (HL + B) A, CY A - (HL + C) A, CY A - byte - CY (saddr), CY (saddr) - byte - CY A, CY A - r - CY r, CY r - A - CY A, CY A - (saddr) - CY A, CY A - (addr16) - CY A, CY A - (HL) - CY A, CY A - (HL + byte) - CY A, CY A - (HL + B) - CY A, CY A - (HL + C) - CY A A byte (saddr) (saddr) byte AAr rrA A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A A (HL + B) A A (HL + C) x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Flag Z AC CY x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 - 8 - - 5 9 5 9 9 9 - 8 - - 5 9 5 9 9 9 - 8 - - 5 9 5 9 9 9 SUBC A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] 2 2 2 3 1 2 2 2 2 3 AND A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] Note 3 2 2 2 3 1 2 2 2 Notes 1. 2. 3. When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. User's Manual U17397EJ4V0UD 627 CHAPTER 29 INSTRUCTION SET www..com Instruction Group 8-bit operation Mnemonic OR Operands A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] Note 3 Bytes 2 3 2 2 2 3 1 2 2 2 2 3 Note 3 Clocks Note 1 Note 2 Operation A A byte (saddr) (saddr) byte AAr rrA A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A A (HL + B) A A (HL + C) A A byte (saddr) (saddr) byte AAr rrA A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A A (HL + B) A A (HL + C) A - byte (saddr) - byte A-r r-A A - (saddr) A - (addr16) A - (HL) A - (HL + byte) A - (HL + B) A - (HL + C) x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Flag Z AC CY 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 - 8 - - 5 9 5 9 9 9 - 8 - - 5 9 5 9 9 9 - 8 - - 5 9 5 9 9 9 XOR A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] 2 2 2 3 1 2 2 2 2 3 CMP A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] Note 3 x x x x x x x x x x x x x x x x x x x x 2 2 2 3 1 2 2 2 Notes 1. 2. 3. When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 628 User's Manual U17397EJ4V0UD CHAPTER 29 INSTRUCTION SET www..com Instruction Group 16-bit operation Mnemonic ADDW SUBW CMPW Operands AX, #word AX, #word AX, #word X C r saddr Bytes 3 3 3 2 2 1 2 1 2 1 1 1 1 1 1 2 2 2 2 6 6 6 16 25 2 4 2 4 4 4 2 2 2 2 10 10 4 4 6 - 4 - 6 6 - 4 - 6 Clocks Note 1 Note 2 Operation AX, CY AX + word AX, CY AX - word AX - word AX A x X AX (Quotient), C (Remainder) AX / C rr+1 (saddr) (saddr) + 1 rr-1 (saddr) (saddr) - 1 rp rp + 1 rp rp - 1 (CY, A7 A0, Am - 1 Am) x 1 time (CY, A0 A7, Am + 1 Am) x 1 time (CY A0, A7 CY, Am - 1 Am) x 1 time (CY A7, A0 CY, Am + 1 Am) x 1 time A3 - 0 (HL)3 - 0, (HL)7 - 4 A3 - 0, (HL)3 - 0 (HL)7 - 4 A3 - 0 (HL)7 - 4, (HL)3 - 0 A3 - 0, (HL)7 - 4 (HL)3 - 0 Decimal Adjust Accumulator after Addition Decimal Adjust Accumulator after Subtract CY (saddr.bit) CY sfr.bit CY A.bit CY PSW.bit CY (HL).bit (saddr.bit) CY sfr.bit CY A.bit CY PSW.bit CY (HL).bit CY x x x x x x x x x x Flag Z AC CY x x x x x x - - - - - - 6 - 6 - - - - - - 12 12 - - 7 7 - 7 7 8 8 - 8 8 Multiply/ divide Increment/ decrement MULU DIVUW INC x x x x DEC r saddr INCW DECW Rotate ROR ROL RORC ROLC ROR4 ROL4 BCD adjustment Bit manipulate ADJBA ADJBS MOV1 rp rp A, 1 A, 1 A, 1 A, 1 [HL] [HL] x x x x x x x x x x x x x CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit saddr.bit, CY sfr.bit, CY A.bit, CY PSW.bit, CY [HL].bit, CY 3 3 2 3 2 3 3 2 3 2 x Notes 1. 2. When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. User's Manual U17397EJ4V0UD 629 CHAPTER 29 INSTRUCTION SET www..com Instruction Group Bit manipulate Mnemonic AND1 Operands CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit Bytes 3 3 2 3 2 3 3 2 3 2 3 3 2 3 2 2 3 2 2 2 2 3 2 2 2 1 1 1 6 - 4 - 6 6 - 4 - 6 6 - 4 - 6 4 - 4 - 6 4 - 4 - 6 2 2 2 Clocks Note 1 Note 2 Operation CY CY (saddr.bit) CY CY sfr.bit CY CY A.bit CY CY PSW.bit CY CY (HL).bit CY CY (saddr.bit) CY CY sfr.bit CY CY A.bit CY CY PSW.bit CY CY (HL).bit CY CY (saddr.bit) CY CY sfr.bit CY CY A.bit CY CY PSW.bit CY CY (HL).bit (saddr.bit) 1 sfr.bit 1 A.bit 1 PSW.bit 1 (HL).bit 1 (saddr.bit) 0 sfr.bit 0 A.bit 0 PSW.bit 0 (HL).bit 0 CY 1 CY 0 CY CY x x Flag Z AC CY x x x x x x x x x x x x x x x 7 7 - 7 7 7 7 - 7 7 7 7 - 7 7 6 8 - 6 8 6 8 - 6 8 - - - OR1 CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit XOR1 CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW. bit CY, [HL].bit SET1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit x x CLR1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit x x SET1 CLR1 NOT1 CY CY CY 1 0 x Notes 1. 2. When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 630 User's Manual U17397EJ4V0UD CHAPTER 29 INSTRUCTION SET www..com Instruction Group Call/return Mnemonic CALL CALLF Operands !addr16 !addr11 Bytes 3 2 7 5 Clocks Note 1 Note 2 Operation (SP - 1) (PC + 3)H, (SP - 2) (PC + 3)L, PC addr16, SP SP - 2 (SP - 1) (PC + 2)H, (SP - 2) (PC + 2)L, PC15 - 11 00001, PC10 - 0 addr11, SP SP - 2 Flag Z AC CY - - CALLT [addr5] 1 6 - (SP - 1) (PC + 1)H, (SP - 2) (PC + 1)L, PCH (00000000, addr5 + 1), PCL (00000000, addr5), SP SP - 2 BRK 1 6 - (SP - 1) PSW, (SP - 2) (PC + 1)H, (SP - 3) (PC + 1)L, PCH (003FH), PCL (003EH), SP SP - 3, IE 0 RET RETI RETB Stack manipulate PUSH PSW rp POP PSW rp MOVW SP, #word SP, AX AX, SP Unconditional BR branch !addr16 $addr16 AX Conditional BC branch BNC BZ BNZ $addr16 $addr16 $addr16 $addr16 1 1 1 1 1 1 1 4 2 2 3 2 2 2 2 2 2 6 6 6 2 4 2 4 - - - 6 6 8 6 6 6 6 - - - - - - - 10 8 8 - - - - - - - PCH (SP + 1), PCL (SP), SP SP + 2 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3 (SP - 1) PSW, SP SP - 1 (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 PSW (SP), SP SP + 1 rpH (SP + 1), rpL (SP), SP SP + 2 SP word SP AX AX SP PC addr16 PC PC + 2 + jdisp8 PCH A, PCL X PC PC + 2 + jdisp8 if CY = 1 PC PC + 2 + jdisp8 if CY = 0 PC PC + 2 + jdisp8 if Z = 1 PC PC + 2 + jdisp8 if Z = 0 RRR RRR RRR Notes 1. 2. When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. User's Manual U17397EJ4V0UD 631 CHAPTER 29 INSTRUCTION SET www..com Instruction Group Mnemonic Operands saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 Bytes 3 4 3 3 3 4 4 3 4 3 4 4 3 4 3 2 2 3 2 1 2 2 2 2 8 - 8 - 10 10 - 8 - 10 10 - 8 - 10 6 6 8 4 2 - - 6 6 Clocks Note 1 Note 2 Operation PC PC + 3 + jdisp8 if (saddr.bit) = 1 PC PC + 4 + jdisp8 if sfr.bit = 1 PC PC + 3 + jdisp8 if A.bit = 1 PC PC + 3 + jdisp8 if PSW.bit = 1 PC PC + 3 + jdisp8 if (HL).bit = 1 PC PC + 4 + jdisp8 if (saddr.bit) = 0 PC PC + 4 + jdisp8 if sfr.bit = 0 PC PC + 3 + jdisp8 if A.bit = 0 PC PC + 4 + jdisp8 if PSW. bit = 0 PC PC + 3 + jdisp8 if (HL).bit = 0 PC PC + 4 + jdisp8 if (saddr.bit) = 1 then reset (saddr.bit) PC PC + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit PC PC + 3 + jdisp8 if A.bit = 1 then reset A.bit PC PC + 4 + jdisp8 if PSW.bit = 1 then reset PSW.bit PC PC + 3 + jdisp8 if (HL).bit = 1 then reset (HL).bit B B - 1, then PC PC + 2 + jdisp8 if B 0 C C -1, then PC PC + 2 + jdisp8 if C 0 (saddr) (saddr) - 1, then PC PC + 3 + jdisp8 if (saddr) 0 RBS1, 0 n No Operation IE 1 (Enable Interrupt) IE 0 (Disable Interrupt) Set HALT Mode Set STOP Mode x Flag Z AC CY Conditional BT branch 9 11 - 9 11 11 11 - 11 11 12 12 - 12 12 - - 10 - - 6 6 - - BF saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 BTCLR saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 x x DBNZ B, $addr16 C, $addr16 saddr, $addr16 CPU control SEL NOP EI DI HALT STOP RBn Notes 1. 2. When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 632 User's Manual U17397EJ4V0UD CHAPTER 29 INSTRUCTION SET www..com 29.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Second Operand #byte A rNote sfr saddr !addr16 PSW [DE] [HL] [HL + byte] $addr16 [HL + B] First Operand A [HL + C] 1 None ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH MOV XCH ADD SUB AND OR XOR CMP MOV XCH ADD SUB AND OR XOR CMP MOV MOV XCH MOV XCH ADD SUB AND OR XOR CMP MOV XCH ADD SUB AND OR XOR CMP ROR ROL RORC ROLC ADDC ADDC SUBC SUBC ADDC ADDC SUBC SUBC r MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP INC DEC B, C sfr saddr MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP !addr16 PSW MOV MOV MOV MOV MOV DBNZ DBNZ INC DEC PUSH POP [DE] [HL] MOV MOV ROR4 ROL4 [HL + byte] [HL + B] [HL + C] X C MOV MULU DIVUW Note Except "r = A" User's Manual U17397EJ4V0UD 633 CHAPTER 29 INSTRUCTION SET www..com (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand First Operand AX ADDW SUBW CMPW rp MOVW MOVW Note #word AX rp Note sfrp saddrp !addr16 SP None MOVW XCHW MOVW MOVW MOVW MOVW INCW DECW PUSH POP sfrp saddrp !addr16 SP MOVW MOVW MOVW MOVW MOVW MOVW MOVW Note Only when rp = BC, DE, HL (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Second Operand First Operand A.bit MOV1 BT BF BTCLR sfr.bit MOV1 BT BF BTCLR saddr.bit MOV1 BT BF BTCLR PSW.bit MOV1 BT BF BTCLR [HL].bit MOV1 BT BF BTCLR CY MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None 634 User's Manual U17397EJ4V0UD CHAPTER 29 INSTRUCTION SET www..com (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand First Operand Basic instruction BR CALL BR CALLF CALLT BR BC BNC BZ BNZ Compound instruction BT BF BTCLR DBNZ AX !addr16 !addr11 [addr5] $addr16 (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP User's Manual U17397EJ4V0UD 635 www..com CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Target products: PD78F0544, 78F0545, 78F0546, 78F0547, 78F0547D Caution The PD78F0547D has an on-chip debug function. Do not use this product for mass production because its reliability cannot be guaranteed after the on-chip debug function has been used, given the issue of the number of times the flash memory can be rewritten. NEC Electronics does not accept complaints concerning this product. Absolute Maximum Ratings (TA = 25C) (1/2) Parameter Supply voltage Symbol VDD EVDD VSS EVSS AVREF AVSS Input voltage VI1 P00 to P06, P10 to P17, P20 to P27, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120 to P124, P140 to P145, X1, X2, XT1, XT2, RESET VI2 Output voltage Analog input voltage VO VAN ANI0 to ANI7 P60 to P63 (N-ch open drain) -0.3 to +6.5 -0.3 to VDD + 0.3 Note Conditions Ratings -0.5 to +6.5 -0.5 to +6.5 -0.5 to +0.3 -0.5 to +0.3 -0.5 to VDD + 0.3 -0.5 to +0.3 -0.3 to VDD + 0.3 Note Note Unit V V V V V V V V V V -0.3 to AVREF + 0.3 P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 -25 -10 Note Note and -0.3 to VDD + 0.3 Output current, high IOH Per pin mA Total of all pins P00 to P04, P40 to P47, -80 mA P120, P130, P140 to P145 P05, P06, P10 to P17, P30 to P33, P50 to P57, P64 to P67, P70 to P77 Per pin Total of all pins Per pin Total of all pins P121 to P124 P20 to P27 mA -55 mA -0.5 -2 -1 -4 mA mA mA mA Note Must be 6.5 V or lower. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U17397EJ4V0UD 636 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) www..com Standard products Absolute Maximum Ratings (TA = 25C) (2/2) Parameter Output current, low Symbol IOL Per pin Conditions P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P120, P130, P140 to P145 Total of all pins P00 to P04, P40 to P47, 200 mA P120, P130, P140 to P145 P05, P06, P10 to P17, P30 to P33, P50 to P57, P60 to P67, P70 to P77 Per pin Total of all pins Per pin Total of all pins Operating ambient temperature TA In normal operation mode In flash memory programming mode Tstg -65 to +150 C P121 to P124 P20 to P27 1 5 4 10 -40 to +85 mA mA mA mA C 140 mA 60 mA Ratings 30 Unit mA Storage temperature Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U17397EJ4V0UD 637 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard www..com products X1 Oscillator Characteristics (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, VSS = EVSS = AVSS = 0 V) Resonator Ceramic resonator Recommended Circuit Parameter X1 clock Conditions 4.0 V VDD 5.5 V Note 1 MIN. 1.0 Note 2 TYP. MAX. 20.0 Unit MHz VSS X1 X2 oscillation frequency (fX) 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V 4.0 V VDD 5.5 V Note 1 1.0 Note 2 10.0 C1 C2 1.0 5.0 Crystal resonator X1 clock 1.0 Note 2 20.0 MHz VSS X1 X2 oscillation frequency (fX) 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V 1.0 Note 2 10.0 C1 C2 1.0 5.0 Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 638 User's Manual U17397EJ4V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) www..com Standard products Internal Oscillator Characteristics (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, VSS = EVSS = AVSS = 0 V) Resonator 8 MHz internal oscillator Parameter Internal high-speed oscillation clock frequency (fRH) Note Conditions RSTS = 1 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V RSTS = 0 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V MIN. 7.6 7.6 2.48 216 192 TYP. 8.0 8.0 5.0 240 240 MAX. 8.4 10.4 9.86 264 264 Unit MHz MHz MHz kHz kHz 240 kHz internal oscillator Internal low-speed oscillation clock frequency (fRL) Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Remark RSTS: Bit 7 of the internal oscillation mode register (RCM)) XT1 Oscillator Characteristics (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, VSS = EVSS = AVSS = 0 V) Resonator Crystal resonator Recommended Circuit Parameter XT1 clock oscillation frequency (fXT) Note Conditions MIN. 32 TYP. 32.768 MAX. 35 Unit kHz VSS XT2 Rd C4 XT1 C3 Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Cautions 1. When using the XT1 oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the X1 oscillator. Particular care is therefore required with the wiring method when the XT1 clock is used. User's Manual U17397EJ4V0UD 639 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard www..com products Recommended Oscillator Constants (1) X1 oscillation: Ceramic resonator (TA = -40 to +85C) (1/2) Manufacturer Part Number SMD/ Lead Frequency (MHz) Recommended Circuit Constants C1 (pF) Murata Mfg. Co., Ltd. CSTCC2M00G56-R0 CSTLS4M00G56-B0 CSTCR4M00G55-R0 CSTLS4M19G56-B0 CSTCR4M19G55-R0 CSTLS4M91G56-B0 CSTCR4M91G55-R0 CSTLS5M00G56-B0 CSTCR5M00G55-R0 CSTLS6M00G56-B0 CSTCR6M00G55-R0 CSTLS8M00G56-B0 CSTCE8M00G55-R0 CSTLS8M38G56-B0 CSTCE8M38G55-R0 CSTLS10M0G56-B0 CSTCE10M0G55-R0 CSTCE12M0G55-R0 CSTCE16M0V53-R0 CSTCE20M0V53-R0 Murata Mfg. Co., Ltd. (low-capacitance products) CSTLS10M0G53-B0 CSTCE12M0G52-R0 CSTCE16M0V51-R0 CSTCE20M0V51-R0 Lead SMD SMD SMD 10.0 12.0 16.0 20.0 Internal (15) Internal (10) Internal (5) Internal (5) Internal (15) Internal (10) Internal (5) Internal (5) 1.8 1.8 1.8 1.9 CSTLS6M00G53-B0 CSTLS8M00G53-B0 CSTLS8M38G53-B0 SMD Lead SMD Lead SMD Lead SMD Lead SMD Lead SMD Lead SMD Lead SMD Lead SMD SMD SMD SMD Lead Lead Lead 12.0 16.0 20.0 6.00 8.00 8.388 10.0 8.388 8.00 6.00 5.00 4.915 4.194 2.00 4.00 Internal (47) Internal (47) Internal (39) Internal (47) Internal (39) Internal (47) Internal (39) Internal (47) Internal (39) Internal (47) Internal (39) Internal (47) Internal (33) Internal (47) Internal (33) Internal (47) Internal (33) Internal (33) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) C2 (pF) Internal (47) Internal (47) Internal (39) Internal (47) Internal (39) Internal (47) Internal (39) Internal (47) Internal (39) Internal (47) Internal (39) Internal (47) Internal (33) Internal (47) Internal (33) Internal (47) Internal (33) Internal (33) Internal (15) Internal (15) Internal (15) Internal (15) Internal (15) 1.9 1.8 2.4 1.8 2.3 1.9 2.3 1.9 2.5 2.3 2.3 2.3 2.6 1.8 1.8 1.8 5.5 MIN. (V) 1.8 MAX. (V) 5.5 Oscillation Voltage Range Caution The oscillator constants shown above are reference values based on evaluation in a specific environment by the resonator manufacturer. If it is necessary to optimize the oscillator characteristics in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0/KF2 so that the internal operation conditions are within the specifications of the DC and AC characteristics. 640 User's Manual U17397EJ4V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) www..com Standard products (1) X1 oscillation: Ceramic resonator (TA = -40 to +85C) (2/2) Manufacturer Part Number SMD/ Lead Frequency (MHz) Recommended Circuit Constants C1 (pF) TDK Corporation CCR4.0MUC8 FCR4.0MC5 CCR8.0MXC8 FCR8.0MC5 SMD Lead SMD Lead 8.00 4.00 Internal (27) Internal (30) Internal (18) Internal (20) C2 (pF) Internal (27) Internal (30) Internal (30) Internal (20) MIN. (V) 1.8 MAX. (V) 5.5 Oscillation Voltage Range Caution The oscillator constants shown above are reference values based on evaluation in a specific environment by the resonator manufacturer. If it is necessary to optimize the oscillator characteristics in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0/KF2 so that the internal operation conditions are within the specifications of the DC and AC characteristics. (2) XT1 oscillation: Crystal resonator (TA = -40 to +85C) Manufacturer Part Number SMD/ Lead Frequency (MHz) Load Capacitance CL (pF) C3 (pF) Seiko Instruments Inc. VT-200 Lead 32.768 6.0 12.5 4 15 VDD = 3.3 V C4 (pF) 3 15 Rd (k) 100 100 C3 (pF) 6 18 VDD = 5.0 V C4 (pF) 5 15 Rd (k) 100 100 1.8 5.5 Recommended Circuit Constants Oscillation Voltage Range MIN. (V) MAX. (V) Caution The oscillator constants shown above are reference values based on evaluation in a specific environment by the resonator manufacturer. If it is necessary to optimize the oscillator characteristics in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0/KF2 so that the internal operation conditions are within the specifications of the DC and AC characteristics. User's Manual U17397EJ4V0UD 641 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard www..com products DC Characteristics (1/4) (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Output current, high Note 1 Symbol IOH1 Conditions Per pin for P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 Total of P00 to P04, P40 to P47, Note 3 P120, P130, P140 to P145 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V Total of P05, P06, P10 to P17, P30 to P33, P50 to P57, P64 to Note 3 P67, P70 to P77 Total Note 3 MIN. TYP. MAX. -3.0 -2.5 -1.0 -20.0 -10.0 -5.0 -30.0 -19.0 -10.0 -50.0 -29.0 -15.0 -0.1 -0.1 8.5 5.0 2.0 15.0 5.0 2.0 20.0 15.0 9.0 45.0 35.0 20.0 65.0 50.0 29.0 0.4 0.4 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V of all pins IOH2 Output current, low Note 2 Per pin for P20 to P27 Per pin for P121 to P124 Per pin for P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 Per pin for P60 to P63 AVREF = VDD 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V IOL1 Total of P00 to P04, P40 to P47, Note 3 P120, P130, P140 to P145 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V Total of P05, P06, P10 to P17, P30 to P33, P50 to P57, P60 to Note 3 P67, P70 to P77 Total of all pins Note 3 IOL2 Per pin for P20 to P27 Per pin for P121 to P124 AVREF = VDD Notes 1. Value of current at which the device operation is guaranteed even if the current flows from VDD to an output pin. 2. Value of current at which the device operation is guaranteed even if the current flows from an output pin to GND. 3. Specification under conditions where the duty factor is 70% (time for which current is output is 0.7 x t and time for which current is not output is 0.3 x t, where t is a specific time). The total output current of the pins at a duty factor of other than 70% can be calculated by the following expression. * Where the duty factor of IOH is n%: Total output current of pins = (IOH x 0.7)/(n x 0.01) User's Manual U17397EJ4V0UD 642 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) www..com Standard products DC Characteristics (2/4) (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Input voltage, high Symbol VIH1 VIH2 Conditions P02, P12, P13, P15, P40 to P47, P50 to P57, P64 to P67, P121 to P124, P144, P145, EXCLK, EXCLKS P00, P01, P03 to P06, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140 to P143, RESET P20 to P27 P60 to P63 P02, P12, P13, P15, P40 to P47, P50 to P57, P60 to P67, P121 to P124, P144, P145, EXCLK, EXCLKS P00, P01, P03 to P06, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140 to P143, RESET P20 to P27 P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 AVREF = VDD 4.0 V VDD 5.5 V, IOH1 = -3.0 mA 2.7 V VDD < 4.0 V, IOH1 = -2.5 mA 1.8 V VDD < 2.7 V, IOH1 = -1.0 mA AVREF = VDD, IOH2 = -100 A IOH2 = -100 A 4.0 V VDD 5.5 V, IOL1 = 8.5 mA 2.7 V VDD < 4.0 V, IOL1 = 5.0 mA 1.8 V VDD < 2.7 V, IOH1 = 2.0 mA 1.8 V VDD < 2.7 V, IOL1 = 0.5 mA VOL2 P20 to P27 P121 to P124 VOL3 P60 to P63 AVREF = VDD, IOL2 = 0.4 mA IOH2 = 0.4 mA 4.0 V VDD 5.5 V, IOL1 = 15.0 mA 4.0 V VDD 5.5 V, IOL1 = 5.0 mA 2.7 V VDD < 4.0 V, IOL1 = 5.0 mA 2.7 V VDD < 4.0 V, IOL1 = 3.0 mA 1.8 V VDD < 2.7 V, IOL1 = 2.0 mA AVREF = VDD MIN. 0.7VDD 0.8VDD TYP. MAX. VDD VDD Unit V V VIH3 0.7AVREF 0.7VDD 0 0 AVREF 6.0 0.3VDD 0.2VDD V V V V Input voltage, low VIH4 VIL1 VIL2 VIL3 Output voltage, high VOH1 0 VDD - 0.7 VDD - 0.5 VDD - 0.5 VDD - 0.5 VDD - 0.5 0.3AVREF V V V V V V VOH2 P20 to P27 P121 to P124 Output voltage, low VOL1 P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 0.7 0.7 0.5 0.4 0.4 0.4 2.0 0.4 0.6 0.4 0.4 V V V V V V V V V V V Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U17397EJ4V0UD 643 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard www..com products DC Characteristics (3/4) (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Input leakage current, high Symbol ILIH1 Conditions P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P120, P130, P140 to P145, VI = VDD MIN. TYP. MAX. 1 Unit A ILIH2 ILIH3 FLMD0, RESET P20 to P27 P121 to 124 (X1, X2, XT1, XT2) Input leakage current, low ILIL1 P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P120, P130, P140 to P145 VI = VSS VI = AVREF = VDD VI = VDD I/O port mode OSC mode 1 1 20 -1 A A A A ILIL2 ILIL3 FLMD0, RESET P20 to P27 P121 to 124 (X1, X2, XT1, XT2) VI = VSS, AVREF = VDD VI = VSS I/O port mode OSC mode 10 0 0.8VDD 20 -1 -1 -20 100 0.2VDD VDD A A A k V V Pull-up resistor FLMD0 supply voltage RU VIL VIH VI = VSS In normal operation mode In self-programming mode Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 644 User's Manual U17397EJ4V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) www..com Standard products DC Characteristics (4/4) (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Supply current Note 1 Symbol IDD1 Operating mode Conditions fXH = 20 MHz VDD = 5.0 V fXH = 10 MHz VDD = 5.0 V fXH = 10 MHz VDD = 3.0 V fXH = 5 MHz VDD = 3.0 V fXH = 5 MHz VDD = 2.0 V Notes 2, 3 Notes 2, 3 Notes 2, 3 Notes 2, 3 Note 2 MIN. Square wave input Resonator connection TYP. 3.2 4.5 1.6 2.3 1.5 2.2 0.9 1.3 0.7 1.0 1.4 6 15 0.8 2.0 0.4 1.0 0.2 0.5 0.4 3.0 12 1 1 0.86 MAX. 5.5 6.9 2.8 3.9 2.7 3.2 1.6 2.0 1.4 1.6 2.5 25 30 2.6 4.4 1.3 2.4 0.65 1.1 1.2 22 25 20 10 1.9 Unit mA mA mA mA mA mA mA mA mA mA mA , , Square wave input Resonator connection , Square wave input Resonator connection , Square wave input Resonator connection , Square wave input Resonator connection fRH = 8 MHz, VDD = 5.0 V fSUB = 32.768 kHz VDD = 5.0 V IDD2 HALT mode fXH = 20 MHz VDD = 5.0 V fXH = 10 MHz VDD = 5.0 V fXH = 5 MHz VDD = 3.0 V Notes 2, 3 Notes 2, 3 Note 2 Note 4 , Square wave input Resonator connection A A mA mA mA mA mA mA mA , Square wave input Resonator connection , Square wave input Resonator connection , Square wave input Resonator connection fRH = 8 MHz, VDD = 5.0 V fSUB = 32.768 kHz VDD = 5.0 V Note 5 Note 4 , Square wave input Resonator connection A A A A mA IDD3 STOP mode VDD = 5.0 V VDD = 5.0 V, TA = -40 to +70 C 2.3 V AVREF VDD A/D converter operating current IADC Note 6 During conversion at maximum Speed Not during conversion (comparator operation) Note 7 0.6 1.2 mA Watchdog timer operating current IWDT Note 8 During 240 kHz internal low-speed oscillation clock operation 5 10 A A LVI operating current ILVI Note 9 9 18 Remarks 1. fXH: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fRH: Internal high-speed oscillation clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency or external subsystem clock frequency) (Notes on next page) User's Manual U17397EJ4V0UD 645 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard www..com products 2. 3. 4. 646 User's Manual U17397EJ4V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) www..com Standard products AC Characteristics (1) Basic operation (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Instruction cycle (minimum instruction execution time) Symbol TCY Conditions Main system clock (fXP) operation 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V Subsystem clock (fSUB) operation External main system clock frequency fEXCLK 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V MIN. 0.1 0.2 0.4 Note 1 TYP. MAX. 32 32 32 Unit s s s s MHz MHz MHz ns ns ns kHz 114 1.0 Note 2 122 125 20.0 10.0 5.0 500 500 500 1.0 Note 2 1.0 24 48 96 32 32.768 External main system clock input high-level width, low-level width tEXCLKH, tEXCLKL 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V External subsystem clock frequency fEXCLKS 35 External subsystem clock input high-level width, low-level width TI000, TI010, TI001, TI011 input high-level width, low-level width tEXCLKSH, tEXCLKSL tTIH0, tTIL0 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V 4.0 V VDD 5.5 V 12 16 s s s s 2/fsam + 0.1 Note 3 2/fsam + 0.2 Note 3 2/fsam + 0.5 Note 3 TI50, TI51 input frequency fTI5 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V 10 10 5 50 50 100 1 MHz MHz MHz ns ns ns TI50, TI51 input high-level width, low-level width tTIH5, tTIL5 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V Interrupt input high-level width, low-level width tINTH, tINTL s ns Key interrupt input low-level width tKR RESET low-level width tRSL 250 10 s Notes 1. 0.38 s when operating with the 8 MHz internal oscillator. It is 2.0 MHz (MIN.) when programming on the board via UART6. Selection of fsam = fPRS, fPRS/4, fPRS/256, or fPRS, fPRS/16, fPRS/64 is possible using bits 0 and 1 (PRM000, PRM001 or PRM010, PRM011) of prescaler mode registers 00 and 01 (PRM00, PRM01). Note that when selecting the TI000 or TI001 valid edge as the count clock, fsam = fPRS. User's Manual U17397EJ4V0UD 647 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard www..com products TCY vs. VDD (Main System Clock Operation) 100 32 10 5.0 Cycle time TCY [ s] 2.0 Guaranteed operation range 1.0 0.4 0.2 0.1 0.01 0 1.0 1.8 2.0 2.7 Supply voltage VDD [V] 3.0 4.0 5.0 5.5 6.0 VIH VIL VIH VIL Test points External Main System Clock Timing, External Subsystem Clock Timing 1/fEXCLK tEXCLKL tEXCLKH EXCLK 0.7VDD (MIN.) 0.3VDD (MAX.) 1/fEXCLKS tEXCLKSL tEXCLKSH EXCLKS 0.7VDD (MIN.) 0.3VDD (MAX.) User's Manual U17397EJ4V0UD 648 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) www..com Standard products TI Timing tTIL0 tTIH0 TI000, TI010, TI001, TI011 1/fTI5 tTIL5 tTIH5 TI50, TI51 Interrupt Request Input Timing tINTL tINTH INTP0 to INTP7 Key Interrupt Input Timing tKR KR0 to KR7 RESET Input Timing tRSL RESET User's Manual U17397EJ4V0UD 649 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard www..com products (2) Serial interface (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) (a) UART6 (dedicated baud rate generator output) Parameter Transfer rate Symbol Conditions MIN. TYP. MAX. 625 Unit kbps (b) UART0 (dedicated baud rate generator output) Parameter Transfer rate Symbol Conditions MIN. TYP. MAX. 625 Unit kbps (c) IIC0 Parameter Symbol Standard Mode MIN. SCL0 clock frequency Setup time of start/restart condition Hold time Hold time when SCL0 = "L" Hold time when SCL0 = "H" Data setup time (reception) Data hold time (transmission) Note 2 Note 1 High-Speed Mode MIN. 0 0.7 0.7 1.25 1.25 0 0.23 MAX. 400 - - - - - 1.00 Unit MAX. 100 - - - - - 4.0 fSCL tSU:STA tHD:STA tLOW tHIGH tSU:DAT tHD:DAT 0 4.8 4.1 5.0 5.0 0 0.47 kHz s s s s s s Notes 1. 2. The first clock pulse is generated after this period when the start/restart condition is detected. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. (d) CSI1n (master mode, SCK1n... internal clock output) Parameter SCK1n cycle time Symbol tKCY1 Conditions 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V SCK1n high-/low-level width tKH1, tKL1 SI1n setup time (to SCK1n) SI1n hold time (from SCK1n) Delay time from SCK1n to SO1n output tSIK1 tKSI1 tKSO1 C = 50 pF Note 2 MIN. 100 200 400 tKCY1/2 - 10 Note 1 TYP. MAX. Unit ns ns ns ns 30 30 40 ns ns ns Notes 1. 2. Remark This value is when high-speed system clock (fXH) is used. C is the load capacitance of the SCK1n and SO1n output lines. n = 0, 1 650 User's Manual U17397EJ4V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) www..com Standard products (e) CSI1n (slave mode, SCK1n... external clock input) Parameter SCK1n cycle time SCK1n high-/low-level width Symbol tKCY2 tKH2, tKL2 SI1n setup time (to SCK1n) SI1n hold time (from SCK1n) Delay time from SCK1n to SO1n output tSIK2 tKSI2 tKSO2 C = 50 pF Note Conditions MIN. 400 tKCY2/2 TYP. MAX. Unit ns ns 80 50 120 ns ns ns Note C is the load capacitance of the SO1n output line. Remark n = 0, 1 (f) CSIA0 (master mode, SCKA0...internal clock output) Parameter SCKA0 cycle time Symbol tKCY3 Conditions 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V SCKA0 high-/low-level width tKH3, tKL3 2.7 V VDD < 4.0 V SIA0 setup time (to SCKA0) tSIK3 4.0 V VDD 5.5 V MIN. 600 1200 tKCY3/2 - 50 tKCY3/2 - 100 100 300 C = 100 pF Note TYP. MAX. Unit ns ns ns ns ns ns 200 300 ns ns ns SIA0 hold time (from SCKA0) tKSI3 Delay time from SCKA0 to SOA0 output Time from SCKA0 to STB0 tSBD 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V Busy signal setup time (to busy signal detection timing) Busy signal hold time (from busy signal detection timing) Time from busy inactive to SCKA0 tSPS tBYH 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V tBYS tKSO3 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V tKCY3/2 - 100 tKCY3 - 30 tKCY3 - 60 100 Strobe signal high-level width tSBW ns ns ns 100 150 2tKCY3 ns ns ns Note C is the load capacitance of the SCKA0 and SOA0 output lines. User's Manual U17397EJ4V0UD 651 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard www..com products (g) CSIA0 (slave mode, SCKA0...external clock input) Parameter SCKA0 cycle time Symbol tKCY4 Conditions 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V SCKA0 high-/low-level width tKH4, tKL4 SIA0 setup time (to SCKA0) tSIK4 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V MIN. 600 1200 300 600 100 300 C = 100 pF Note TYP. MAX. Unit ns ns ns ns ns ns SIA0 hold time (from SCKA0) tKSI4 Delay time from SCKA0 to SOA0 output SCKA0 rise/fall time tR4, tF4 tKSO4 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 200 300 1000 ns ns ns Note C is the load capacitance of the SOA0 output line. Serial Transfer Timing (1/2) IIC0: tLOW SCL0 tHD:DAT tHD:STA tHIGH tSU:DAT tSU:STA tHD:STA SDA0 Stop condition Start condition Restart condition Stop condition CSI1n: tKCYm tKLm tKHm SCK1n tSIKm tKSIm SI1n Input data tKSOm SO1n Output data Remark m = 1, 2 n = 0, 1 652 User's Manual U17397EJ4V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) www..com Standard products Serial Transfer Timing (2/2) CSIA0: SOA0 D2 D1 D0 D7 SIA0 D2 tSIK3, 4 tKSO3, 4 D1 tKSI3, 4 tKH3, 4 tF4 D0 D7 SCKA0 tR4 tKL3, 4 tKCY3, 4 STB0 tSBD tSBW CSIA0 (busy processing): SCKA0 7 8 9Note 10Note 10 + nNote tBYH tSPS 1 tBYS BUSY0 (active-high) Note SCKA0 does not become low level here, but the timing is illustrated so that the timing specifications can be shown. User's Manual U17397EJ4V0UD 653 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard www..com products A/D Converter Characteristics (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, 2.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Resolution Overall error Notes 1, 2 Symbol RES AINL Conditions MIN. TYP. MAX. 10 Unit bit %FSR %FSR %FSR 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 2.3 V AVREF < 2.7 V 0.4 0.6 1.2 6.1 12.2 27 36.7 36.7 66.6 0.4 0.6 0.6 0.4 0.6 0.6 2.5 4.5 6.5 1.5 2.0 2.0 AVSS AVREF Conversion time tCONV 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 2.3 V AVREF < 2.7 V s s s %FSR %FSR %FSR %FSR %FSR %FSR LSB LSB LSB LSB LSB %FSR V Zero-scale error Notes 1, 2 EZS 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 2.3 V AVREF < 2.7 V Full-scale error Notes 1, 2 EFS 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 2.3 V AVREF < 2.7 V Integral non-linearity error Note 1 ILE 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 2.3 V AVREF < 2.7 V Differential non-linearity error Note 1 DLE 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 2.3 V AVREF < 2.7 V Analog input voltage VAIN Notes 1. 2. Excludes quantization error (1/2 LSB). This value is indicated as a ratio (%FSR) to the full-scale value. 1.59 V POC Circuit Characteristics (TA = -40 to +85C, VSS = EVSS = 0 V) Parameter Detection voltage Power supply voltage rise inclination Minimum pulse width tPW 200 Symbol VPOC tPTH VDD: 0 V change inclination of VPOC Conditions MIN. 1.44 0.5 TYP. 1.59 MAX. 1.74 Unit V V/ms s 654 User's Manual U17397EJ4V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) www..com Standard products POC Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tPW tPTH Time Supply Voltage Rise Time (TA = -40 to +85C, VSS = EVSS = 0 V) Parameter Maximum time to rise to 1.8 V (VDD (MIN.)) (VDD: 0 V 1.8 V) Maximum time to rise to 1.8 V (VDD (MIN.)) (releasing RESET input VDD: 1.8 V) tPUP2 Symbol tPUP1 Conditions POCMODE (option byte) = 0, when RESET input is not used POCMODE (option byte) = 0, when RESET input is used 1.9 ms MIN. TYP. MAX. 3.6 Unit ms Supply Voltage Rise Time Timing * When RESET pin input is not used Supply voltage (VDD) * When RESET pin input is used Supply voltage (VDD) 1.8 V 1.8 V VPOC Time tPUP1 Time RESET pin tPUP2 2.7 V POC Circuit Characteristics (TA = -40 to +85C, VSS = EVSS = 0 V) Parameter Detection voltage on application of supply voltage Symbol VDDPOC Conditions POCMODE (option bye) = 1 MIN. 2.50 TYP. 2.70 MAX. 2.90 Unit V User's Manual U17397EJ4V0UD 655 CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard www..com products LVI Circuit Characteristics (TA = -40 to +85C, VPOC VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = 0 V) Parameter Detection voltage Supply voltage level Symbol VLVI0 VLVI1 VLVI2 VLVI3 VLVI4 VLVI5 VLVI6 VLVI7 VLVI8 VLVI9 VLVI10 VLVI11 VLVI12 VLVI13 VLVI14 VLVI15 External input pin Minimum pulse width Operation stabilization wait time Note 2 Note 1 Conditions MIN. 4.14 3.99 3.83 3.68 3.52 3.37 3.22 3.06 2.91 2.75 2.60 2.45 2.29 2.14 1.98 1.83 TYP. 4.24 4.09 3.93 3.78 3.62 3.47 3.32 3.16 3.01 2.85 2.70 2.55 2.39 2.24 2.08 1.93 1.21 MAX. 4.34 4.19 4.03 3.88 3.72 3.57 3.42 3.26 3.11 2.95 2.80 2.65 2.49 2.34 2.18 2.03 1.31 Unit V V V V V V V V V V V V V V V V V EXLVI tLW tLWAIT EXLVI < VDD, 1.8 V VDD 5.5 V 1.11 200 s 10 s Notes 1. The EXLVI/P120/INTP0 pin is used. 2. Time required from setting bit 7 (LVION) of the low-voltage detection register (LVIM) to 1 to operation stabilization Remark VLVI(n - 1) > VLVIn: n = 1 to 15 LVI Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tLW tLWAIT LVION 1 Time 656 User's Manual U17397EJ4V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) www..com Standard products Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Data retention supply voltage Symbol VDDDR Conditions MIN. 1.44 Note TYP. MAX. 5.5 Unit V Note The value depends on the POC detection voltage. When the voltage drops, the data is retained until a POC reset is effected, but data is not retained when a POC reset is effected. STOP mode Data retention mode Operation mode VDD STOP instruction execution Standby release signal (interrupt request) VDDDR Flash Memory Programming Characteristics (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) * Basic characteristics Parameter VDD supply current Erase time Notes 1, 2 Symbol IDD Conditions fXP = 10 MHz (TYP.), 20 MHz (MAX.) MIN. TYP. 4.5 20 20 10 MAX. 11.0 200 200 100 Unit mA ms ms All block Block unit Teraca Terasa Twrwa Cerwr Retention: 10 years 1 erase + 1 write after erase = 1 rewrite Note 3 Write time (in 8-bit units) Note 1 s Times Number of rewrites per chip 100 Notes 1. 2. 3. Characteristic of the flash memory. For the characteristic when a dedicated flash programmer, PG-FP4, is used and the rewrite time during self programming, see Tables 27-12 and 27-13. The prewrite time before erasure and the erase verify time (writeback time) are not included. When a product is first written after shipment, "erase write" and "write only" are both taken as one rewrite. Remarks 1. fXP: Main system clock oscillation frequency 2. For serial write operation characteristics, refer to 78K0/Kx2 Flash Memory Programming (Programmer) Application Note (U17739E). User's Manual U17397EJ4V0UD 657 www..com CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS, TARGET) Target products: PD78F0544(A), 78F0545(A), 78F0546(A), 78F0547(A) Absolute Maximum Ratings (TA = 25C) (1/2) Parameter Supply voltage Symbol VDD EVDD VSS EVSS AVREF AVSS Input voltage VI1 P00 to P06, P10 to P17, P20 to P27, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120 to P124, P140 to P145, X1, X2, XT1, XT2, RESET VI2 Output voltage Analog input voltage VO VAN ANI0 to ANI7 P60 to P63 (N-ch open drain) -0.3 to +6.5 -0.3 to VDD + 0.3 Note Conditions Ratings -0.5 to +6.5 -0.5 to +6.5 -0.5 to +0.3 -0.5 to +0.3 -0.5 to VDD + 0.3 -0.5 to +0.3 -0.3 to VDD + 0.3 Note Note Unit V V V V V V V V V V -0.3 to AVREF + 0.3 P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 -25 -10 Note Note and -0.3 to VDD + 0.3 Output current, high IOH Per pin mA Total of all pins P00 to P04, P40 to P47, -80 mA P120, P130, P140 to P145 P05, P06, P10 to P17, P30 to P33, P50 to P57, P64 to P67, P70 to P77 Per pin Total of all pins Per pin Total of all pins P121 to P124 P20 to P27 mA -55 mA -0.5 -2 -1 -4 mA mA mA mA Note Must be 6.5 V or lower. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 658 User's Manual U17397EJ4V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS, TARGET) (A) www..com grade products Absolute Maximum Ratings (TA = 25C) (2/2) Parameter Output current, low Symbol IOL Per pin Conditions P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P120, P130, P140 to P145 Total of all pins P00 to P04, P40 to P47, 200 mA P120, P130, P140 to P145 P05, P06, P10 to P17, P30 to P33, P50 to P57, P60 to P67, P70 to P77 Per pin Total of all pins Per pin Total of all pins Operating ambient temperature Storage temperature Tstg TA In normal operation mode In flash memory programming mode -65 to +150 C P121 to P124 P20 to P27 1 5 4 10 -40 to +85 mA mA mA mA C 140 mA 60 mA Ratings 30 Unit mA Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U17397EJ4V0UD 659 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS, TARGET) (A) grade www..com products X1 Oscillator Characteristics (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, VSS = EVSS = AVSS = 0 V) Resonator Ceramic resonator Recommended Circuit Parameter X1 clock Conditions 4.0 V VDD 5.5 V MIN. 1.0 Note 2 TYP. MAX. 20.0 Unit MHz VSS X1 X2 oscillation frequency (fX) Note 1 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V 4.0 V VDD 5.5 V 1.0 Note 2 10.0 C1 C2 1.0 5.0 Crystal resonator X1 clock 1.0 Note 2 20.0 MHz VSS X1 X2 oscillation frequency (fX) Note 1 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V 1.0 Note 2 10.0 C1 C2 1.0 5.0 Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. It is 2.0 MHz (MIN.) when programming on the board via UART6. Cautions 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. Since the CPU is started by the internal high-speed oscillation clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 660 User's Manual U17397EJ4V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS, TARGET) (A) www..com grade products Internal Oscillator Characteristics (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, VSS = EVSS = AVSS = 0 V) Resonator 8 MHz internal oscillator Parameter Internal high-speed oscillation clock frequency (fRH) Note Conditions RSTS = 1 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V RSTS = 0 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V MIN. 7.6 7.6 2.48 216 192 TYP. 8.0 8.0 5.0 240 240 MAX. 8.4 10.4 9.86 264 264 Unit MHz MHz MHz kHz kHz 240 kHz internal oscillator Internal low-speed oscillation clock frequency (fRL) Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Remark RSTS: Bit 7 of the internal oscillation mode register (RCM)) XT1 Oscillator Characteristics (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, VSS = EVSS = AVSS = 0 V) Resonator Crystal resonator Recommended Circuit Parameter XT1 clock oscillation frequency (fXT) Note Conditions MIN. 32 TYP. 32.768 MAX. 35 Unit kHz VSS XT2 Rd C4 XT1 C3 Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Cautions 1. When using the XT1 oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the X1 oscillator. Particular care is therefore required with the wiring method when the XT1 clock is used. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. User's Manual U17397EJ4V0UD 661 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS, TARGET) (A) grade www..com products DC Characteristics (1/4) (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Output current, high Note 1 Symbol IOH1 Conditions Per pin for P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 Total of P00 to P04, P40 to P47, Note 3 P120, P130, P140 to P145 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V Total of P05, P06, P10 to P17, P30 to P33, P50 to P57, P64 to Note 3 P67, P70 to P77 Total Note 3 MIN. TYP. MAX. -3.0 -2.5 -1.0 12.0 7.0 5.0 18.0 15.0 10.0 23.0 20.0 15.0 -0.1 -0.1 8.5 5.0 2.0 15.0 5.0 2.0 20.0 15.0 9.0 45.0 35.0 20.0 65.0 50.0 29.0 0.4 0.4 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V of all pins IOH2 Output current, low Note 2 Per pin for P20 to P27 Per pin for P121 to P124 Per pin for P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 Per pin for P60 to P63 AVREF = VDD 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V IOL1 Total of P00 to P04, P40 to P47, Note 3 P120, P130, P140 to P145 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V Total of P05, P06, P10 to P17, P30 to P33, P50 to P57, P60 to Note 3 P67, P70 to P77 Total of all pins Note 3 IOL2 Per pin for P20 to P27 Per pin for P121 to P124 AVREF = VDD Notes 1. Value of current at which the device operation is guaranteed even if the current flows from VDD to an output pin. 2. Value of current at which the device operation is guaranteed even if the current flows from an output pin to GND. 3. Specification under conditions where the duty factor is 70% (time for which current is output is 0.7 x t and time for which current is not output is 0.3 x t, where t is a specific time). The total output current of the pins at a duty factor of other than 70% can be calculated by the following expression. * Where the duty factor of IOH is n%: Total output current of pins = (IOH x 0.7)/(n x 0.01) User's Manual U17397EJ4V0UD 662 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS, TARGET) (A) www..com grade products DC Characteristics (2/4) (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Input voltage, high Symbol VIH1 VIH2 Conditions P02, P12, P13, P15, P40 to P47, P50 to P57, P64 to P67, P121 to P124, P144, P145 P00, P01, P03 to P06, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140 to P143, , EXCLK, EXCLKS, RESET P20 to P27 P60 to P63 P02, P12, P13, P15, P40 to P47, P50 to P57, P60 to P67, P121 to P124, P144, P145 P00, P01, P03 to P06, P10, P11, P14, P16, P17, P30 to P33, P70 to P77, P120, P140 to P143, EXCLK, EXCLKS, RESET P20 to P27 P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 AVREF = VDD 4.0 V VDD 5.5 V, IOH1 = -3.0 mA 2.7 V VDD < 4.0 V, IOH1 = -2.5 mA 1.8 V VDD < 2.7 V, IOH1 = -1.0 mA AVREF = VDD, IOH2 = -100 A IOH2 = -100 A 4.0 V VDD 5.5 V, IOL1 = 8.5 mA 2.7 V VDD < 4.0 V, IOL1 = 5.0 mA 1.8 V VDD < 2.7 V, IOH1 = 2.0 mA 1.8 V VDD < 2.7 V, IOL1 = 0.5 mA VOL2 P20 to P27 P121 to P124 VOL3 P60 to P63 AVREF = VDD, IOL2 = 0.4 mA IOH2 = 0.4 mA 4.0 V VDD 5.5 V, IOL1 = 15.0 mA 4.0 V VDD 5.5 V, IOL1 = 5.0 mA 2.7 V VDD < 4.0 V, IOL1 = 5.0 mA 2.7 V VDD < 4.0 V, IOL1 = 3.0 mA 1.8 V VDD < 2.7 V, IOL1 = 2.0 mA AVREF = VDD MIN. 0.7VDD 0.8VDD TYP. MAX. VDD VDD Unit V V VIH3 VIH4 Input voltage, low VIL1 VIL2 0.7AVREF 0.7VDD 0 0 AVREF 6.0 0.3VDD 0.2VDD V V V V VIL3 Output voltage, high VOH1 0 VDD - 0.7 VDD - 0.5 VDD - 0.5 VDD - 0.5 VDD - 0.5 0.3AVREF V V V V V V VOH2 P20 to P27 P121 to P124 Output voltage, low VOL1 P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P120, P130, P140 to P145 0.7 0.7 0.5 0.4 0.4 0.4 2.0 0.4 0.6 0.4 0.4 V V V V V V V V V V V Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U17397EJ4V0UD 663 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS, TARGET) (A) grade www..com products DC Characteristics (3/4) (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Input leakage current, high Symbol ILIH1 Conditions P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P120, P130, P140 to P145, FLMD0, RESET ILIH2 ILIH3 P20 to P27 P121 to 124 (X1, X2, XT1, XT2) Input leakage current, low ILIL1 P00 to P06, P10 to P17, P30 to P33, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P120, P130, P140 to P145 FLMD0, RESET ILIL2 ILIL3 P20 to P27 P121 to 124 (X1, X2, XT1, XT2) Pull-up resistor FLMD0 supply voltage RU VIL VIH VI = VSS In normal operation mode In self-programming mode VI = VSS, AVREF = VDD VI = VSS I/O port mode OSC mode 10 0 0.8VDD 20 -1 -1 -20 100 0.2VDD VDD VI = VSS VI = AVREF = VDD VI = VDD I/O port mode OSC mode 1 1 20 -1 VI = VDD MIN. TYP. MAX. 1 Unit A A A A A A A A k V V Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 664 User's Manual U17397EJ4V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS, TARGET) (A) www..com grade products DC Characteristics (4/4) (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Supply current Note 1 Symbol IDD1 Operating mode Conditions fXH = 20 MHz VDD = 5.0 V fXH = 10 MHz VDD = 5.0 V fXH = 10 MHz VDD = 3.0 V fXH = 5 MHz VDD = 3.0 V fXH = 5 MHz VDD = 2.0 V Notes 2, 3 Notes 2, 3 Notes 2, 3 Notes 2, 3 Note 2 MIN. Square wave input Resonator connection TYP. 3.2 4.5 1.6 2.3 1.5 2.2 0.9 1.3 0.7 1.0 1.4 6 15 0.8 2.0 0.4 1.0 0.2 0.5 0.4 3.0 12 1 1 0.86 MAX. 5.5 6.9 2.8 3.9 2.7 3.2 1.6 2.0 1.4 1.6 2.5 25 30 2.6 4.4 1.3 2.4 0.65 1.1 1.2 22 25 20 10 1.9 Unit mA mA mA mA mA mA mA mA mA mA mA , , Square wave input Resonator connection , Square wave input Resonator connection , Square wave input Resonator connection , Square wave input Resonator connection fRH = 8 MHz, VDD = 5.0 V fSUB = 32.768 kHz VDD = 5.0 V IDD2 HALT mode fXH = 20 MHz VDD = 5.0 V fXH = 10 MHz VDD = 5.0 V fXH = 5 MHz VDD = 3.0 V Notes 2, 3 Notes 2, 3 Note 2 Note 4 , Square wave input Resonator connection A A mA mA mA mA mA mA mA , Square wave input Resonator connection , Square wave input Resonator connection , Square wave input Resonator connection fRH = 8 MHz, VDD = 5.0 V fSUB = 32.768 kHz VDD = 5.0 V Note 5 Note 4 , Square wave input Resonator connection A A A A mA IDD3 STOP mode VDD = 5.0 V VDD = 5.0 V, TA = -40 to +70 C 2.3 V AVREF VDD A/D converter operating current IADC Note 6 During conversion at maximum Speed Not during conversion (comparator operation) Note 7 0.6 1.2 mA Watchdog timer operating current LVI operating current IWDT Note 8 During 240 kHz internal low-speed oscillation clock operation 5 10 A A ILVI Note 9 9 18 Remarks 1. fXH: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fRH: Internal high-speed oscillation clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency or external subsystem clock frequency) (Notes on next page) User's Manual U17397EJ4V0UD 665 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS, TARGET) (A) grade www..com products Notes 1. Total current flowing into the internal power supply (VDD, EVDD, AVREF), including the peripheral operation current and the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. However, the current flowing into the pull-up resistors and the output current of the port are not included. Not including the operating current of the 8 MHz internal oscillator, and the current flowing into the A/D converter, watchdog timer and LVI circuit. When AMPH (bit 0 of clock operation mode select register (OSCCTL)) = 0. Not including the operating current of the X1 oscillation, 8 MHz internal oscillator and 240 kHz internal oscillator, and the current flowing into the A/D converter, watchdog timer and LVI circuit. 5. 6. 7. 8. Not including the operating current of the 240 kHz internal oscillator and XT1 oscillation, and the current flowing into the A/D converter, watchdog timer and LVI circuit. Current flowing only to the A/D converter. The current value of the 78K0/KF2 is the sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode. Current when ADCE (bit 0 of A/D converter mode register (ADM)) = 1 and ADCS (bit 7 of ADM) = 0 Current flowing only to the watchdog timer (including the operating current of the 240 kHz internal oscillator). The current value of the 78K0/KF2 is the sum of IDD2 or IDD3 and IWDT when the watchdog timer operates in the HALT or STOP mode. 9. Current flowing only to the LVI circuit. The current value of the 78K0/KF2 is the sum of IDD2 or IDD3 and ILVI when the LVI circuit operates in the HALT or STOP mode. 2. 3. 4. 666 User's Manual U17397EJ4V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS, TARGET) (A) www..com grade products AC Characteristics (1) Basic operation (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Instruction cycle (minimum instruction execution time) Symbol TCY Conditions Main system clock (fXP) operation 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V Subsystem clock (fSUB) operation External main system clock frequency fEXCLK 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V External main system clock input high-level width, low-level width tEXCLKH, tEXCLKL 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V External subsystem clock frequency External subsystem clock input high-level width, low-level width TI000, TI010, TI001, TI011 input high-level width, low-level width tEXCLKSH, tEXCLKSL tTIH0, tTIL0 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V TI50, TI51 input frequency fTI5 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V TI50, TI51 input high-level width, low-level width tTIH5, tTIL5 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V Interrupt input high-level width, low-level width tINTH, tINTL 250 10 ns 50 50 100 1 4.0 V VDD 5.5 V 2/fsam + 0.1 Note 3 MIN. 0.1 0.2 0.4 Note 1 TYP. MAX. 32 32 32 Unit s s s s MHz MHz MHz ns ns ns kHz 114 1.0 Note 2 122 125 20.0 10.0 5.0 500 500 500 1.0 Note 2 1.0 24 48 96 32 32.768 fEXCLKS 35 12 16 s s s s 2/fsam + 0.2 Note 3 2/fsam + 0.5 Note 3 10 10 5 MHz MHz MHz ns ns ns s Key interrupt input low-level width tKR RESET low-level width tRSL s Notes 1. 2. 3. 0.38 s when operating with the 8 MHz internal oscillator. It is 2.0 MHz (MIN.) when programming on the board via UART6. Selection of fsam = fPRS, fPRS/4, fPRS/256, or fPRS, fPRS/16, fPRS/64 is possible using bits 0 and 1 (PRM000, PRM001 or PRM010, PRM011) of prescaler mode registers 00 and 01 (PRM00, PRM01). Note that when selecting the TI000 or TI001 valid edge as the count clock, fsam = fPRS. User's Manual U17397EJ4V0UD 667 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS, TARGET) (A) grade www..com products TCY vs. VDD (Main System Clock Operation) 100 32 10 5.0 Cycle time TCY [ s] 2.0 Guaranteed operation range 1.0 0.4 0.2 0.1 0.01 0 1.0 1.8 2.0 2.7 Supply voltage VDD [V] 3.0 4.0 5.0 5.5 6.0 AC Timing Test Points VIH VIL VIH VIL Test points External Main System Clock Timing, External Subsystem Clock Timing 1/fEXCLK tEXCLKL tEXCLKH EXCLK 0.8VDD (MIN.) 0.2VDD (MAX.) 1/fEXCLKS tEXCLKSL tEXCLKSH EXCLKS 0.8VDD (MIN.) 0.2VDD (MAX.) 668 User's Manual U17397EJ4V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS, TARGET) (A) www..com grade products TI Timing tTIL0 tTIH0 TI000, TI010, TI001, TI011 1/fTI5 tTIL5 tTIH5 TI50, TI51 Interrupt Request Input Timing tINTL tINTH INTP0 to INTP7 Key Interrupt Input Timing tKR KR0 to KR7 RESET Input Timing tRSL RESET User's Manual U17397EJ4V0UD 669 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS, TARGET) (A) grade www..com products (2) Serial interface (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) (a) UART6 (dedicated baud rate generator output) Parameter Transfer rate Symbol Conditions MIN. TYP. MAX. 625 Unit kbps (b) UART0 (dedicated baud rate generator output) Parameter Transfer rate Symbol Conditions MIN. TYP. MAX. 625 Unit kbps (c) IIC0 Parameter Symbol Standard Mode MIN. SCL0 clock frequency Setup time of start/restart condition Hold time Hold time when SCL0 = "L" Hold time when SCL0 = "H" Data setup time (reception) Data hold time (transmission) Note 2 Note 1 High-Speed Mode MIN. 0 0.7 0.7 1.25 1.25 0 0.23 MAX. 400 - - - - - 1.00 Unit MAX. 100 - - - - - 4.0 fSCL tSU:STA tHD:STA tLOW tHIGH tSU:DAT tHD:DAT 0 4.8 4.1 5.0 5.0 0 0.47 kHz s s s s s s Notes 1. 2. The first clock pulse is generated after this period when the start/restart condition is detected. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. 670 User's Manual U17397EJ4V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS, TARGET) (A) www..com grade products (d) CSI1n (master mode, SCK1n... internal clock output) Parameter SCK1n cycle time Symbol tKCY1 Conditions 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V SCK1n high-/low-level width tKH1, tKL1 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V SI1n setup time (to SCK1n) tSIK1 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V SI1n hold time (from SCK1n) Delay time from SCK1n to SO1n output tKSI1 tKSO1 C = 50 pF Note 2 MIN. 200 400 600 tKCY1/2 - 20 Note 1 TYP. MAX. Unit ns ns ns ns 4.0 V VDD 5.5 V tKCY1/2 - 30 Note 1 ns tKCY1/2 - 60 Note 1 ns 70 100 190 30 40 ns ns ns ns ns Notes 1. 2. This value is when high-speed system clock (fXH) is used. C is the load capacitance of the SCK1n and SO1n output lines. (e) CSI1n (slave mode, SCK1n... external clock input) Parameter SCK1n cycle time SCK1n high-/low-level width Symbol tKCY2 tKH2, tKL2 SI1n setup time (to SCK1n) SI1n hold time (from SCK1n) Delay time from SCK1n to SO1n output tSIK2 tKSI2 tKSO2 C = 50 pF Note Conditions MIN. 400 tKCY2/2 TYP. MAX. Unit ns ns 80 50 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V 120 120 180 ns ns ns ns ns Note C is the load capacitance of the SO1n output line. Remark n = 0, 1 User's Manual U17397EJ4V0UD 671 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS, TARGET) (A) grade www..com products (f) CSIA0 (master mode, SCKA0...internal clock output) Parameter SCKA0 cycle time Symbol tKCY3 Conditions 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V SCKA0 high-/low-level width tKH3, tKL3 2.7 V VDD < 4.0 V SIA0 setup time (to SCKA0) tSIK3 4.0 V VDD 5.5 V MIN. 600 1200 tKCY3/2 - 50 tKCY3/2 - 100 100 300 C = 100 pF Note TYP. MAX. Unit ns ns ns ns ns ns 200 300 ns ns ns SIA0 hold time (from SCKA0) tKSI3 Delay time from SCKA0 to SOA0 output Time from SCKA0 to STB0 tSBD 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V Busy signal setup time (to busy signal detection timing) Busy signal hold time (from busy signal detection timing) Time from busy inactive to SCKA0 tSPS tBYH 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V tBYS tKSO3 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V tKCY3/2 - 100 tKCY3 - 30 tKCY3 - 60 100 Strobe signal high-level width tSBW ns ns ns 100 150 2tKCY3 ns ns ns Note C is the load capacitance of the SCKA0 and SOA0 output lines. 672 User's Manual U17397EJ4V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS, TARGET) (A) www..com grade products (g) CSIA0 (slave mode, SCKA0...external clock input) Parameter SCKA0 cycle time Symbol tKCY4 Conditions 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V SCKA0 high-/low-level width tKH4, tKL4 SIA0 setup time (to SCKA0) tSIK4 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V MIN. 600 1200 300 600 100 300 C = 100 pF Note TYP. MAX. Unit ns ns ns ns ns ns SIA0 hold time (from SCKA0) tKSI4 Delay time from SCKA0 to SOA0 output SCKA0 rise/fall time tR4, tF4 tKSO4 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 200 300 1000 ns ns ns Note C is the load capacitance of the SOA0 output line. Serial Transfer Timing (1/2) IIC0: tLOW SCL0 tHD:DAT tHD:STA tHIGH tSU:DAT tSU:STA tHD:STA SDA0 Stop condition Start condition Restart condition Stop condition CSI1n: tKCYm tKLm tKHm SCK1n tSIKm tKSIm SI1n Input data tKSOm SO1n Output data Remark m = 1, 2 n = 0, 1 User's Manual U17397EJ4V0UD 673 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS, TARGET) (A) grade www..com products Serial Transfer Timing (2/2) CSIA0: SOA0 D2 D1 D0 D7 SIA0 D2 tSIK3, 4 tKSO3, 4 D1 tKSI3, 4 tKH3, 4 tF4 D0 D7 SCKA0 tR4 tKL3, 4 tKCY3, 4 STB0 tSBD tSBW CSIA0 (busy processing): SCKA0 7 8 9Note 10Note 10 + nNote tBYH tSPS 1 tBYS BUSY0 (active-high) Note SCKA0 does not become low level here, but the timing is illustrated so that the timing specifications can be shown. 674 User's Manual U17397EJ4V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS, TARGET) (A) www..com grade products A/D Converter Characteristics (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, 2.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Resolution Overall error Notes 1, 2 Symbol RES AINL Conditions MIN. TYP. MAX. 10 Unit bit %FSR %FSR %FSR 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 2.3 V AVREF < 2.7 V 0.4 0.6 1.2 6.1 12.2 27 36.7 36.7 66.6 0.4 0.6 0.6 0.4 0.6 0.6 2.5 4.5 6.5 1.5 2.0 2.0 AVSS AVREF Conversion time tCONV 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 2.3 V AVREF < 2.7 V s s s %FSR %FSR %FSR %FSR %FSR %FSR LSB LSB LSB LSB LSB %FSR V Zero-scale error Notes 1, 2 EZS 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 2.3 V AVREF < 2.7 V Full-scale error Notes 1, 2 EFS 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 2.3 V AVREF < 2.7 V Integral non-linearity error Note 1 ILE 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 2.3 V AVREF < 2.7 V Differential non-linearity error Note 1 DLE 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 2.3 V AVREF < 2.7 V Analog input voltage VAIN Notes 1. 2. Excludes quantization error (1/2 LSB). This value is indicated as a ratio (%FSR) to the full-scale value. 1.59 V POC Circuit Characteristics (TA = -40 to +85C, VSS = EVSS = 0 V) Parameter Detection voltage Power supply voltage rise inclination Minimum pulse width tPW 200 Symbol VPOC tPTH VDD: 0 V change inclination of VPOC Conditions MIN. 1.44 0.5 TYP. 1.59 MAX. 1.74 Unit V V/ms s User's Manual U17397EJ4V0UD 675 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS, TARGET) (A) grade www..com products POC Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tPW tPTH Time Supply Voltage Rise Time (TA = -40 to +85C, VSS = EVSS = 0 V) Parameter Maximum time to rise to 1.8 V (VDD (MIN.)) (VDD: 0 V 1.8 V) Maximum time to rise to 1.8 V (VDD (MIN.)) (releasing RESET input VDD: 1.8 V) tPUP2 Symbol tPUP1 Conditions POCMODE (option byte) = 0, when RESET input is not used POCMODE (option byte) = 0, when RESET input is used 1.9 ms MIN. TYP. MAX. 3.6 Unit ms Supply Voltage Rise Time Timing * When RESET pin input is not used Supply voltage (VDD) * When RESET pin input is used Supply voltage (VDD) 1.8 V 1.8 V VPOC Time tPUP1 Time RESET pin tPUP2 2.7 V POC Circuit Characteristics (TA = -40 to +85C, VSS = EVSS = 0 V) Parameter Detection voltage on application of supply voltage Symbol VDDPOC Conditions POCMODE (option bye) = 1 MIN. 2.50 TYP. 2.70 MAX. 2.90 Unit V 676 User's Manual U17397EJ4V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS, TARGET) (A) www..com grade products LVI Circuit Characteristics (TA = -40 to +85C, VPOC VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = 0 V) Parameter Detection voltage Supply voltage level Symbol VLVI0 VLVI1 VLVI2 VLVI3 VLVI4 VLVI5 VLVI6 VLVI7 VLVI8 VLVI9 VLVI10 VLVI11 VLVI12 VLVI13 VLVI14 VLVI15 External input pin Minimum pulse width Operation stabilization wait time Note 2 Note 1 Conditions MIN. 4.14 3.99 3.83 3.68 3.52 3.37 3.22 3.06 2.91 2.75 2.60 2.45 2.29 2.14 1.98 1.83 TYP. 4.24 4.09 3.93 3.78 3.62 3.47 3.32 3.16 3.01 2.85 2.70 2.55 2.39 2.24 2.08 1.93 1.21 MAX. 4.34 4.19 4.03 3.88 3.72 3.57 3.42 3.26 3.11 2.95 2.80 2.65 2.49 2.34 2.18 2.03 1.31 Unit V V V V V V V V V V V V V V V V V EXLVI tLW tLWAIT EXLVI < VDD, 1.8 V VDD 5.5 V 1.11 200 s 10 s Notes 1. The EXLVI/P120/INTP0 pin is used. 2. Time required from setting bit 7 (LVION) of the low-voltage detection register (LVIM) to 1 to operation stabilization Remark VLVI(n - 1) > VLVIn: n = 1 to 15 LVI Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tLW tLWAIT LVION 1 Time User's Manual U17397EJ4V0UD 677 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS, TARGET) (A) grade www..com products Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Data retention supply voltage Symbol VDDDR Conditions MIN. 1.44 Note TYP. MAX. 5.5 Unit V Note The value depends on the POC detection voltage. When the voltage drops, the data is retained until a POC reset is effected, but data is not retained when a POC reset is effected. STOP mode Data retention mode Operation mode VDD STOP instruction execution Standby release signal (interrupt request) VDDDR Flash Memory Programming Characteristics (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) * Basic characteristics Parameter VDD supply current Erase time Notes 1, 2 Symbol IDD Conditions fXP = 10 MHz (TYP.), 20 MHz (MAX.) MIN. TYP. 4.5 20 20 10 MAX. 11.0 200 200 100 Unit mA ms ms All block Block unit Teraca Terasa Twrwa Cerwr Retention: 10 years 1 erase + 1 write after erase = 1 rewrite Note 3 Write time (in 8-bit units) Note 1 s Times Number of rewrites per chip T.B.D. Notes 1. 2. 3. Characteristic of the flash memory. For the characteristic when a dedicated flash programmer, PG-FP4, is used and the rewrite time during self programming, see Tables 27-12 and 27-13. The prewrite time before erasure and the erase verify time (writeback time) are not included. When a product is first written after shipment, "erase write" and "write only" are both taken as one rewrite. Remarks 1. fXP: Main system clock oscillation frequency 2. For serial write operation characteristics, refer to 78K0/Kx2 Flash Memory Programming (Programmer) Application Note (U17739E). 678 User's Manual U17397EJ4V0UD www..com CHAPTER 32 PACKAGE DRAWINGS * PD78F0544GC-UBT-A, 78F0545GC-UBT-A, 78F0546GC-UBT-A, 78F0547GC-UBT-A, 78F0547DGC-UBT-A 80-PIN PLASTIC LQFP(14x14) HD D detail of lead end 60 61 41 40 A3 c E HE L1 L Lp 80 1 ZE ZD b x M 21 20 (UNIT:mm) ITEM D E HD DIMENSIONS 14.000.20 14.000.20 17.200.20 17.200.20 1.70 MAX. 0.1250.075 1.400.05 0.25 0.320.06 0.17 +0.03 -0.06 0.80 0.8860.15 1.600.20 3 +5 -3 0.65 0.13 0.10 0.825 0.825 P80GC-65-UBT e S A A2 S HE A A1 A2 A3 b c L y S A1 Lp L1 e NOTE Each lead centerline is located within 0.13 mm of its true position at maximum material condition. x y ZD ZE User's Manual U17397EJ4V0UD 679 CHAPTER 32 PACKAGE DRAWINGS www..com 80-PIN PLASTIC LQFP(14x14) HD D detail of lead end 60 61 41 40 A3 c E HE L1 L Lp (UNIT:mm) 80 1 ZE ZD b x M 21 20 ITEM D E HD HE A A1 A2 DIMENSIONS 14.000.20 14.000.20 17.200.20 17.200.20 1.70 MAX. 0.1250.075 1.400.05 0.25 +0.08 0.30 -0.04 0.125 +0.075 -0.025 0.80 0.8860.15 1.600.20 3 +5 -3 0.65 0.13 0.10 0.825 0.825 P80GC-65-GAD e S A A2 S A3 b c L Lp L1 y S A1 e x NOTE Each lead centerline is located within 0.13 mm of its true position at maximum material condition. y ZD ZE 680 User's Manual U17397EJ4V0UD CHAPTER 32 PACKAGE DRAWINGS www..com * PD78F0544GK-8EU-A, 78F0545GK-8EU-A, 78F0546GK-8EU-A, 78F0547GK-8EU-A, 78F0547DGK-8EU-A 80-PIN PLASTIC LQFP(FINE PITCH)(12x12) HD D detail of lead end 60 61 41 40 c A3 E HE L1 L Lp 80 1 ZE ZD b x M 21 20 ITEM D E HD HE A A1 A2 (UNIT:mm) DIMENSIONS 12.000.20 12.000.20 14.000.20 14.000.20 1.60 MAX. 0.100.05 1.400.05 0.25 0.220.05 0.145 +0.055 -0.045 0.50 0.600.15 1.000.20 3 +5 -3 0.50 0.08 0.08 1.25 1.25 P80GK-50-8EU-1 e S A A2 S A3 b c L Lp L1 y S A1 e x y NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. ZD ZE User's Manual U17397EJ4V0UD 681 CHAPTER 32 PACKAGE DRAWINGS www..com 80-PIN PLASTIC LQFP(FINE PITCH)(12x12) HD D detail of lead end 60 61 41 c 40 A3 L Lp E HE L1 (UNIT:mm) ITEM D DIMENSIONS 12.000.20 12.000.20 14.000.20 14.000.20 1.60 MAX. 0.100.05 1.400.05 0.25 +0.07 0.20 -0.03 0.125 +0.075 -0.025 0.50 0.600.15 1.000.20 +5 3 -3 0.50 0.08 0.08 1.25 1.25 P80GK-50-GAK 80 1 ZE ZD b x M 21 20 E HD HE A A1 A2 A3 b e S A A2 S c L Lp L1 e x y ZD ZE y S A1 NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. 682 User's Manual U17397EJ4V0UD www..com CHAPTER 33 RECOMMENDED SOLDERING CONDITIONS These products should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, please contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) PD78F0544GC-UBT-A, 78F0545GC-UBT-A, 78F0546GC-UBT-A, 78F0547GC-UBT-A, 78F0547DGC-UBT-ANote 1 * 80-pin plastic LQFP (12 x 12) PD78F0544GK-8EU-A, 78F0545GK-8EU-A, 78F0546GK-8EU-A, 78F0547GK-8EU-A, 78F0547DGK-8EU-ANote 1 Soldering Method Soldering Conditions Recommended Condition Symbol IR60-207-3 Infrared reflow Package peak temperature: 260C, Time: 60 seconds max. (at 220C or higher), Count: 3 times or less, Exposure limit: 7 days 20 to 72 hours) Note 2 (after that, prebake at 125C for Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) - Notes 1. The PD78F0547D has an on-chip debug function. Do not use this product for mass production because its reliability cannot be guaranteed after the on-chip debug function has been used, due to issues with respect to the number of times the flash memory can be rewritten. NEC Electronics does not accept complaints concerning this product. 2. After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). User's Manual U17397EJ4V0UD 683 www..com CHAPTER 34 CAUTIONS FOR WAIT 34.1 Cautions for Wait This product has two internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware. Because the clock of the CPU bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may be passed if an access to the CPU conflicts with an access to the peripheral hardware. When accessing the peripheral hardware that may cause a conflict, therefore, the CPU repeatedly executes processing, until the correct data is passed. As a result, the CPU does not start the next instruction processing but waits. If this happens, the number of execution clocks of an instruction increases by the number of wait clocks (for the number of wait clocks, see Tables 34-1 and 34-2). This must be noted when real-time processing is performed. 684 User's Manual U17397EJ4V0UD CHAPTER 34 CAUTIONS FOR WAIT www..com 34.2 Peripheral Hardware That Generates Wait Table 34-1 lists the registers that issue a wait request when accessed by the CPU, and the number of CPU wait clocks and Table 34-2 lists the RAM accesses that issue a wait request and the number of CPU wait clocks. Table 34-1. Registers That Generate Wait and Number of CPU Wait Clocks Peripheral Hardware Serial interface UART0 Serial interface UART6 Serial interface IIC0 A/D converter ADM ADS ADPC ADCR Write Write Write Read 1 to 5 clocks (when fAD = fPRS/2 is selected) 1 to 7 clocks (when fAD = fPRS/3 is selected) 1 to 9 clocks (when fAD = fPRS/4 is selected) 2 to 13 clocks (when fAD = fPRS/6 is selected) 2 to 17 clocks (when fAD = fPRS/8 is selected) 2 to 25 clocks (when fAD = fPRS/12 is selected) The above number of clocks is when the same source clock is selected for fCPU and fPRS. The number of wait clocks can be calculated by the following expression and under the following conditions. Caution When the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped, do not access the registers listed above using an access method in which a wait request is issued. Remark The clock is the CPU clock (fCPU). User's Manual U17397EJ4V0UD 685 CHAPTER 34 CAUTIONS FOR WAIT www..com Table 34-2. RAM Accesses That Generate Wait and Number of CPU Wait Clocks Area Buffer RAM Note Note No waits are generated when five CSIA0 operating clocks or more are inserted between writing to the RAM from the CSIA0 and writing to the buffer RAM from the CPU. 686 User's Manual U17397EJ4V0UD www..com APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the 78K0/KF2. Figure A-1 shows the development tool configuration. * Support for PC98-NX series Unless otherwise specified, products supported by IBM PC/ATTM compatibles are compatible with PC98-NX series computers. When using PC98-NX series computers, refer to the explanation for IBM PC/AT compatibles. * WindowsTM Unless otherwise specified, "Windows" means the following OSs. * Windows 98 * Windows NTTM * Windows 2000 * Windows XP User's Manual U17397EJ4V0UD 687 APPENDIX A DEVELOPMENT TOOLS www..com Figure A-1. Development Tool Configuration (1/3) (1) When using the in-circuit emulator QB-78K0KX2 Software package * Software package Language processing software * Assembler package * C compiler package * Device fileNote 1 * C library source fileNote 2 Debugging software * Integrated debuggerNote 4 * System simulator Control software * Project manager (Windows only)Note 3 Host machine (PC or EWS) USB interface cableNote 4 Power supply unitNote 4 Flash memory write environment Flash memory programmerNote 4 Flash memory write adapter QB-78K0KX2Note 4 Emulation probe Flash memory Target system Notes 1. 2. 3. 4. Download the device file for 78K0/KF2 (DF780547) from the download site for development tools (http://www.necel.com/micro/ods/eng/index.html). The C library source file is not included in the software package. The project manager PM+ is included in the assembler package. The PM+ is only used for Windows. In-circuit emulator QB-78K0KX2 is supplied with integrated debugger ID78K0-QB, simple flash memory programmer PG-FPL3, power supply unit, and USB interface cable. Any other products are sold separately. 688 User's Manual U17397EJ4V0UD APPENDIX A DEVELOPMENT TOOLS www..com Figure A-1. Development Tool Configuration (2/3) (2) When using the on-chip debug emulator QB-78K0MINI Software package * Software package Language processing software * Assembler package * C compiler package * Device fileNote 1 * C library source fileNote 2 Debugging software * Integrated debuggerNote 4 * System simulator Control software * Project manager (Windows only)Note 3 Host machine (PC or EWS) USB interface cableNote 4 Flash memory write environment Flash memory programmer QB-78K0MININote 4 Connection cableNote 4 Flash memory write adapter Flash memory Target connector Target system Notes 1. 2. 3. 4. Download the device file for 78K0/KF2 (DF780547) from the download site for development tools (http://www.necel.com/micro/ods/eng/index.html). The C library source file is not included in the software package. The project manager PM+ is included in the assembler package. The PM+ is only used for Windows. On-chip debug emulator QB-78K0MINI is supplied with integrated debugger ID78K0-QB, USB interface cable, and connection cable. Any other products are sold separately. User's Manual U17397EJ4V0UD 689 APPENDIX A DEVELOPMENT TOOLS www..com Figure A-1. Development Tool Configuration (3/3) Software package * Software package Language processing software * Assembler package * C compiler package * Device fileNote 1 * C library source fileNote 2 Debugging software * Integrated debuggerNote 1 * System simulator Control software * Project manager (Windows only)Note 3 Host machine (PC or EWS) USB interface cableNote 4 QB-MINI2Note 4 QB-MINI2Note 4 Connection cable (16-pin cable)Note 4 78K0-OCD boardNote 4 Connection cable (10-pin/16-pin cable)Note 4 Target connector Target system Notes 1. 2. 3. 4. Download the device file for 78K0/KF2 (DF780547) and the integrated debugger (ID78K0-QB) from the download site for development tools (http://www.necel.com/micro/ods/eng/index.html). The C library source file is not included in the software package. The project manager PM+ is included in the assembler package. The PM+ is only used for Windows. On-chip debug emulator QB-MINI2 is supplied with USB interface cable, connection cables (10-pin cable and 16-pin cable), and 78K0-OCD board. Any other products are sold separately. In addition, download the software for operating the QB-MINI2 from the download site for development tools (http://www.necel.com/micro/ods/eng/index.html). 690 User's Manual U17397EJ4V0UD APPENDIX A DEVELOPMENT TOOLS www..com A.1 Software Package SP78K0 78K/0 Series software package Development tools (software) common to the 78K/0 Series are combined in this package. Part number: SxxxxSP78K0 Remark xxxx in the part number differs depending on the host machine and OS used. SxxxxSP78K0 xxxx AB17 BB17 Host Machine PC-9800 series, IBM PC/AT compatibles OS Windows (Japanese version) Windows (English version) Supply Medium CD-ROM A.2 Language Processing Software RA78K0 Assembler package This assembler converts programs written in mnemonics into object codes executable with a microcontroller. This assembler is also provided with functions capable of automatically creating symbol tables and branch instruction optimization. This assembler should be used in combination with a device file (DF780547) (sold separately). Note 1 This file contains information peculiar to the device. This device file should be used in combination with a tool (RA78K0, CC78K0, SM+ for 78K0/KX2, and ID78K0-QB) (all sold separately). The corresponding OS and host machine differ depending on the tool to be used. Part number: SxxxxDF780547 CC78K0-L Note 2 This is a source file of the functions that configure the object library included in the C compiler package. This file is required to match the object library included in the C compiler package to the user's specifications. Part number: SxxxxCC78K0-L C library source file Notes 1. The DF780547 can be used in common with the RA78K0, CC78K0, SM+ for 78K0/KX2, and ID78K0QB. Download the DF780547 from the download site for development tools (http://www.necel.com/micro/ods/eng/index.html). The CC78K0-L is not included in the software package (SP78K0). User's Manual U17397EJ4V0UD 691 APPENDIX A DEVELOPMENT TOOLS www..com Remark xxxx in the part number differs depending on the host machine and OS used. SxxxxRA78K0 SxxxxCC78K0 SxxxxCC78K0-L xxxx AB17 BB17 3P17 3K17 Host Machine PC-9800 series, IBM PC/AT compatibles HP9000 series 700 SPARCstation TM TM OS Windows (Japanese version) Windows (English version) HP-UX TM Supply Medium CD-ROM (Rel. 10.10) (Rel. 4.1.4) (Rel. 2.5.1) SunOS Solaris TM TM SxxxxDF780547 xxxx AB13 BB13 Host Machine PC-9800 series, IBM PC/AT compatibles OS Windows (Japanese version) Windows (English version) Supply Medium 3.5-inch 2HD FD A.3 Control Software PM+ Project manager This is control software designed to enable efficient user program development in the Windows environment. All operations used in development of a user program, such as starting the editor, building, and starting the debugger, can be performed from the project manager. 692 User's Manual U17397EJ4V0UD APPENDIX A DEVELOPMENT TOOLS www..com A.4 Flash Memory Programming Tools A.4.1 When using flash memory programmer FG-FP4, FL-PR4, PG-FPL3, and FP-LITE3 PG-FP4, FL-PR4 Flash memory programmer PG-FPL3, FP-LITE3 Simple flash memory programmer FA-80GC-8BT-A, FA-78F0547GC-UBT-MX, FA-80GK-9EU-A, FA-78F0547GK-8EU-MX Flash memory programming adapter Simple flash memory programmer dedicated to microcontrollers with on-chip flash memory. Flash memory programming adapter used connected to the flash memory programmer for use. * FA-80GC-8BT-A, FA-78F0547GC-UBT-MX: For 80-pin plastic LQFP (GC-UBT, GC-GAD type) * FA-80GK-9EU-A, FA-78F0547GK-8EU-MX: For 80-pin plastic LQFP (GK-8EU, GK-GAK type) Flash memory programmer dedicated to microcontrollers with on-chip flash memory. Remarks 1. FL-PR4, FP-LITE3, FA-80GC-8BT-A, FA-78F0547GC-UBT-MX, FA-80GK-9EU-A, and FA- 78F0547GK-8EU-MX are products of Naito Densei Machida Mfg. Co., Ltd. TEL: +81-45-475-4191 Naito Densei Machida Mfg. Co., Ltd. 2. Use the latest version of the flash memory programming adapter. QB-MINI2 On-chip debug emulator with programming function This is a flash memory programmer dedicated to microcontrollers with on-chip flash memory. It is available also as on-chip debug emulator which serves to debug hardware and software when developing application systems using the 78K0/Kx2. When using this as flash memory programmer, it should be used in combination with a connection cable (16-pin cable) and a USB interface cable that is used to connect the host machine. Target connector specifications 16-pin general-purpose connector (2.54 mm pitch) Remarks 1. The QB-MINI2 is supplied with a USB interface cable and connection cables (10-pin cable and 16pin cable), and the 78K0-OCD board. A connection cable (10-pin cable) and the 78K0-OCD board are used only when using the on-chip debug function. 2. Download the software for operating the QB-MINI2 from the download site for development tools (http://www.necel.com/micro/ods/eng/index.html). User's Manual U17397EJ4V0UD 693 APPENDIX A DEVELOPMENT TOOLS www..com A.5 Debugging Tools (Hardware) A.5.1 When using in-circuit emulator QB-78K0KX2 QB-78K0KX2 In-circuit emulator Note This in-circuit emulator serves to debug hardware and software when developing application systems using the 78K0/Kx2. It supports to the integrated debugger (ID78K0-QB). This emulator should be used in combination with a power supply unit and emulation probe, and the USB is used to connect this emulator to the host machine. This check pin adapter is used in waveform monitoring using the oscilloscope, etc. This emulation probe is flexible type and used to connect the in-circuit emulator and target system. This exchange adapter is used to perform pin conversion from the in-circuit emulator to target connector. * QB-80GC-EA-01T: 80-pin plastic LQFP (GC-UBT, GC-GAD type) * QB-80GK-EA-01T: 80-pin plastic LQFP (GK-8EU, GA-GAK type) This space adapter is used to adjust the height between the target system and in-circuit emulator. * QB-80GC-YS-01T: 80-pin plastic LQFP (GC-UBT, GC-GAD type) * QB-80GK-YS-01T: 80-pin plastic LQFP (GK-8EU, GA-GAK type) This YQ connector is used to connect the target connector and exchange adapter. * QB-80GC-YQ-01T: 80-pin plastic LQFP (GC-UBT, GC-GAD type) * QB-80GK-YQ-01T: 80-pin plastic LQFP (GK-8EU, GA-GAK type) This mount adapter is used to mount the target device with socket. * QB-80GC-HQ-01T: 80-pin plastic LQFP (GC-UBT, GC-GAD type) * QB-80GK-HQ-01T: 80-pin plastic LQFP (GK-8EU, GA-GAK type) This target connector is used to mount on the target system. * QB-80GC-NQ-01T: 80-pin plastic LQFP (GC-UBT, GC-GAD type) * QB-80GK-NQ-01T: 80-pin plastic LQFP (GK-8EU, GA-GAK type) QB-144-CA-01 Check pin adapter QB-80-EP-01T Emulation probe QB-80GC-EA-01T, QB-80GK-EA-01T Exchange adapter QB-80GC-YS-01T, QB-80GK-YS-01T Space adapter QB-80GC-YQ-01T, QB-80GK-YQ-01T YQ connector QB-80GC-HQ-01T, QB-80GK-HQ-01T Mount adapter QB-80GC-NQ-01T, QB-80GK-NQ-01T Target connector Remarks 1. The QB-78K0KX2 is supplied with a power supply unit and USB interface cable. As control software, integrated debugger ID78K0-QB and simple flash memory programmer PG-FPL3 are supplied. 2. The packed contents differ depending on the part number, as follows. Packed Contents In-Circuit Emulator Part Number QB-78K0KX2-ZZZ QB-78K0KX2-T80GC QB-78K0KX2-T80GK QB-78K0KX2 None QB-80-EP-01T QB-80GC-EA-01T QB-80GK-EA-01T QB-80GC-YQ-01T QB-80GK-YQ-01T QB-80GC-NQ-01T QB-80GK-NQ-01T Emulation Probe Exchange Adapter YQ Connector Target Connector A.5.2 When using on-chip debug emulator QB-78K0MINI QB-78K0MINI On-chip debug emulator Note This on-chip debug emulator serves to debug hardware and software when developing application systems using the 78K0/Kx2. It supports the integrated debugger (ID78K0-QB). This emulator should be used in combination with a connection cable and a USB interface cable that is used to connect the host machine. 10-pin general-purpose connector (2.54 mm pitch) Target connector specifications Note The QB-78K0MINI is supplied with a USB interface cable and a connection cable. As control software, the integrated debugger ID78K0-QB is supplied. 694 User's Manual U17397EJ4V0UD APPENDIX A DEVELOPMENT TOOLS www..com A.5.3 When using on-chip debug emulator with programming function QB-MINI2 QB-MINI2 On-chip debug emulator with programming function This on-chip debug emulator serves to debug hardware and software when developing application systems using the 78K0/Kx2. It is available also as flash memory programmer dedicated to microcontrollers with on-chip flash memory. When using this as on-chip debug emulator, it should be used in combination with a connection cable (10pin cable or 16-pin cable), a USB interface cable that is used to connect the host machine, and the 78K0-OCD board. Target connector specifications 10-pin general-purpose connector (2.54 mm pitch) or 16-pin general-purpose connector (2.54 mm pitch) Remarks 1. The QB-MINI2 is supplied with a USB interface cable and connection cables (10-pin cable and 16pin cable), and the 78K0-OCD board. A connection cable (10-pin cable) and the 78K0-OCD board are used only when using the on-chip debug function. 2. Download the software for operating the QB-MINI2 from the download site for development tools (http://www.necel.com/micro/ods/eng/index.html). A.6 Debugging Tools (Software) SM+ for 78K0/Kx2 System simulator SM+ for 78K0/Kx2 is Windows-based software. It is used to perform debugging at the C source level or assembler level while simulating the operation of the target system on a host machine. Use of SM+ for 78K0/Kx2 allows the execution of application logical testing and performance testing on an independent basis from hardware development, thereby providing higher development efficiency and software quality. SM+ for 78K0/KX2 should be used in combination with the device file (DF780547) (sold separately). Part number: SM780547-B ID78K0-QB Integrated debugger This debugger supports the in-circuit emulators for the 78K/0 Series. The ID78K0-QB is Windows-based software. It has improved C-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory display with the trace result. It should be used in combination with the device file (sold separately). Part number: SxxxxID78K0-QB Remark xxxx in the part number differs depending on the host machine and OS used. SxxxxSM780547-B SxxxxID78K0-QB xxxx AB17 BB17 Host Machine PC-9800 series, IBM PC/AT compatibles OS Windows (Japanese version) Windows (English version) Supply Medium CD-ROM User's Manual U17397EJ4V0UD 695 www..com APPENDIX B NOTES ON TARGET SYSTEM DESIGN This chapter shows areas on the target system where component mounting is prohibited and areas where there are component mounting height restrictions when the QB-78K0KX2 is used. Figure B-1. For 80-Pin GC Package 12.05 12.05 15 13.375 15 17.375 : Exchange adapter area: : Emulation probe tip area: Note Components up to 17.45 mm in height can be mountedNote Components up to 24.45 mm in height can be mounted Note Height can be adjusted by using space adapters (each adds 2.4 mm) 696 User's Manual U17397EJ4V0UD 10 10 APPENDIX B NOTES ON TARGET SYSTEM DESIGN www..com Figure B-2. For 80-Pin GK Package 10.5 10.5 15 13.375 15 17.375 : Exchange adapter area: : Emulation probe tip area: Note Components up to 17.45 mm in height can be mounted Note Components up to 24.45 mm in height can be mountedNote Height can be adjusted by using space adapters (each adds 2.4 mm) 10 10 User's Manual U17397EJ4V0UD 697 www..com APPENDIX C REGISTER INDEX C.1 Register Index (In Alphabetical Order with Respect to Register Names) [A] A/D converter mode register (ADM) ............................................................................................................................305 A/D port configuration register (ADPC) ...............................................................................................................128, 311 Analog input channel specification register (ADS) ......................................................................................................310 Asynchronous serial interface control register 6 (ASICL6) ..........................................................................................358 Asynchronous serial interface operation mode register 0 (ASIM0) .............................................................................328 Asynchronous serial interface operation mode register 6 (ASIM6) .............................................................................352 Asynchronous serial interface reception error status register 0 (ASIS0) .....................................................................330 Asynchronous serial interface reception error status register 6 (ASIS6) .....................................................................354 Asynchronous serial interface transmission status register 6 (ASIF6) ........................................................................355 Automatic data transfer address count register 0 (ADTC0).........................................................................................414 Automatic data transfer address point specification register 0 (ADTP0) .....................................................................412 Automatic data transfer interval specification register 0 (ADTI0).................................................................................413 [B] Baud rate generator control register 0 (BRGC0) .........................................................................................................331 Baud rate generator control register 6 (BRGC6) .........................................................................................................357 [C] Capture/compare control register 00 (CRC00)............................................................................................................180 Capture/compare control register 01 (CRC01)............................................................................................................180 Clock operation mode select register (OSCCTL) ........................................................................................................136 Clock output selection register (CKS) .........................................................................................................................299 Clock selection register 6 (CKSR6).............................................................................................................................356 [D] Divisor selection register 0 (BRGCA0) ........................................................................................................................411 [E] 8-bit A/D conversion result register (ADCRH) .............................................................................................................309 8-bit timer compare register 50 (CR50) .......................................................................................................................245 8-bit timer compare register 51 (CR51) .......................................................................................................................245 8-bit timer counter 50 (TM50)......................................................................................................................................245 8-bit timer counter 51 (TM51)......................................................................................................................................245 8-bit timer H carrier control register 1 (TMCYC1)........................................................................................................268 8-bit timer H compare register 00 (CMP00).................................................................................................................263 8-bit timer H compare register 01 (CMP01).................................................................................................................263 8-bit timer H compare register 10 (CMP10).................................................................................................................263 8-bit timer H compare register 11 (CMP11).................................................................................................................263 8-bit timer H mode register 0 (TMHMD0) ....................................................................................................................264 8-bit timer H mode register 1 (TMHMD1) ....................................................................................................................264 8-bit timer mode control register 50 (TMC50)..............................................................................................................248 8-bit timer mode control register 51 (TMC51)..............................................................................................................248 698 User's Manual U17397EJ4V0UD APPENDIX C REGISTER INDEX www..com External interrupt falling edge enable register (EGN)..................................................................................................532 External interrupt rising edge enable register (EGP)...................................................................................................532 [I] IIC clock selection register 0 (IICCL0).........................................................................................................................456 IIC control register 0 (IICC0) .......................................................................................................................................447 IIC flag register 0 (IICF0) ............................................................................................................................................454 IIC function expansion register 0 (IICX0) ....................................................................................................................457 IIC shift register 0 (IIC0)..............................................................................................................................................444 IIC status register 0 (IICS0) ........................................................................................................................................452 Input switch control register (ISC) ...............................................................................................................................360 Internal expansion RAM size switching register (IXS).................................................................................................596 Internal memory size switching register (IMS) ............................................................................................................595 Internal oscillation mode register (RCM).....................................................................................................................140 Interrupt mask flag register 0H (MK0H) ......................................................................................................................530 Interrupt mask flag register 0L (MK0L)........................................................................................................................530 Interrupt mask flag register 1H (MK1H) ......................................................................................................................530 Interrupt mask flag register 1L (MK1L)........................................................................................................................530 Interrupt request flag register 0H (IF0H) .....................................................................................................................528 Interrupt request flag register 0L (IF0L) ......................................................................................................................528 Interrupt request flag register 1H (IF1H) .....................................................................................................................528 Interrupt request flag register 1L (IF1L) ......................................................................................................................528 [K] Key return mode register (KRM) .................................................................................................................................542 [L] Low-voltage detection level selection register (LVIS)..................................................................................................575 Low-voltage detection register (LVIM) ........................................................................................................................573 [M] Main clock mode register (MCM) ................................................................................................................................142 Main OSC control register (MOC) ...............................................................................................................................141 Memory bank select register (BANK)............................................................................................................................85 Multiplication/division data register A0 (MDA0H, MDA0L) ..........................................................................................514 Multiplication/division data register B0 (MDB0)...........................................................................................................515 Multiplier/divider control register 0 (DMUC0) ..............................................................................................................516 [O] Oscillation stabilization time counter status register (OSTC) ..............................................................................143, 544 Oscillation stabilization time select register (OSTS)............................................................................................144, 545 [P] Port mode register 0 (PM0)......................................................................................................................... 124, 188, 389 Port mode register 1 (PM1)................................................................................................. 124, 250, 268, 332, 360, 389 Port mode register 2 (PM2).................................................................................................................................124, 312 Port mode register 3 (PM3).................................................................................................................................124, 250 Port mode register 4 (PM4).........................................................................................................................................124 Port mode register 5 (PM5).........................................................................................................................................124 User's Manual U17397EJ4V0UD 699 APPENDIX C REGISTER INDEX www..com Port mode register 6 (PM6) .................................................................................................................................124, 459 Port mode register 7 (PM7) .........................................................................................................................................124 Port mode register 12 (PM12) ............................................................................................................................124, 576 Port mode register 14 (PM14) .....................................................................................................................124, 301, 414 Port register 0 (P0)......................................................................................................................................................126 Port register 1 (P1)......................................................................................................................................................126 Port register 2 (P2)......................................................................................................................................................126 Port register 3 (P3)......................................................................................................................................................126 Port register 4 (P4)......................................................................................................................................................126 Port register 5 (P5)......................................................................................................................................................126 Port register 6 (P6)......................................................................................................................................................126 Port register 7 (P7)......................................................................................................................................................126 Port register 12 (P12) ..................................................................................................................................................126 Port register 13 (P13) ..................................................................................................................................................126 Port register 14 (P14) ..................................................................................................................................................126 Prescaler mode register 00 (PRM00) ..........................................................................................................................185 Prescaler mode register 01 (PRM01) ..........................................................................................................................185 Priority specification flag register 0H (PR0H) ..............................................................................................................531 Priority specification flag register 0L (PR0L) ...............................................................................................................531 Priority specification flag register 1H (PR1H) ..............................................................................................................531 Priority specification flag register 1L (PR1L) ...............................................................................................................531 Processor clock control register (PCC) .......................................................................................................................138 Pull-up resistor option register 0 (PU0) .......................................................................................................................127 Pull-up resistor option register 1 (PU1) .......................................................................................................................127 Pull-up resistor option register 3 (PU3) .......................................................................................................................127 Pull-up resistor option register 4 (PU4) .......................................................................................................................127 Pull-up resistor option register 5 (PU5) .......................................................................................................................127 Pull-up resistor option register 6 (PU6) .......................................................................................................................127 Pull-up resistor option register 7 (PU7) .......................................................................................................................127 Pull-up resistor option register 12 (PU12) ...................................................................................................................127 Pull-up resistor option register 14 (PU14) ...................................................................................................................127 [R] Receive buffer register 0 (RXB0) ................................................................................................................................327 Receive buffer register 6 (RXB6) ................................................................................................................................351 Receive shift register 0 (RXS0) ...................................................................................................................................327 Receive shift register 6 (RXS6) ...................................................................................................................................351 Remainder data register 0 (SDR0)..............................................................................................................................514 Reset control flag register (RESF) ..............................................................................................................................565 [S] Serial clock selection register 10 (CSIC10) .................................................................................................................387 Serial clock selection register 11 (CSIC11) .................................................................................................................387 Serial I/O shift register 0 (SIOA0)................................................................................................................................406 Serial I/O shift register 10 (SIO10) ..............................................................................................................................384 Serial I/O shift register 11 (SIO11) ..............................................................................................................................384 700 User's Manual U17397EJ4V0UD APPENDIX C REGISTER INDEX www..com Serial operation mode register 10 (CSIM10)...............................................................................................................385 Serial operation mode register 11 (CSIM11)...............................................................................................................385 Serial operation mode specification register 0 (CSIMA0)............................................................................................407 Serial status register 0 (CSIS0)...................................................................................................................................408 Serial trigger register 0 (CSIT0) ..................................................................................................................................410 Slave address register 0 (SVA0).................................................................................................................................444 16-bit timer capture/compare register 000 (CR000)....................................................................................................173 16-bit timer capture/compare register 001 (CR001)....................................................................................................173 16-bit timer capture/compare register 010 (CR010)....................................................................................................173 16-bit timer capture/compare register 011 (CR011)....................................................................................................173 16-bit timer counter 00 (TM00)....................................................................................................................................172 16-bit timer counter 01 (TM01)....................................................................................................................................172 16-bit timer mode control register 00 (TMC00) ...........................................................................................................177 16-bit timer mode control register 01 (TMC01) ...........................................................................................................177 16-bit timer output control register 00 (TOC00)...........................................................................................................182 16-bit timer output control register 01 (TOC01)...........................................................................................................182 [T] Timer clock selection register 50 (TCL50) ..................................................................................................................246 Timer clock selection register 51 (TCL51) ..................................................................................................................246 10-bit A/D conversion result register (ADCR)..............................................................................................................308 Transmit buffer register 6 (TXB6)................................................................................................................................351 Transmit buffer register 10 (SOTB10).........................................................................................................................384 Transmit buffer register 11 (SOTB11).........................................................................................................................384 Transmit shift register 0 (TXS0) ..................................................................................................................................327 Transmit shift register 6 (TXS6) ..................................................................................................................................351 [W] Watch timer operation mode register (WTM) ..............................................................................................................287 Watchdog timer enable register (WDTE) ....................................................................................................................293 User's Manual U17397EJ4V0UD 701 APPENDIX C REGISTER INDEX www..com C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) [A] ADCR: ADCRH: ADM: ADPC: ADS: ADTC0: ADTI0: ADTP0: ASICL6: ASIF6: ASIM0: ASIM6: ASIS0: ASIS6: [B] BANK: BRGC0: BRGC6: BRGCA0: [C] CKS: CKSR6: CMP00: CMP01: CMP10: CMP11: CR000: CR001: CR010: CR011: CR50: CR51: CRC00: CRC01: CSIC10: CSIC11: CSIM10: CSIM11: CSIMA0: CSIS0: CSIT0: Clock output selection register ................................................................................................................299 Clock selection register 6 ........................................................................................................................356 8-bit timer H compare register 00 ............................................................................................................263 8-bit timer H compare register 01 ............................................................................................................263 8-bit timer H compare register 10 ............................................................................................................263 8-bit timer H compare register 11 ............................................................................................................263 16-bit timer capture/compare register 000...............................................................................................173 16-bit timer capture/compare register 001...............................................................................................173 16-bit timer capture/compare register 010...............................................................................................173 16-bit timer capture/compare register 011...............................................................................................173 8-bit timer compare register 50................................................................................................................245 8-bit timer compare register 51................................................................................................................245 Capture/compare control register 00 .......................................................................................................180 Capture/compare control register 01 .......................................................................................................180 Serial clock selection register 10 .............................................................................................................387 Serial clock selection register 11 .............................................................................................................387 Serial operation mode register 10............................................................................................................385 Serial operation mode register 11............................................................................................................385 Serial operation mode specification register 0.........................................................................................407 Serial status register 0.............................................................................................................................408 Serial trigger register 0 ............................................................................................................................410 User's Manual U17397EJ4V0UD 10-bit A/D conversion result register........................................................................................................308 8-bit A/D conversion result register..........................................................................................................309 A/D converter mode register....................................................................................................................305 A/D port configuration register .........................................................................................................128, 311 Analog input channel specification register .............................................................................................310 Automatic data transfer address count register 0 ....................................................................................414 Automatic data transfer interval specification register 0 ..........................................................................413 Automatic data transfer address point specification register 0 ................................................................412 Asynchronous serial interface control register 6......................................................................................358 Asynchronous serial interface transmission status register 6 ..................................................................355 Asynchronous serial interface operation mode register 0........................................................................328 Asynchronous serial interface operation mode register 6........................................................................352 Asynchronous serial interface reception error status register 0...............................................................330 Asynchronous serial interface reception error status register 6...............................................................354 Memory bank select register .................................................................................................................... 85 Baud rate generator control register 0 .....................................................................................................331 Baud rate generator control register 6 .....................................................................................................357 Divisor selection register 0 ......................................................................................................................411 702 APPENDIX C REGISTER INDEX www..com [D] DMUC0: [E] EGN: EGP: [I] IF0H: IF0L: IF1H: IF1L: IIC0: IICC0: IICCL0: IICF0: IICS0: IICX0: IMS: ISC: IXS: [K] KRM: [L] LVIM: LVIS: [M] MCM: MDA0H: MDA0L: MDB0: MK0H: MK0L: MK1H: MK1L: MOC: [O] OSCCTL: OSTC: OSTS: [P] P0: P1: P2: Port register 0..........................................................................................................................................126 Port register 1..........................................................................................................................................126 Port register 2..........................................................................................................................................126 User's Manual U17397EJ4V0UD Multiplier/divider control register 0...........................................................................................................516 External interrupt falling edge enable register .........................................................................................532 External interrupt rising edge enable register..........................................................................................532 Interrupt request flag register 0H.............................................................................................................528 Interrupt request flag register 0L .............................................................................................................528 Interrupt request flag register 1H.............................................................................................................528 Interrupt request flag register 1L .............................................................................................................528 IIC shift register 0 ....................................................................................................................................444 IIC control register 0 ................................................................................................................................447 IIC clock selection register 0 ...................................................................................................................456 IIC flag register 0.....................................................................................................................................454 IIC status register 0 .................................................................................................................................452 IIC function expansion register 0.............................................................................................................457 Internal memory size switching register ..................................................................................................595 Input switch control register.....................................................................................................................360 Internal expansion RAM size switching register ......................................................................................596 Key return mode register.........................................................................................................................542 Low-voltage detection register ................................................................................................................573 Low-voltage detection level selection register .........................................................................................575 Main clock mode register ........................................................................................................................142 Multiplication/division data register A0 ....................................................................................................514 Multiplication/division data register A0 ....................................................................................................514 Multiplication/division data register B0 ....................................................................................................515 Interrupt mask flag register 0H ................................................................................................................530 Interrupt mask flag register 0L.................................................................................................................530 Interrupt mask flag register 1H ................................................................................................................530 Interrupt mask flag register 1L.................................................................................................................530 Main OSC control register .......................................................................................................................141 Clock operation mode select register ......................................................................................................136 Oscillation stabilization time counter status register ........................................................................143, 544 Oscillation stabilization time select register .....................................................................................144, 545 703 APPENDIX C REGISTER INDEX www..com P3: P4: P5: P6: P7: P12: P13: P14: PCC: PM0: PM1: PM2: PM3: PM4: PM5: PM6: PM7: PM12: PM14: PR0H: PR0L: PR1H: PR1L: PRM00: PRM01: PU0: PU1: PU3: PU4: PU5: PU6: PU7: PU12: PU14: [R] RCM: RESF: RXB0: RXB6: RXS0: RXS6: [S] SDR0: SIO10: Port register 3 ..........................................................................................................................................126 Port register 4 ..........................................................................................................................................126 Port register 5 ..........................................................................................................................................126 Port register 6 ..........................................................................................................................................126 Port register 7 ..........................................................................................................................................126 Port register 12 ........................................................................................................................................126 Port register 13 ........................................................................................................................................126 Port register 14 ........................................................................................................................................126 Processor clock control register...............................................................................................................138 Port mode register 0 ................................................................................................................124, 188, 389 Port mode register 1 ........................................................................................124, 250, 268, 332, 360, 389 Port mode register 2 ........................................................................................................................124, 312 Port mode register 3 ........................................................................................................................124, 250 Port mode register 4 ................................................................................................................................124 Port mode register 5 ................................................................................................................................124 Port mode register 6 ........................................................................................................................124, 459 Port mode register 7 ................................................................................................................................124 Port mode register 12 ......................................................................................................................124, 576 Port mode register 14 ..............................................................................................................124, 301, 414 Priority specification flag register 0H .......................................................................................................531 Priority specification flag register 0L ........................................................................................................531 Priority specification flag register 1H .......................................................................................................531 Priority specification flag register 1L ........................................................................................................531 Prescaler mode register 00 .....................................................................................................................185 Prescaler mode register 01 .....................................................................................................................185 Pull-up resistor option register 0 ..............................................................................................................127 Pull-up resistor option register 1 ..............................................................................................................127 Pull-up resistor option register 3 ..............................................................................................................127 Pull-up resistor option register 4 ..............................................................................................................127 Pull-up resistor option register 5 ..............................................................................................................127 Pull-up resistor option register 6 ..............................................................................................................127 Pull-up resistor option register 7 ..............................................................................................................127 Pull-up resistor option register 12 ............................................................................................................127 Pull-up resistor option register 14 ............................................................................................................127 Internal oscillation mode register .............................................................................................................140 Reset control flag register........................................................................................................................565 Receive buffer register 0 .........................................................................................................................327 Receive buffer register 6 .........................................................................................................................351 Receive shift register 0 ............................................................................................................................327 Receive shift register 6 ............................................................................................................................351 Remainder data register 0 .......................................................................................................................514 Serial I/O shift register 10 ........................................................................................................................384 User's Manual U17397EJ4V0UD 704 APPENDIX C REGISTER INDEX www..com SIO11: SIOA0: SOTB10: SOTB11: SVA0: [T] TCL50: TCL51: TM00: TM01: TM50: TM51: TMC00: TMC01: TMC50: TMC51: TMCYC1: Serial I/O shift register 11........................................................................................................................384 Serial I/O shift register 0..........................................................................................................................406 Transmit buffer register 10 ......................................................................................................................384 Transmit buffer register 11 ......................................................................................................................384 Slave address register 0..........................................................................................................................444 Timer clock selection register 50.............................................................................................................246 Timer clock selection register 51.............................................................................................................246 16-bit timer counter 00 ............................................................................................................................172 16-bit timer counter 01 ............................................................................................................................172 8-bit timer counter 50 ..............................................................................................................................245 8-bit timer counter 51 ..............................................................................................................................245 16-bit timer mode control register 00.......................................................................................................177 16-bit timer mode control register 01.......................................................................................................177 8-bit timer mode control register 50.........................................................................................................248 8-bit timer mode control register 51.........................................................................................................248 8-bit timer H carrier control register 1 ......................................................................................................268 TMHMD0: 8-bit timer H mode register 0...................................................................................................................264 TMHMD1: 8-bit timer H mode register 1...................................................................................................................264 TOC00: TOC01: TXB6: TXS0: TXS6: [W] WDTE: WTM: Watchdog timer enable register ..............................................................................................................293 Watch timer operation mode register ......................................................................................................287 16-bit timer output control register 00......................................................................................................182 16-bit timer output control register 01......................................................................................................182 Transmit buffer register 6 ........................................................................................................................351 Transmit shift register 0...........................................................................................................................327 Transmit shift register 6...........................................................................................................................351 User's Manual U17397EJ4V0UD 705 www..com APPENDIX D LIST OF CAUTIONS This appendix lists cautions described in this document. "Classification (hard/soft)" in table is as follows. Hard: Soft: Hard Classification Cautions for microcontroller internal/external hardware Cautions for software such as register settings or programs (1/27) Details of Function Cautions Page Function Chapter 1 Chapter Pin function AVSS, EVSS EVDD REGC ANI0/P20 to ANI7/P27 Make AVSS and EVSS the same potential as VSS. Make EVDD the same potential as VDD. Connect the REGC pin to VSS via a capacitor (0.47 to 1 F: recommended). ANI0/P20 to ANI7/P27 are set in the analog input mode after release of reset. p. 22 p. 22 p. 22 pp. 22, 36 Chapter 2 Hard Pin function P31/INTP2/ OCD1A In the product with an on-chip debug function (PD78F0547D), be sure to pull the p. 36 P31/INTP2/OCD1A pin down before a reset, release to prevent malfunction. For products without an on-chip debug function (other than the PD78F0547D) and having a product rank of "I", "K", or "E", and for the product with an on-chip debug function (PD78F0547D), connect P31/INTP2/OCD1A as follows when writing the flash memory with a flash memory programmer. * P31/INTP2/OCD1A: Connect to EVSS via a resistor (10 k: recommended). The above connection is not necessary when writing the flash memory by means of self programming. p. 36 P121/X1 For products without an on-chip debug function (other than the PD78F0547D) p. 39 and having a product rank of "I", "K", or "E", and for the product with an on-chip debug function (PD78F0547D), connect P121/X1/OCD0A as follows when writing the flash memory with a flash memory programmer. * P121/X1/OCD0A: When using this pin as a port, connect it to VSS via a resistor (10 k: recommended) (in the input mode) or leave it open (in the output mode). The above connection is not necessary when writing the flash memory by means of self programming. Keep the wiring length as short as possible for the broken-line part in the above figure. p. 40 p. 46 REGC pin Chapter 3 Soft Memory space IMS, IXS: Internal Regardless of the internal memory capacity, the initial values of the internal memory size memory size switching register (IMS) and internal expansion RAM size switching switching register, register (IXS) of all products in the 78K0/KF2 are fixed (IMS = CFH, IXS = 0CH). internal expansion Therefore, set the value corresponding to each product as indicated below. RAM size To set the memory size, set IMS and then IXS. Set the memory size so that the switching register internal ROM and internal expansion RAM areas do not overlap. Memory bank Instructions cannot be fetched between different memory banks. p. 46 p. 55 Branch and access cannot be directly executed between different memory banks. p. 55 Execute branch or access between different memory banks via the common area. Allocate interrupt servicing in the common area. p. 55 An instruction that extends from 7FFFH to 8000H can only be executed in memory p. 55 bank 0. SFR: Special Do not access addresses to which SFRs are not assigned. function register SP: Stack pointer Since reset signal generation makes the SP contents undefined, be sure to initialize the SP before using the stack. p. 56 p. 62 706 User's Manual U17397EJ4V0UD APPENDIX D LIST OF CAUTIONS www..com (2/27) Soft Classification Function Chapter Details of Function Cautions Page Chapter 4 Memory bank switching function (PD78F0546 , 78F0547, 78F0547D only) BANK: Memory bank select register Be sure to change the value of the BANK register in the common area (0000H to 7FFFH). If the value of the BANK register is changed in the bank area (8000H to BFFFH), an inadvertent program loop occurs in the CPU. Therefore, never change the value of the BANK register in the bank area. Instructions cannot be fetched between different memory banks. Branching and accessing cannot be directly executed between different memory banks. Execute branching or accessing between different memory banks via the common area. Allocate interrupt servicing in the common area. An instruction that extends from 7FFFH to 8000H can only be executed in memory bank 0. p. 85 Memory bank p. 86 p. 86 p. 86 p. 86 Chapter 5 Soft Port function P02/SO11, P04/SCK11 To use P02/SO11 and P04/SCK11 as general-purpose ports, set serial operation p. 97 mode register 11 (CSIM11) and serial clock selection register 11 (CSIC11) to the default status (00H). p. 101 P10/SCK10/TxD0, To use P10/SCK10/TxD0 and P12/SO10 as general-purpose ports, set serial operation mode register 10 (CSIM10) and serial clock selection register 10 P12/SO10 (CSIC10) to the default status (00H). Hard Port 2 P31/INTP2/ OCD1A Make the AVREF pin the same potential as the VDD pin when port 2 is used as a digital port. p. 106 In the product with an on-chip debug function (PD78F0547D), be sure to pull the p. 107 P31/INTP2/OCD1A pin down before a reset release, to prevent malfunction. For products without an on-chip debug function (other than the PD78F0547D) and having a product rank of "I", "K", or "E", and for the product with an on-chip debug function (PD78F0547D), connect P31/INTP2/OCD1A as follows when writing the flash memory with a flash memory programmer. * P31/INTP2/OCD1A: Connect to EVSS via a resistor (10 k: recommended). The above connection is not necessary when writing the flash memory by means of self programming. p. 107 Soft P121/X1/OCD0A, P122/X2/EXCLK/ OCD0B, P123/XT1, P124/XT2/EXCLKS When using the P121 to P124 pins to connect a resonator for the main system p. 116 clock (X1, X2) or subsystem clock (XT1, XT2), or to input an external clock for the main system clock (EXCLK) or subsystem clock (EXCLKS), the X1 oscillation mode, XT1 oscillation mode, or external clock input mode must be set by using the clock operation mode select register (OSCCTL) (for details, see 6.3 (1) Clock operation mode select register (OSCCTL) and (3) Setting of operation mode for subsystem clock pin). The reset value of OSCCTL is 00H (all of the P121 to P124 pins are I/O port pins). At this time, setting of the PM121 to PM124 and P121 to P124 pins is not necessary. p. 116 For products without an on-chip debug function (other than the PD78F0547D) and having a product rank of "I", "K", or "E", and for the product with an on-chip debug function (PD78F0547D), connect P121/X1/OCD0A as follows when writing the flash memory with a flash memory programmer. * P121/X1/OCD0A: When using this pin as a port, connect it to VSS via a resistor (10 k: recommended) (in the input mode) or leave it open (in the output mode). The above connection is not necessary when writing the flash memory by means of self programming. Port mode registers ADPC: A/D port configuration register Be sure to set bit 7 of PM0, bits 4 to 7 of PM3, bits 5 to 7 of PM12, and bits 6 and p. 125 7 of PM14 to "1". Set the channel used for A/D conversion to the input mode by using port mode register 2 (PM2). If data is written to ADPC, a wait cycle is generated. Do not write data to ADPC when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 34 CAUTIONS FOR WAIT. p. 128 p. 128 User's Manual U17397EJ4V0UD 707 APPENDIX D LIST OF CAUTIONS www..com (3/27) Chapter 5 Chapter Soft Classification Function Details of Function Cautions Page Port function 1-bit manipulation instruction for port register n (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit. Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode. p. 132 Chapter 6 Soft Clock generator OSCSTL: Clock Be sure to set AMPH to 1 if the high-speed system clock oscillation frequency p. 137 operation mode exceeds 10 MHz. select register Set AMPH before setting the peripheral functions after a reset release. The value p. 137 of AMPH can be changed only once after a reset release. When the high-speed system clock (X1 oscillation) is selected as the CPU clock, supply of the CPU clock is stopped for 4.06 to 16.12 s after AMPH is set to 1. When the high-speed system clock (external clock input) is selected as the CPU clock, supply of the CPU clock is stopped for the duration of 160 external clocks after AMPH is set to 1. If the STOP instruction is executed when AMPH = 1, supply of the CPU clock is stopped for 4.06 to 16.12 s after the STOP mode is released when the internal high-speed oscillation clock is selected as the CPU clock, or for the duration of 160 external clocks when the high-speed system clock (external clock input) is selected as the CPU clock. When the high-speed system clock (X1 oscillation) is selected as the CPU clock, the oscillation stabilization time is counted after the STOP mode is released. To change the value of EXCLK and OSCSEL, be sure to confirm that bit 7 (MSTOP) of the main OSC control register (MOC) is 1 (the X1 oscillator stops or the external clock from the EXCLK pin is disabled). p. 137 p. 137 PCC: Processor Be sure to clear bits 3 and 7 to "0". p. 138 clock control Confirm that bit 5 (CLS) of the processor clock control register (PCC) is 0 (CPU is p. 139 register operating with main system clock) when changing the current values of XTSTART, EXCLKS, and OSCSELS. RCM: Internal When setting RSTOP to 1, be sure to confirm that the CPU operates with a clock oscillation mode other than the internal high-speed oscillation clock. Specifically, set under either register of the following conditions. * When MCS = 1 (when CPU operates with the high-speed system clock) * When CLS = 1 (when CPU operates with the subsystem clock) In addition, stop peripheral hardware that is operating on the internal high-speed oscillation clock before setting RSTOP to 1. MOC: Main OSC When setting MSTOP to 1, be sure to confirm that the CPU operates with a clock control register other than the high-speed system clock. Specifically, set under either of the following conditions. * When MCS = 0 (when CPU operates with the internal high-speed oscillation clock) * When CLS = 1 (when CPU operates with the subsystem clock) In addition, stop peripheral hardware that is operating on the high-speed system clock before setting MSTOP to 1. p. 140 p. 141 Do not clear MSTOP to 0 while bit 6 (OSCSEL) of the clock operation mode select p. 141 register (OSCCTL) is 0 (I/O port mode). The peripheral hardware cannot operate when the peripheral hardware clock is p. 141 stopped. To resume the operation of the peripheral hardware after the peripheral hardware clock has been stopped, initialize the peripheral hardware. Hard MCM: Main clock mode register XSEL can be changed only once after a reset release. p. 142 A clock other than fPRS is supplied to the following peripheral functions regardless p. 142 of the setting of XSEL and MCM0. * Watchdog timer (operates with internal low-speed oscillation clock) 7 9 * When "fRL", "fRL/2 ", or "fRL/2 " is selected as the count clock for 8-bit timer H1 (operates with internal low-speed oscillation clock) * Peripheral hardware selects the external clock as the clock source (Except when the external count clock of TM0n (n = 0, 1) is selected (TI00n pin valid edge)) 708 User's Manual U17397EJ4V0UD APPENDIX D LIST OF CAUTIONS www..com (4/27) Chapter 6 Chapter Soft Classification Function Details of Function Cautions Page Clock generator OSTC: Oscillation stabilization time counter status register After the above time has elapsed, the bits are set to 1 in order from MOST11 and p. 143 remain 1. p. 143 The oscillation stabilization time counter counts up to the oscillation stabilization time set by OSTS. If the STOP mode is entered and then released while the internal high-speed oscillation clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. The X1 clock oscillation stabilization wait time does not include the time until clock p. 143 oscillation starts ("a" below). Soft Hard OSTS: Oscillation stabilization time select register To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS before executing the STOP instruction. Do not change the value of the OSTS register during the X1 clock oscillation stabilization time. p. 144 p. 144 p. 144 The oscillation stabilization time counter counts up to the oscillation stabilization time set by OSTS. If the STOP mode is entered and then released while the internal high-speed oscillation clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. Hard The X1 clock oscillation stabilization wait time does not include the time until clock p. 144 oscillation starts ("a" below). X1/XT1 oscillator - p. 146 When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the broken lines in the Figures 6-9 and 6-10 to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. Note that the XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption. When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1, resulting in malfunctioning. Clock generator operation when power supply voltage is turned on - p. 147 p. 151 If the voltage rises with a slope of less than 0.5 V/ms (MIN.) from power application until the voltage reaches 1.8 V, input a low level to the RESET pin from power application until the voltage reaches 1.8 V, or set the 2.7 V/1.59 V POC mode by using the option byte (POCMODE = 1) (see Figure 6-13). By doing so, the CPU operates with the same timing as <2> and thereafter in Figure 6-12 after reset release by the RESET pin. It is not necessary to wait for the oscillation stabilization time when an external clock input from the EXCLK and EXCLKS pins is used. pp. 151, 152 p. 152 A voltage oscillation stabilization time of 1.93 to 5.39 ms is required after the power supply voltage reaches 1.59 V (TYP.). If the supply voltage rises from 1.59 V (TYP.) to 2.7 V (TYP.) within 1.93 ms, the power supply oscillation stabilization time of 0 to 5.39 ms is automatically generated before reset processing. Controlling X1/P121, The X1/P121 and X2/EXCLK/P122 pins are in the I/O port mode after a reset high-speed X2/EXCLK/P122 release. system X1 clock Do not change the value of EXCLK and OSCSEL while the X1 clock is operating. clock p. 153 p. 153 User's Manual U17397EJ4V0UD 709 APPENDIX D LIST OF CAUTIONS www..com (5/27) Classification Function Chapter Details of Function Cautions Page Chapter 6 Soft Controlling X1 clock high-speed system clock External main system clock Set the X1 clock after the supply voltage has reached the operable voltage of the p. 154 clock to be used (see CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) or CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS, TARGET)). Do not change the value of EXCLK and OSCSEL while the external main systerm p. 154 clock is operating. Set the external main system clock after the supply voltage has reached the operable voltage of the clock to be used (see CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) or CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS, TARGET)). p. 154 Main system clock High-speed system clock If the high-speed system clock is selected as the main system clock, a clock other p. 155 than the high-speed system clock cannot be set as the peripheral hardware clock. Be sure to confirm that MCS = 0 or CLS = 1 when setting MSTOP to 1. In addition, stop peripheral hardware that is operating on the high-speed system clock. p. 156 p. 158 Be sure to confirm that MCS = 1 or CLS = 1 when setting RSTOP to 1. In Controlling Internal highspeed oscillation addition, stop peripheral hardware that is operating on the internal high-speed internal oscillation clock. high-speed clock oscillation clock Controlling XT1/P123, The XT1/P123 and XT2/EXCLKS/P124 pins are in the I/O port mode after a reset p. 158 subsystem XT2/EXCLKS/P1 release. clock 24 XT1 clock, Do not change the value of XTSTART, EXCLKS, and OSCSELS while the external subsystem clock is operating. subsystem clock Subsystem clock Be sure to confirm that CLS = 0 when clearing OSCSELS to 0. In addition, stop the watch timer if it is operating on the subsystem clock. The subsystem clock oscillation cannot be stopped using the STOP instruction. pp. 158, 159 p. 159 p. 159 If "Internal low-speed oscillator cannot be stopped" is selected by the option byte, p. 160 Controlling Internal lowspeed oscillation oscillation of the internal low-speed oscillation clock cannot be controlled. internal low-speed clock oscillation clock CPU clock - Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) or CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS, TARGET)). pp. 162, 163, 165 p. 167 Selection of the main system clock cycle division factor (PCC0 to PCC2) and switchover from the main system clock to the subsystem clock (changing CSS from 0 to 1) should not be set simultaneously. Simultaneous setting is possible, however, for selection of the main system clock cycle division factor (PCC0 to PCC2) and switchover from the subsystem clock to the main system clock (changing CSS from 1 to 0). When switching the internal high-speed oscillation clock to the high-speed system p. 168 clock, bit 2 (XSEL) of MCM must be set to 1 in advance. The value of XSEL can be changed only once after a reset release. Chapter 7 Hard 16-bit timer/event counters 00, 01 - The valid edge of TI010 and timer output (TO00) cannot be used for the P01 pin at the same time, and the valid edge of TI011 and timer output (TO01) cannot be used for the P06 pin at the same time. Select either of the functions. If clearing of bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n (TMC0n) to 00 and input of the capture trigger conflict, then the captured data is undefined. To change the mode from the capture mode to the comparison mode, first clear the TMC0n3 and TMC0n2 bits to 00, and then change the setting. A value that has been once captured remains stored in CR00n unless the device is reset. If the mode has been changed to the comparison mode, be sure to set a comparison value. p. 172 Soft p. 172 p. 172 710 User's Manual U17397EJ4V0UD APPENDIX D LIST OF CAUTIONS www..com (6/27) Classification Function Chapter Details of Function Cautions Page Chapter 7 Soft 16-bit TM0n: 16-bit timer timer/event counter 0n counters CR00n, CR01n: 00, 01 16-bit timer capture/compare registers 00n, 01n Even if TM0n is read, the value is not captured by CR01n. CR00n does not perform the capture operation when it is set in the comparison mode, even if a capture trigger is input to it. CR01n does not perform the capture operation when it is set in the comparison mode, even if a capture trigger is input to it. p. 173 p. 174 p. 174 To capture the count value of the TM0n register to the CR00n register by using p. 176 the phase reverse to that input to the TI00n pin, the interrupt request signal (INTTM00n) is not generated after the value has been captured. If the valid edge is detected on the TI01n pin during this operation, the capture operation is not performed but the INTTM00n signal is generated as an external interrupt signal. To not use the external interrupt, mask the INTTM00n signal. TMC0n: 16-bit 16-bit timer/event counter 0n starts operation at the moment TMC0n2 and p. 177 timer mode TMC0n3 are set to values other than 00 (operation stop mode), respectively. Set control register 0n TMC0n2 and TMC0n3 to 00 to stop the operation. Hard CRC0n: Capture/ To ensure that the capture operation is performed properly, the capture trigger compare control requires a pulse two cycles longer than the count clock selected by prescaler register 0n mode register 0n (PRM0n). TOC0n: 16-bit Be sure to set TOC0n using the following procedure. timer output <1> Set TOC0n4 and TOC0n1 to 1. control register 0n <2> Set only TOE0n to 1. <3> Set either of LVS0n or LVR0n to 1. pp. 180, 181 p. 182 Soft PRM0n: Prescaler Do not apply the following setting when setting the PRM0n1 and PRM0n0 bits to p. 185 mode register 0n 11 (to specify the valid edge of the TI00n pin as a count clock). * Clear & start mode entered by the TI00n pin valid edge * Setting the TI00n pin as a capture trigger If the operation of the 16-bit timer/event counter 0n is enabled when the TI00n or p. 185 TI01n pin is at high level and when the valid edge of the TI00n or TI01n pin is specified to be the rising edge or both edges, the high level of the TI00n or TI01n pin is detected as a rising edge. Note this when the TI00n or TI01n pin is pulled up. However, the rising edge is not detected when the timer operation has been once stopped and then is enabled again. Hard The valid edge of TI010 and timer output (TO00) cannot be used for the P01 pin p. 185 at the same time, and the valid edge of TI011 and timer output (TO01) cannot be used for the P06 pin at the same time. Select either of the functions. Clear & start mode entered by TI00n pin valid edge input PPG output Do not set the count clock as the valid edge of the TI00n pin (PRM0n1 and PRM0n0 = 11). When PRM0n1 and PRM0n0 = 11, TM0n is cleared. p. 199 Soft To change the duty factor (value of CR01n) during operation, see 7.5.1 Rewriting p. 221 CR01n during TM0n operation. Set values to CR00n and CR01n such that the condition 0000H CR01n < CR00n FFFFH is satisfied. p. 222 One-shot pulse output Do not input the trigger again (setting OSPT0n to 1 or detecting the valid edge of p. 224 the TI00n pin) while the one-shot pulse is output. To output the one-shot pulse again, generate the trigger after the current one-shot pulse output has completed. To use only the setting of OSPT0n to 1 as the trigger of one-shot pulse output, do p. 224 not change the level of the TI00n pin or its alternate function port pin. Otherwise, the pulse will be unexpectedly output. Do not set the same value to CR0n0 and CR0n1. p. 226 p. 238 p. 239 p. 239 LVS0n, LVRn0 - Hard Be sure to set LVS0n and LVR0n following steps <1>, <2>, and <3> above. Step <2> can be performed after <1> and before <3>. Table 7-5 shows the restrictions for each channel. Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because counting TM0n is started asynchronously to the count pulse. User's Manual U17397EJ4V0UD 711 APPENDIX D LIST OF CAUTIONS www..com (7/27) Classification Function Chapter Details of Function Cautions Page Chapter 7 Soft 16-bit timer/event counters 00, 01 CR00n, CR01n: 16-bit timer capture/compare registers 00n, 01n Set a value other than 0000H to CR00n and CR01n in clear & start mode entered upon a match between TM0n and CR00n (TM0n cannot count one pulse when it is used as an external event counter). When the valid edge is input to the TI00n/TI01n pin and the reverse phase of the TI00n pin is detected while CR00n/CR01n is read, CR01n performs a capture operation but the read value of CR00n/CR01n is not guaranteed. At this time, an interrupt signal (INTTM00n/INTTM01n) is generated when the valid edge of the TI00n/TI01n pin is detected (the interrupt signal is not generated when the reversephase edge of the TI00n pin is detected). When the count value is captured because the valid edge of the TI00n/TI01n pin was detected, read the value of CR00n/CR01n after INTTM00n/INTTM01n is generated. p. 239 p. 240 The values of CR00n and CR01n are not guaranteed after 16-bit timer/event counter p. 240 0n stops. ES0n0, ES0n1 Re-triggering one-shot pulse OVF0n Set the valid edge of the TI00n pin while the timer operation is stopped (TMC0n3 and TMC0n2 = 00). Set the valid edge by using ES0n0 and ES0n1. Make sure that the trigger is not generated while an active level is being output in the one-shot pulse output mode. Be sure to input the next trigger after the current active level is output. The OVF0n flag is set to 1 in the following case, as well as when TM0n overflows. Select the clear & start mode entered upon a match between TM0n and CR00n. Set CR00n to FFFFH. When TM0n matches CR00n and TM0n is cleared from FFFFH to 0000H Even if the OVF0n flag is cleared to 0 after TM0n overflows and before the next count clock is counted (before the value of TM0n becomes 0001H), it is set to 1 again and clearing is invalid. One-shot pulse output TI00n Hard TI00n, TI01n p. 240 p. 240 p. 241 p. 241 One-shot pulse output operates correctly in the free-running timer mode or the clear p. 241 & start mode entered by the TI00n pin valid edge. The one-shot pulse cannot be output in the clear & start mode entered upon a match between TM0n and CR00n. When the valid edge of TI00n is specified as the count clock, the capture register for p. 242 which TI00n is specified as a trigger does not operate correctly. To accurately capture the count value, the pulse input to the TI00n and TI01n pins as a capture trigger must be wider than two count clocks selected by PRM0n (see Figure 7-9). p. 242 INTTM00n, INTTM01n Soft CRC0n1 = 1 The capture operation is performed at the falling edge of the count clock but the p. 242 interrupt signals (INTTM00n and INTTM01n) are generated at the rising edge of the next count clock (see Figure 7-9). When the count value of the TM0n register is captured to the CR00n register in the p. 242 phase reverse to the signal input to the TI00n pin, the interrupt signal (INTTM00n) is not generated after the count value is captured. If the valid edge is detected on the TI01n pin during this operation, the capture operation is not performed but the INTTM00n signal is generated as an external interrupt signal. Mask the INTTM00n signal when the external interrupt is not used. Hard Specifying valid If the operation of the 16-bit timer/event counter 0n is enabled after reset and while p. 242 edge after reset the TI00n or TI01n pin is at high level and when the rising edge or both the edges are specified as the valid edge of the TI00n or TI01n pin, then the high level of the TI00n or TI01n pin is detected as the rising edge. Note this when the TI00n or TI01n pin is pulled up. However, the rising edge is not detected when the operation is once stopped and then enabled again. Sampling clock for eliminating noise The sampling clock for eliminating noise differs depending on whether the valid edge p. 242 of TI00n is used as the count clock or capture trigger. In the former case, the sampling clock is fixed to fPRS. In the latter, the count clock selected by PRM0n is used for sampling. When the signal input to the TI00n pin is sampled and the valid level is detected two times in a row, the valid edge is detected. Therefore, noise having a short pulse width can be eliminated (see Figure 7-9). 712 User's Manual U17397EJ4V0UD APPENDIX D LIST OF CAUTIONS www..com (8/27) Hard Classification Function Details of Function Cautions Page Chapter Chapter 8 TI00n/TI01n 16-bit timer/event counters 00, 01 8-bit CR5n: 8-bit timer timer/event compare register 5n counters 50, 51 The signal input to the TI00n/TI01n pin is not acknowledged while the timer is stopped, regardless of the operation mode of the CPU. p. 242 Soft In the mode in which clear & start occurs on a match of TM5n and CR5n (TMC5n6 = 0), do not write other values to CR5n during operation. In PWM mode, make the CR5n rewrite period 3 count clocks of the count clock (clock selected by TCL5n) or more. p. 245 p. 245 p. 246 p. 246 p. 247 p. 247 p. 249 p. 249 TCL50: Timer clock When rewriting TCL50 to other data, stop the timer operation beforehand. selection register 50 Be sure to clear bits 3 to 7 to "0". TCL51: Timer clock When rewriting TCL51 to other data, stop the timer operation beforehand. selection register 51 Be sure to clear bits 3 to 7 to "0". TMC5n: 8-bit timer The settings of LVS5n and LVR5n are valid in other than PWM mode. mode control Perform <1> to <4> below in the following order, not at the same time. register 51 (TMC51) <1> Set TMC5n1, TMC5n6: Operation mode setting <2> Set TOE5n to enable output: Timer output enable <3> Set LVS5n, LVR5n (see Caution 1): Timer F/F setting <4> Set TCE5n When TCE5n = 1, setting the other bits of TMC5n is prohibited. Interval timer PWM output Do not write other values to CR5n during operation. In PWM mode, make the CR5n rewrite period 3 count clocks of the count clock (clock selected by TCL5n) or more. When reading from CR5n between <1> and <2> in Figure 8-15, the value read differs from the actual value (read value: M, actual value of CR5n: N). Timer start error An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 8-bit timer counters 50 and 51 (TM50, TM51) are started asynchronously to the count clock. Square-wave output Do not write other values to CR5n during operation. p. 249 p. 251 p. 254 p. 255 p. 258 p. 259 Chapter 9 Soft 8-bit timers CMP0n: 8-bit timer CMP0n cannot be rewritten during timer count operation. CMP0n can be H0, H1 H comparer register refreshed (the same value is written) during timer count operation. 0n (CMP0n) CMP1n: 8-bit timer In the PWM output mode and carrier generator mode, be sure to set CMP1n H compare register when starting the timer count operation (TMHEn = 1) after the timer count 1n (CMP1n) operation was stopped (TMHEn = 0) (be sure to set again even if setting the same value to CMP1n). TMHMD0: 8-bit timer H mode register 0 When TMHE0 = 1, setting the other bits of TMHMD0 is prohibited. However, TMHMD0 can be refreshed (the same value is written). In the PWM output mode, be sure to set the 8-bit timer H compare register 10 (CMP10) when starting the timer count operation (TMHE0 = 1) after the timer count operation was stopped (TMHE0 = 0) (be sure to set again even if setting the same value to CMP10). When TMHE1 = 1, setting the other bits of TMHMD1 is prohibited. However, TMHMD1 can be refreshed (the same value is written). In the PWM output mode and carrier generator mode, be sure to set the 8-bit timer H compare register 11 (CMP11) when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to CMP11). When the carrier generator mode is used, set so that the count clock frequency of TMH1 becomes more than 6 times the count clock frequency of TM51. TMCYC1: 8-bit timer H carrier register 1 Do not rewrite RMC1 when TMHE = 1. However, TMCYC1 can be refreshed (the same value is written). p. 263 p. 263 p. 266 p. 266 TMHMD1: 8-bit timer H mode register 1 p. 267 p. 267 p. 267 p. 268 User's Manual U17397EJ4V0UD 713 APPENDIX D LIST OF CAUTIONS www..com (9/27) Classification Function Chapter Details of Function Cautions Page Chapter 9 Hard 8-bit PWM output timers H0, H1 The set value of the CMP1n register can be changed while the timer counter is operating. However, this takes a duration of three operating clocks (signal selected by the CKSn2 to CKSn0 bits of the TMHMDn register) from when the value of the CMP1n register is changed until the value is transferred to the register. p. 273 Soft Be sure to set the CMP1n register when starting the timer count operation (TMHEn = p. 273 1) after the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the same value to the CMP1n register). Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N) are within the following range. 00H CMP1n (M) < CMP0n (N) FFH Carrier Do not rewrite the NRZB1 bit again until at least the second clock after it has been generator (8-bit rewritten, or else the transfer from the NRZB1 bit to the NRZ1 bit is not guaranteed. timer H1 only) When the 8-bit timer/event counter 51 is used in the carrier generator mode, an interrupt is generated at the timing of <1>. When the 8-bit timer/event counter 51 is used in a mode other than the carrier generator mode, the timing of the interrupt generation differs. p. 273 p. 279 p. 279 Be sure to set the CMP11 register when starting the timer count operation (TMHE1 = p. 281 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to the CMP11 register). Set so that the count clock frequency of TMH1 becomes more than 6 times the count p. 281 clock frequency of TM51. Set the values of the CMP01 and CMP11 registers in a range of 01H to FFH. p. 281 p. 281 The set value of the CMP11 register can be changed while the timer counter is operating. However, it takes the duration of three operating clocks (signal selected by the CKS12 to CKS10 bits of the TMHMD1 register) since the value of the CMP11 register has been changed until the value is transferred to the register. Be sure to set the RMC1 bit before the count operation is started. Chapter 10 Soft Watch timer WTM: Watch Do not change the count clock and interval time (by setting bits 4 to 7 (WTM4 to timer operation WTM7) of WTM) during watch timer operation. mode register Interrupt request p. 281 p. 288 Hard When operation of the watch timer and 5-bit counter is enabled by the watch timer p. 290 mode control register (WTM) (by setting bits 0 (WTM0) and 1 (WTM1) of WTM to 1), the interval until the first interrupt request signal (INTWT) is generated after the register is set does not exactly match the specification made with bits 2 and 3 (WTM2, WTM3) of WTM. Subsequently, however, the INTWT signal is generated at the specified intervals. Chapter 11 Soft Watchdog WDTE: If a value other than ACH is written to WDTE, an internal reset signal is generated. If p. 293 timer Watchdog timer the source clock to the watchdog timer is stopped, however, an internal reset signal enable register is generated when the source clock to the watchdog timer resumes operation. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset signal is generated. If the source clock to the watchdog timer is stopped, however, an internal reset signal is generated when the source clock to the watchdog timer resumes operation. The value read from WDTE is 9AH/1AH (this differs from the written value (ACH)). Operation control p. 293 p. 293 The first writing to WDTE after a reset release clears the watchdog timer, if it is made p. 294 before the overflow time regardless of the timing of the writing, and the watchdog timer starts counting again. If the watchdog timer is cleared by writing "ACH" to WDTE, the actual overflow time p. 294 may be different from the overflow time set by the option byte by up to 2/fRL seconds. The watchdog timer can be cleared immediately before the count value overflows (FFFFH). p. 294 714 User's Manual U17397EJ4V0UD APPENDIX D LIST OF CAUTIONS www..com (10/27) Soft Classification Function Chapter Details of Function Cautions Page Chapter 11 Watchdog timer Operation control p. 295 The operation of the watchdog timer in the HALT and STOP modes differs as follows depending on the set value of bit 0 (LSROSC) of the option byte (see Table on p. 295). If LSROSC = 0, the watchdog timer resumes counting after the HALT or STOP mode is released. At this time, the counter is not cleared to 0 but starts counting from the value at which it was stopped. If oscillation of the internal low-speed oscillator is stopped by setting LSRSTOP (bit 1 of the internal oscillation mode register (RCM) = 1) when LSROSC = 0, the watchdog timer stops operating. At this time, the counter is not cleared to 0. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0 is prohibited. pp. 295, 296 Setting overflow time of watchdog timer, Setting window open period of watchdog time Setting window open period of watchdog timer Chapter 13 Chapter 12 Soft Clock output/ CKS: clock buzzer output output select controller register A/D converter ADCR: 10-bit A/D conversion register, ADCRH: 8-bit A/D conversion register pp. 295, The watchdog timer continues its operation during self-programming and 296 EEPROM emulation of the flash memory. During processing, the interrupt acknowledge time is delayed. Set the overflow time and window size taking this delay into consideration. The first writing to WDTE after a reset release clears the watchdog timer, if it is made before the overflow time regardless of the timing of the writing, and the watchdog timer starts counting again. Set BCS1 and BCS0 when the buzzer output operation is stopped (BZOE = 0). Set CCS3 to CCS0 while the clock output operation is stopped (CLOE = 0). p. 296 p. 300 p. 300 Soft When data is read from ADCR and ADCRH, a wait cycle is generated. Do not p. 304 read data from ADCR and ADCRH when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 34 CAUTIONS FOR WAIT. ADM: A/D A/D conversion must be stopped before rewriting bits FR0 to FR2, LV1, and p. 306 converter mode LV0 to values other than the identical data. register If data is written to ADM, a wait cycle is generated. Do not write data to ADM p. 306 when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 34 CAUTIONS FOR WAIT. A/D conversion timer selection Set the conversion times with the following conditions. * 4.0 V AVREF 5.5 V: fAD = 0.6 to 3.6 MHz * 2.7 V AVREF < 4.0 V: fAD = 0.6 to 1.8 MHz * 2.3 V AVREF < 2.7 V: fAD = 0.6 to 1.48 MHz When rewriting FR2 to FR0, LV1, and LV0 to other than the same data, stop A/D conversion once (ADCS = 0) beforehand. Change LV1 and LV0 from the default value, when 2.3 V AVREF < 2.7 V. The above conversion time does not include clock frequency errors. Select conversion time, taking clock frequency errors into consideration. ADCR: 10-bit A/D conversion register p. 307 p. 307 p. 307 p. 307 p. 308 When writing to the A/D converter mode register (ADM), analog input channel specification register (ADS), and A/D port configuration register (ADPC), the contents of ADCR may become undefined. Read the conversion result following conversion completion before writing to ADM, ADS, and ADPC. Using timing other than the above may cause an incorrect conversion result to be read. If data is read from ADCR, a wait cycle is generated. Do not read data from ADCR when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 34 CAUTIONS FOR WAIT. p. 308 User's Manual U17397EJ4V0UD 715 APPENDIX D LIST OF CAUTIONS www..com (11/27) Soft Classification Function Chapter Details of Function Cautions Page Chapter 13 A/D converter ADCRH: 8-bit A/D conversion register p. 309 When writing to the A/D converter mode register (ADM), analog input channel specification register (ADS), and A/D port configuration register (ADPC), the contents of ADCRH may become undefined. Read the conversion result following conversion completion before writing to ADM, ADS, and ADPC. Using timing other than the above may cause an incorrect conversion result to be read. If data is read from ADCRH, a wait cycle is generated. Do not read data from ADCRH when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 34 CAUTIONS FOR WAIT. p. 309 ADS: Analog input channel specification register ADS: Analog input channel specification register, ADPC: A/D port configuration register (ADPC) ADPC: A/D port configuration register (ADPC) Be sure to clear bits 3 to 7 to "0". p. 310 If data is written to ADS, a wait cycle is generated. Do not write data to ADS when p. 310 the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 34 CAUTIONS FOR WAIT. Set a channel to be used for A/D conversion in the input mode by using port mode pp. 310, register 2 (PM2). 311 If data is written to ADPC, a wait cycle is generated. Do not write data to ADPC when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 34 CAUTIONS FOR WAIT. p. 311 Basic operations Make sure the period of <1> to <5> is 1 s or more. of A/D converter A/D conversion operation Make sure the period of <1> to <5> is 1 s or more. <1> may be done between <2> and <4>. p. 313 p. 317 p. 317 <1> can be omitted. However, ignore data of the first conversion after <5> in this p. 317 case. The period from <6> to <9> differs from the conversion time set using bits 5 to 1 (FR2 to FR0, LV1, LV0) of ADM. The period from <8> to <9> is the conversion time set using FR2 to FR0, LV1, and LV0. p. 317 Operating current The A/D converter stops operating in the STOP mode. At this time, the operating p. 320 in STOP mode current can be reduced by clearing bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0. To restart from the standby status, clear bit 0 (ADIF) of interrupt request flag register 1L (IF1L) to 0 and start operation. Hard Input range of ANI0 to ANI7 Observe the rated range of the ANI0 to ANI7 input voltage. If a voltage of AVREF or higher and AVSS or lower (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. In addition, the converted values of the other channels may also be affected. If conflict occurs between A/D conversion result register (ADCR, ADCRH) write and ADCR or ADCRH read by instruction upon the end of conversion, ADCR or ADCRH read has priority. After the read operation, the new conversion result is written to ADCR or ADCRH. If conflict occurs between ADCR or ADCRH write and A/D converter mode register (ADM) write, analog input channel specification register (ADS), or A/D port configuration register (ADPC) write upon the end of conversion, ADM, ADS, or ADPC write has priority. ADCR or ADCRH write is not performed, nor is the conversion end interrupt signal (INTAD) generated. p. 320 Soft Conflicting operations p. 320 p. 320 716 User's Manual U17397EJ4V0UD APPENDIX D LIST OF CAUTIONS www..com (12/27) Hard Classification Function Chapter Details of Function Cautions Page Chapter 13 p. 320 A/D Noise To maintain the 10-bit resolution, attention must be paid to noise input to the converter countermeasures AVREF pin and pins ANI0 to ANI7. * Connect a capacitor with a low equivalent resistance and a good frequency response to the power supply. * The higher the output impedance of the analog input source, the greater the influence. To reduce the noise, connecting external C as shown in Figure 1320 is recommended. * Do not switch these pins with other pins during conversion. * The accuracy is improved if the HALT mode is set immediately after the start of conversion. ANI0/P20 to ANI7/P27 The analog input pins (ANI0 to ANI7) are also used as input port pins (P20 to P27). When A/D conversion is performed with any of ANI0 to ANI7 selected, do not access P20 to P27 while conversion is in progress; otherwise the conversion resolution may be degraded. It is recommended to select pins used as P20 to P27 starting with the ANI0/P20 that is the furthest from AVREF. p. 321 If a digital pulse is applied to the pins adjacent to the pins currently used for A/D p. 321 conversion, the expected value of the A/D conversion may not be obtained due to coupling noise. Therefore, do not apply a pulse to the pins adjacent to the pin undergoing A/D conversion. p. 321 Input impedance This A/D converter charges a sampling capacitor for sampling during sampling of ANI0 to ANI7 time. pins Therefore, only a leakage current flows when sampling is not in progress, and a current that charges the capacitor flows during sampling. Consequently, the input impedance fluctuates depending on whether sampling is in progress, and on the other states. To make sure that sampling is effective, however, it is recommended to keep the output impedance of the analog input source to within 10 k, and to connect a capacitor of about 100 pF to the ANI0 to ANI7 pins (see Figure 13-20). AVREF pin input impedance A series resistor string of several tens of k is connected between the AVREF and p. 321 AVSS pins. Therefore, if the output impedance of the reference voltage source is high, this will result in a series connection to the series resistor string between the AVREF and AVSS pins, resulting in a large reference voltage error. Soft Interrupt request The interrupt request flag (ADIF) is not cleared even if the analog input channel p. 322 flag (ADIF) specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the prechange analog input may be set just before the ADS rewrite. Caution is therefore required since, at this time, when ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the post-change analog input has not ended. When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed. Conversion results just after A/D conversion start A/D conversion result register (ADCR, ADCRH) read operation The first A/D conversion value immediately after A/D conversion starts may not p. 322 fall within the rating range if the ADCS bit is set to 1 within 1 s after the ADCE bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit = 0. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first conversion result. When a write operation is performed to the A/D converter mode register (ADM), analog input channel specification register (ADS), and A/D port configuration register (ADPC), the contents of ADCR and ADCRH may become undefined. Read the conversion result following conversion completion before writing to ADM, ADS, and ADPC. Using a timing other than the above may cause an incorrect conversion result to be read. p. 322 User's Manual U17397EJ4V0UD 717 APPENDIX D LIST OF CAUTIONS www..com (13/27) Soft Classification Function Chapter Details of Function Cautions Page Chapter 14 Serial interface UART0 UART mode If clock supply to serial interface UART0 is not stopped (e.g., in the HALT mode), normal operation continues. If clock supply to serial interface UART0 is stopped (e.g., in the STOP mode), each register stops operating, and holds the value immediately before clock supply was stopped. The TXD0 pin also holds the value immediately before clock supply was stopped and outputs it. However, the operation is not guaranteed after clock supply is resumed. Therefore, reset the circuit so that POWER0 = 0, RXE0 = 0, and TXE0 = 0. Set POWER0 = 1 and then set TXE0 = 1 (transmission) or RXE0 = 1 (reception) to start communication. TXE0 and RXE0 are synchronized by the base clock (fXCLK0) set by BRGC0. To enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base clock, the transmission circuit or reception circuit may not be initialized. Set transmit data to TXS0 at least one base clock (fXCLK0) after setting TXE0 = 1. p. 324 p. 324 p. 324 pp. 324 327 p. 327 p. 329 p. 329 TXS0: Transmit Do not write the next transmit data to TXS0 before the transmission completion shift register 0 interrupt signal (INTST0) is generated. ASIM0: Asynchronous serial interface operation mode register 0 To start the transmission, set POWER0 to 1 and then set TXE0 to 1. To stop the transmission, clear TXE0 to 0, and then clear POWER0 to 0. To start the reception, set POWER0 to 1 and then set RXE0 to 1. To stop the reception, clear RXE0 to 0, and then clear POWER0 to 0. Set POWER0 to 1 and then set RXE0 to 1 while a high level is input to the RxD0 p. 329 pin. If POWER0 is set to 1 and RXE0 is set to 1 while a low level is input, reception is started. TXE0 and RXE0 are synchronized by the base clock (fXCLK0) set by BRGC0. To enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base clock, the transmission circuit or reception circuit may not be initialized. Set transmit data to TXS0 at least one base clock (fXCLK0) after setting TXE0 = 1. Clear the TXE0 and RXE0 bits to 0 before rewriting the PS01, PS00, and CL0 bits. Make sure that TXE0 = 0 when rewriting the SL0 bit. Reception is always performed with "number of stop bits = 1", and therefore, is not affected by the set value of the SL0 bit. Be sure to set bit 0 to 1. p. 329 p. 329 p. 329 p. 329 p. 329 p. 330 p. 330 p. 330 ASIS0: Asynchronous serial interface reception error status register 0 The operation of the PE0 bit differs depending on the set values of the PS01 and PS00 bits of asynchronous serial interface operation mode register 0 (ASIM0) Only the first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. If an overrun error occurs, the next receive data is not written to receive buffer register 0 (RXB0) but discarded. If data is read from ASIS0, a wait cycle is generated. Do not read data from ASIS0 p. 330 when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 34 CAUTIONS FOR WAIT. BRGC0: Baud Make sure that bit 6 (TXE0) and bit 5 (RXE0) of the ASIM0 register = 0 when rate generator rewriting the MDL04 to MDL00 bits. control register 0 The baud rate value is the output clock of the 5-bit counter divided by 2. POWER0, TXE0, RXE0: Bits 7, 6, 5 of ASIM0 UART mode Clear POWER0 to 0 after clearing TXE0 and RXE0 to 0 to set the operation stop mode. To start the communication, set POWER0 to 1, and then set TXE0 or RXE0 to 1. p. 332 p. 332 p. 333 Soft Hard Take relationship with the other party of communication when setting the port mode p. 334 register and port register. 718 User's Manual U17397EJ4V0UD APPENDIX D LIST OF CAUTIONS www..com (14/27) Soft Classification Function Chapter Details of Function Cautions Page Chapter 14 Serial interface UART0 UART transmission After transmit data is written to TXS0, do not write the next transmit data before the p. 337 transmission completion interrupt signal (INTST0) is generated. UART reception If a reception error occurs, read asynchronous serial interface reception error status p. 338 register 0 (ASIS0) and then read receive buffer register 0 (RXB0) to clear the error flag. Otherwise, an overrun error will occur when the next data is received, and the reception error status will persist UART reception Reception is always performed with the "number of stop bits = 1". The second stop p. 338 bit is ignored. Error of baud rate Keep the baud rate error during transmission to within the permissible error range at p. 341 the reception destination. Make sure that the baud rate error during reception satisfies the range shown in (4) p. 341 Permissible baud rate range during reception. Permissible Make sure that the baud rate error during reception is within the permissible error baud rate range range, by using the calculation expression shown below. during reception p. 343 Chapter 15 Soft Serial interface UART6 UART mode The TXD6 output inversion function inverts only the transmission side and not the p. 345 reception side. To use this function, the reception side must be ready for reception of inverted data. If clock supply to serial interface UART6 is not stopped (e.g., in the HALT mode), normal operation continues. If clock supply to serial interface UART6 is stopped (e.g., in the STOP mode), each register stops operating, and holds the value immediately before clock supply was stopped. The TXD6 pin also holds the value immediately before clock supply was stopped and outputs it. However, the operation is not guaranteed after clock supply is resumed. Therefore, reset the circuit so that POWER6 = 0, RXE6 = 0, and TXE6 = 0. Set POWER6 = 1 and then set TXE6 = 1 (transmission) or RXE6 = 1 (reception) to start communication. TXE6 and RXE6 are synchronized by the base clock (fXCLK6) set by CKSR6. To enable transmission or reception again, set TXE6 or RXE6 to 1 at least two clocks of the base clock after TXE6 or RXE6 has been cleared to 0. If TXE6 or RXE6 is set within two clocks of the base clock, the transmission circuit or reception circuit may not be initialized. Set transmit data to TXB6 at least one base clock (fXCLK6) after setting TXE6 = 1. p. 345 p. 345 p. 345 p. 345 If data is continuously transmitted, the communication timing from the stop bit to the p. 345 next start bit is extended two operating clocks of the macro. However, this does not affect the result of communication because the reception side initializes the timing when it has detected a start bit. Do not use the continuous transmission function if the interface is used in LIN communication operation. TXB6: Transmit Do not write data to TXB6 when bit 1 (TXBF6) of asynchronous serial interface buffer register 6 transmission status register 6 (ASIF6) is 1. p. 351 Do not refresh (write the same value to) TXB6 by software during a communication p. 351 operation (when bits 7 and 6 (POWER6, TXE6) of asynchronous serial interface operation mode register 6 (ASIM6) are 1 or when bits 7 and 5 (POWER6, RXE6) of ASIM6 are 1). Set transmit data to TXB6 at least one base clock (fXCLK6) after setting TXE6 = 1. ASIM6: Asynchronous serial interface operation mode register 6 To start the transmission, set POWER6 to 1 and then set TXE6 to 1. To stop the transmission, clear TXE6 to 0, and then clear POWER6 to 0. To start the reception, set POWER6 to 1 and then set RXE6 to 1. To stop the reception, clear RXE6 to 0, and then clear POWER6 to 0. p. 351 p. 353 p. 353 Set POWER6 to 1 and then set RXE6 to 1 while a high level is input to the RXD6 p. 353 pin. If POWER6 is set to 1 and RXE6 is set to 1 while a low level is input, reception is started. User's Manual U17397EJ4V0UD 719 APPENDIX D LIST OF CAUTIONS www..com (15/27) Soft Classification Function Chapter Details of Function Cautions Page Chapter 15 Serial interface UART6 ASIM6: Asynchronous serial interface operation mode register 6 TXE6 and RXE6 are synchronized by the base clock (fXCLK6) set by CKSR6. To enable transmission or reception again, set TXE6 or RXE6 to 1 at least two clocks of the base clock after TXE6 or RXE6 has been cleared to 0. If TXE6 or RXE6 is set within two clocks of the base clock, the transmission circuit or reception circuit may not be initialized. Set transmit data to TXB6 at least one base clock (fXCLK6) after setting TXE6 = 1. Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits. Fix the PS61 and PS60 bits to 0 when used in LIN communication operation. Clear TXE6 to 0 before rewriting the SL6 bit. Reception is always performed with "the number of stop bits = 1", and therefore, is not affected by the set value of the SL6 bit. Make sure that RXE6 = 0 when rewriting the ISRM6 bit. p. 353 p. 353 p. 353 p. 353 p. 353 p. 353 p. 354 p. 354 p. 354 ASIS6: Asynchronous serial interface reception error status register 6 The operation of the PE6 bit differs depending on the set values of the PS61 and PS60 bits of asynchronous serial interface operation mode register 6 (ASIM6). For the stop bit of the receive data, only the first bit is checked regardless of the number of stop bits. If an overrun error occurs, the next receive data is not written to receive buffer register 6 (RXB6) but discarded. If data is read from ASIS6, a wait cycle is generated. Do not read data from ASIS6 p. 354 when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 34 CAUTIONS FOR WAIT. ASIF6: Asynchronous serial interface transmission status register 6 p. 355 To transmit data continuously, write the first transmit data (first byte) to the TXB6 register. Be sure to check that the TXBF6 flag is "0". If so, write the next transmit data (second byte) to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is "1", the transmit data cannot be guaranteed. To initialize the transmission unit upon completion of continuous transmission, be p. 355 sure to check that the TXSF6 flag is "0" after generation of the transmission completion interrupt, and then execute initialization. If initialization is executed while the TXSF6 flag is "1", the transmit data cannot be guaranteed. Make sure POWER6 = 0 when rewriting TPS63 to TPS60. p. 356 CKSR6: Clock selection register 6 Soft Hard BRGC6: Baud Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when rate generator rewriting the MDL67 to MDL60 bits. control register 6 The baud rate is the output clock of the 8-bit counter divided by 2. ASICL6: Asynchronous serial interface control register 6 p. 357 p. 357 p. 358 ASICL6 can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (POWER6, TXE6) of ASIM6 = 1 or bits 7 and 5 (POWER6, RXE6) of ASIM6 = 1). However, do not set both SBRT6 and SBTT6 to 1 by a refresh operation during SBF reception (SBRT6 = 1) or SBF transmission (until INTST6 occurs since SBTT6 has been set (1)), because it may re-trigger SBF reception or SBF transmission. In the case of an SBF reception error, the mode returns to the SBF reception mode. p. 359 The status of the SBRF6 flag is held (1). Before setting the SBRT6 bit, make sure that bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1. After setting the SBRT6 bit to 1, do not clear it to 0 before SBF reception is completed (before an interrupt request signal is generated). The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to 0 after SBF reception has been correctly completed. p. 359 p. 359 Before setting the SBTT6 bit to 1, make sure that bit 7 (POWER6) and bit 6 (TXE6) p. 359 of ASIM6 = 1. After setting the SBTT6 bit to 1, do not clear it to 0 before SBF transmission is completed (before an interrupt request signal is generated). The read value of the SBTT6 bit is always 0. SBTT6 is automatically cleared to 0 at p. 359 the end of SBF transmission 720 User's Manual U17397EJ4V0UD APPENDIX D LIST OF CAUTIONS www..com (16/27) Soft Classification Function Details of Function Cautions Page Chapter Chapter 15 Serial ASICL6: interface Asynchronous serial UART6 interface control register 6 POWER6, TXE6, RXE6: Bits 7, 6, 5 of ASIM6 UART mode Parity types and operation Continuous transmission Do not set the SBRT6 bit to 1 during reception, and do not set the SBTT6 bit to p. 359 1 during transmission. Before rewriting the DIR6 and TXDLV6 bits, clear the TXE6 and RXE6 bits to 0. p. 359 Clear POWER6 to 0 after clearing TXE6 and RXE6 to 0 to stop the operation. To start the communication, set POWER6 to 1, and then set TXE6 or RXE6 to 1. Take relationship with the other party of communication when setting the port mode register and port register. p. 361 p. 362 Fix the PS61 and PS60 bits to 0 when the device is used in LIN communication p. 365 operation. p. 367 The TXBF6 and TXSF6 flags of the ASIF6 register change from "10" to "11", and to "01" during continuous transmission. To check the status, therefore, do not use a combination of the TXBF6 and TXSF6 flags for judgment. Read only the TXBF6 flag when executing continuous transmission. When the device is use in LIN communication operation, the continuous transmission function cannot be used. Make sure that asynchronous serial interface transmission status register 6 (ASIF6) is 00H before writing transmit data to transmit buffer register 6 (TXB6). p. 367 p. 367 To transmit data continuously, write the first transmit data (first byte) to the TXB6 register. Be sure to check that the TXBF6 flag is "0". If so, write the next transmit data (second byte) to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is "1", the transmit data cannot be guaranteed. To initialize the transmission unit upon completion of continuous transmission, be sure to check that the TXSF6 flag is "0" after generation of the transmission completion interrupt, and then execute initialization. If initialization is executed while the TXSF6 flag is "1", the transmit data cannot be guaranteed. During continuous transmission, the next transmission may complete before execution of INTST6 interrupt servicing after transmission of one data frame. As a countermeasure, detection can be performed by developing a program that can count the number of transmit data and by referencing the TXSF6 flag. Normal reception If a reception error occurs, read ASIS6 and then RXB6 to clear the error flag. Otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. Reception is always performed with the "number of stop bits = 1". The second stop bit is ignored. Be sure to read asynchronous serial interface reception error status register 6 (ASIS6) before reading RXB6. Error of baud rate Keep the baud rate error during transmission to within the permissible error range at the reception destination. p. 367 p. 367 p. 371 p. 371 p. 371 p. 377 Make sure that the baud rate error during reception satisfies the range shown in p. 377 (4) Permissible baud rate range during reception. Permissible baud rate Make sure that the baud rate error during reception is within the permissible range during reception error range, by using the calculation expression shown below. Chapter 16 Soft Serial SOTB1n: Transmit interface buffer register 1n CSI10, CSI11 Do not access SOTB1n when CSOT1n = 1 (during serial communication). In the slave mode, transmission/reception is started when data is written to SOTB11 with a low level input to the SSI11 pin. For details on the transmission/reception operation, see 16.4.2 (2) Communication operation. p. 379 p. 384 p. 384 SIO1n: Serial I/O shift Do not access SIO1n when CSOT1n = 1 (during serial communication). p. 384 register 1n In the slave mode, reception is started when data is read from SIO11 with a low p. 384 level input to the SSI11 pin. For details on the reception operation, see 16.4.2 (2) Communication operation. User's Manual U17397EJ4V0UD 721 APPENDIX D LIST OF CAUTIONS www..com (17/27) Classification Function Details of Function Cautions Page Chapter Chapter 16 Soft Serial interface CSI10, CSI11 CSIM10: Serial operation mode register 10 CSIC10: Serial clock selection register 10 Be sure to clear bit 5 to 0. p. 385 Do not write to CSIC10 while CSIE10 = 1 (operation enabled). p. 387 To use P10/SCK10/TXD0 and P12/SO10 as general-purpose ports, set CSIC10 p. 387 in the default status (00H). The phase type of the data clock is type 1 after reset. p. 387 p. 388 Do not write to CSIC11 while CSIE11 = 1 (operation enabled). CSIC11: Serial clock selection register 11 To use P02/SO11 and P04/SCK11 as general-purpose ports, set CSIC11 in the p. 388 default status (00H). The phase type of the data clock is type 1 after reset. p. 388 p. 391 p. 394 p. 394 3-wire serial I/O mode Take relationship with the other party of communication when setting the port mode register and port register. Communication operation Do not access the control register and data register when CSOT1n = 1 (during serial communication). When using serial interface CSI11, wait for the duration of at least one clock before the clock operation is started to change the level of the SSI11 pin in the slave mode; otherwise, malfunctioning may occur. SO1n output Chapter 17 Soft If a value is written to TRMD1n, DAP1n, and DIR1n, the output value of SO1n changes. p. 402 Serial SIOA0: Serial I/O shift A communication operation is started by writing to SIOA0. Consequently, when p. 406 interface register 0 transmission is disabled (bit 3 (TXEA0) of CSIMA0 = 0), write dummy data to CSIA0 the SIOA0 register to start the communication operation, and then perform a receive operation. Do not write data to SIOA0 while the automatic transmit/receive function is operating. CSIMA0: When CSIAE0 = 0, the buffer RAM cannot be accessed. Serial operation mode When CSIAE0 is changed from 1 to 0, the registers and bits mentioned in Note specification register 0 above are asynchronously initialized. To set CSIAE0 = 1 again, be sure to reset the initialized registers. When CSIAE0 is re-set to 1 after CSIAE0 is changed from 1 to 0, it is not guaranteed that the value of the buffer RAM will be retained. CSIS0: Serial status register 0 Be sure to clear bit 7 to 0. p. 406 p. 407 p. 407 p. 407 p. 408 During transfer (TSF0 = 1), rewriting serial operation mode specification register p. 409 0 (CSIMA0), serial status register 0 (CSIS0), divisor selection register 0 (BRGCA0), automatic data transfer address point specification register 0 (ADTP0), automatic data transfer interval specification register 0 (ADTI0), and serial I/O shift register 0 (SIOA0) are prohibited. However, these registers can be read and re-written to the same value. In addition, the buffer RAM can be rewritten during transfer. Even if ATSTP0 or ATSTA0 is set to 1, automatic transfer cannot be started/stopped until 1-byte transfer is complete. ATSTP0 and ATSTA0 change to 0 automatically after the interrupt signal INTACSI is generated. After automatic data transfer is stopped, the data address when the transfer stopped is stored in automatic data transfer address count register 0 (ADTC0). However, since no function to restart automatic data transfer is incorporated, when transfer is stopped by setting ATSTP0 = 1, start automatic data transfer by setting ATSTA0 to 1 after re-setting the registers. p. 410 p. 410 p. 410 CSIT0: Serial trigger register 0 BRGCA0: Divisor selection register 0 Set the transfer clock so as to satisfy the following conditions. * When 4.0 V VDD 5.5 V: 1.67 MHz or lower * When 2.7 V VDD < 4.0 V: 833.33 kHz or lower p. 411 722 User's Manual U17397EJ4V0UD APPENDIX D LIST OF CAUTIONS www..com (18/27) Soft Classification Function Details of Function Cautions Page Chapter Chapter 17 Serial interface CSIA0 Be sure to clear bits 7 to 5 to "0". ADTP0: Automatic data transfer address point specification register 0 p. 412 Because the setting of bit 5 (STBE0) and bit 4 (BUSYE0) of serial status register p. 413 ADTI0: Automatic data transfer interval 0 (CSIS0) takes priority over the ADTI0 setting, the interval time based on the specification register setting of STBE0 and BUSYE0 is generated even when ADTI0 is cleared to 00H. 0 3-wire serial I/O mode Take relationship with the other party of communication when setting the port mode register and port register. p. 416 p. 418 1-byte transmission/ The SOA0 pin becomes low level by an SIOA0 write. reception 3-wire serial I/O mode with automatic transmit/receive function Automatic transmission/ reception mode A wait state may be generated when data is written to the buffer RAM. For details, see CHAPTER 34 CAUTIONS FOR WAIT. Communication start If CSIAE0 is set to 1 after data is written to SIOA0, communication does not start. p. 420 p. 421 Take the relationship with the other communicating party into consideration when p. 423 setting the port mode register and port register. Because, in the automatic transmission/reception mode, the automatic transmit/receive function writes/reads data to/from the internal buffer RAM after 1-byte transmission/reception, an interval is inserted until the next transmission/reception. As the buffer RAM write/read is performed at the same time as CPU processing, the interval is dependent upon the value of automatic data transfer interval specification register 0 (ADTI0) and the set values of bits 5 and 4 (STBE0, BUSYE0) of serial status register 0 (CSIS0) (see (5) Automatic transmit/receive interval time). p. 425 If an access to the buffer RAM by the CPU conflicts with an access to the buffer p. 425 RAM by serial interface CSIA0 during the interval period, the interval time specified by automatic data transfer interval specification register 0 (ADTI0) may be extended. Automatic transmission Because, in the automatic transmission mode, the automatic transmit/receive function reads data from the internal buffer RAM after 1-byte transmission, an interval is inserted until the next transmission. As the buffer RAM read is performed at the same time as CPU processing, the interval is dependent upon the value of automatic data transfer interval specification register 0 (ADTI0) and the set values of bits 5 and 4 (STBE0, BUSYE0) of serial status register 0 (CSIS0) (see (5) Automatic transmit/receive interval time). p. 430 If an access to the buffer RAM by the CPU conflicts with an access to the buffer p. 430 RAM by serial interface CSIA0 during the interval period, the interval time specified by automatic data transfer interval specification register 0 (ADTI0) may be extended. p. 432 Repeat transmission Because, in the repeat transmission mode, a read is performed on the buffer RAM after the transmission of one byte, the interval is included in the period up mode to the next transmission. As the buffer RAM read is performed at the same time as CPU processing, the interval is dependent upon automatic data transfer interval specification register 0 (ADTI0) and the set values of bits 5 and 4 (STBE0, BUSYE0) of serial status register 0 (CSIS0) (see (5) Automatic transmit/receive interval time). If an access to the buffer RAM by the CPU conflicts with an access to the buffer p. 432 RAM by serial interface CSIA0 during the interval period, the interval time specified by automatic data transfer interval specification register 0 (ADTI0) may be extended. User's Manual U17397EJ4V0UD 723 APPENDIX D LIST OF CAUTIONS www..com (19/27) Soft Classification Function Details of Function Cautions Page Chapter Chapter 17 Serial interface CSIA0 Automatic transmission/ reception suspension and restart If the HALT instruction is executed during automatic transmission/reception, communication is suspended and the HALT mode is set if during 8-bit data communication. When the HALT mode is cleared, automatic transmission/reception is restarted from the suspended point. p. 435 When suspending automatic transmission/reception, do not change the operating p. 435 mode to 3-wire serial I/O mode while TSF0 = 1. Busy control option Busy control cannot be used simultaneously with the interval time control function of automatic data transfer interval specification register 0 (ADTI0). p. 436 p. 438 p. 444 p. 444 Busy & strobe control When TSF0 is cleared, the SOA0 pin goes low. option Chapter 18 Soft Serial interface IIC0 IIC0: IIC shift register Do not write data to IIC0 during data transfer. 0 Write or read IIC0 only during the wait period. Accessing IIC0 in a communication state other than during the wait period is prohibited. When the device serves as the master, however, IIC0 can be written only once after the communication trigger bit (STT0) is set to 1. IICC0: IIC control register 0 2 The start condition is detected immediately after I C is enabled to operate (IICE0 p. 448 = 1) while the SCL0 line is at high level and the SDA0 line is at low level. 2 Immediately after enabling I C to operate (IICE0 = 1), set LREL0 (1) by using a 1bit memory manipulation instruction. When bit 3 (TRC0) of IIC status register 0 (IICS0) is set to 1, WREL0 is set to 1 during the ninth clock and wait is canceled, after which TRC0 is cleared and the SDA0 line is set to high impedance. p. 451 IICS0: IIC status register 0 If data is read from IICS0, a wait cycle is generated. Do not read data from IICS0 when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 34 CAUTIONS FOR WAIT. Write to STCEN only when the operation is stopped (IICE0 = 0). p. 452 IICF0: IIC flag register 0 p. 455 As the bus release status (IICBSY = 0) is recognized regardless of the actual bus p. 455 status when STCEN = 1, when generating the first start condition (STT0 = 1), it is necessary to verify that no third party communications are in progress in order to prevent such communications from being destroyed. Write to IICRSV only when the operation is stopped (IICE0 = 0). p. 455 Determine the transfer clock frequency of I C by using CLX0, SMC0, CL01, and p. 458 CL00 before enabling the operation (by setting bit 7 (IICE0) of IIC control register 0 (IICC0) to 1). To change the transfer clock frequency, clear IICE0 once to 0. p. 475 Immediately after I C operation is enabled (IICE0 = 1), the bus communication status (IICBSY (bit 6 of IICF0) = 1) is recognized regardless of the actual bus status. When changing from a mode in which no stop condition has been detected to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication. When using multiple masters, it is not possible to perform master device communication when the bus has not been released (when a stop condition has not been detected). Use the following sequence for generating a stop condition. * Set IIC clock selection register 0 (IICCL0). * Set bit 7 (IICE0) of IIC control register 0 (IICC0) to 1. * Set bit 0 (SPT0) of IICC0 to 1. Immediately after I C operation is enabled (IICE0 = 1), the bus released status (IICBSY = 0) is recognized regardless of the actual bus status. To generate the first start condition (STT0 (bit 1 of IIC control register 0 (IICC0)) = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. 2 2 2 Selection clock setting When STCEN = 0 When STCEN = 1 p. 475 724 User's Manual U17397EJ4V0UD APPENDIX D LIST OF CAUTIONS www..com (20/27) Soft Classification Function Details of Function Cautions Page Chapter Chapter 18 Serial interface IIC0 If other I C If I C operation is enabled and the device participates in communication already p. 475 2 communications are in progress when the SDA0 pin is low and the SCL0 pin is high, the macro of I C already in progress recognizes that the SDA0 pin has gone low (detects a start condition). If the value on the bus at this time can be recognized as an extension code, ACK is 2 returned, but this interferes with other I C communications. To avoid this, start 2 I C in the following sequence. * Clear bit 4 (SPIE0) of IICC0 to 0 to disable generation of an interrupt request signal (INTIIC0) when the stop condition is detected. 2 * Set bit 7 (IICE0) of IICC0 to 1 to enable the operation of I C. * Wait for detection of the start condition. * Set bit 6 (LREL0) of IICC0 to 1 before ACK is returned (4 to 80 clocks after setting IICE0 to 1), to forcibly disable detection. Transfer clock frequency setting Determine the transfer clock frequency by using SMC0, CL01, CL00 (bits 3, 1, p. 475 and 0 of IICL0), and CLX0 (bit 0 of IICX0) before enabling the operation (IICE0 = 1). To change the transfer clock frequency, clear IICE0 to 0 once. p. 476 2 2 STT0, SPT0: Setting STT0 and SPT0 (bits 1 and 0 of IICC0) again after they are set and Bits 1, 0 of IIC control before they are cleared to 0 is prohibited. register 0 (IICC0) Transmission reserve When transmission is reserved, set SPIE0 (bit 4 of IICL0) to 1 so that an interrupt p. 476 request is generated when the stop condition is detected. Transfer is started when communication data is written to IIC0 after the interrupt request is generated. Unless the interrupt is generated when the stop condition is detected, the device stops in the wait state because the interrupt request is not generated when communication is started. However, it is not necessary to set SPIE0 to 1 when MSTS0 (bit 7 of IICS0) is detected by software Chapter 19 Soft Multiplier/ SDR0: Remainder divider data register 0 MDA0H, MDA0L: Multiplication/ division data register A0 The value read from SDR0 during operation processing (while bit 7 (DMUE) of multiplier/divider control register 0 (DMUC0) is 1) is not guaranteed. SDR0 is reset when the operation is started (when DMUE is set to 1). MDA0H is cleared to 0 when an operation is started in the multiplication mode (when multiplier/divider control register 0 (DMUC0) is set to 81H). Do not change the value of MDA0 during operation processing (while bit 7 (DMUE) of multiplier/divider control register 0 (DMUC0) is 1). Even in this case, the operation is executed, but the result is undefined. p. 514 p. 514 p. 514 p. 514 The value read from MDA0 during operation processing (while DMUE is 1) is not p. 514 guaranteed. MDB0: Multiplication/ Do not change the value of MDB0 during operation processing (while bit 7 division data register (DMUE) of multiplier/divider control register 0 (DMUC0) is 1). Even in this case, B0 the operation is executed, but the result is undefined. Do not clear MDB0 to 0000H in the division mode. If set, undefined operation results are stored in MDA0 and SDR0. DMUC0: Multiplier/divider control register 0 If DMUE is cleared to 0 during operation processing (when DMUE is 1), the operation result is not guaranteed. If the operation is completed while the clearing instruction is being executed, the operation result is guaranteed, provided that the interrupt flag is set. p. 515 p. 515 p. 516 Do not change the value of DMUSEL0 during operation processing (while DMUE p. 516 is 1). If it is changed, undefined operation results are stored in multiplication/division data register A0 (MDA0) and remainder data register 0 (SDR0). If DMUE is cleared to 0 during operation processing (while DMUE is 1), the operation processing is stopped. To execute the operation again, set multiplication/division data register A0 (MDA0), multiplication/division data register B0 (MDB0), and multiplier/divider control register 0 (DMUC0), and start the operation (by setting DMUE to 1). p. 516 User's Manual U17397EJ4V0UD 725 APPENDIX D LIST OF CAUTIONS www..com (21/27) Soft Classification Function Chapter Details of Function Cautions Page Chapter 20 Interrupt function 1F0L, 1F0L, 1F1L, 1F1H: Interrupt request flag registers Be sure to clear bits 5 to 7 of IF1H to 0. When operating a timer, serial interface, or A/D converter after standby release, operate it once after clearing the interrupt request flag. An interrupt request flag may be set by noise. p. 528 p. 528 When manipulating a flag of the interrupt request flag register, use a 1-bit memory p. 529 manipulation instruction (CLR1). When describing in C language, use a bit manipulation instruction such as "IF0L.0 = 0;" or "_asm("clr1 IF0L, 0");" because the compiled assembler must be a 1-bit memory manipulation instruction (CLR1). If a program is described in C language using an 8-bit memory manipulation instruction such as "IF0L &= 0xfe;" and compiled, it becomes the assembler of three instructions. mov a, IF0L and a, #0FEH mov IF0L, a In this case, even if the request flag of another bit of the same interrupt request flag register (IF0L) is set to 1 at the timing between "mov a, IF0L" and "mov IF0L, a", the flag is cleared to 0 at "mov IF0L, a". Therefore, care must be exercised when using an 8-bit memory manipulation instruction in C language. MK0L, MK0H, MK1L, MK1H: Interrupt mask flag registers Be sure to set bits 5 to 7 of MK1H to 1. p. 530 Be sure to set bits 5 to 7 of PR1H to 1. PR0L, PR0H, PR1L, PR1H: Priority specification flag registers Select the port mode by clearing EGPn and EGNn to 0 because an edge may be EGP, EGN: External interrupt detected when the external interrupt function is switched to the port function. rising edge, falling edge enable registers Software Do not use the RETI instruction for restoring from the software interrupt. interrupt request BRK instruction p. 531 p. 532 p. 536 p. 540 The BRK instruction is not one of the above-listed interrupt request hold instructions. However, the software interrupt activated by executing the BRK instruction causes the IE flag to be cleared. Therefore, even if a maskable interrupt request is generated during execution of the BRK instruction, the interrupt request is not acknowledged. p. 542 p. 542 Chapter 21 Soft Key interrupt function KRM: Key return If any of the KRM0 to KRM7 bits used is set to 1, set bits 0 to 7 (PU70 to PU77) of mode register the corresponding pull-up resistor register 7 (PU7) to 1. If KRM is changed, the interrupt request flag may be set. Therefore, disable interrupts and then change the KRM register. Clear the interrupt request flag and enable interrupts. The bits not used in the key interrupt mode can be used as normal ports. p. 542 726 User's Manual U17397EJ4V0UD APPENDIX D LIST OF CAUTIONS www..com (22/27) Soft Classification Function Chapter Details of Function Cautions Page Chapter 22 Standby function Standby function The STOP mode can be used only when the CPU is operating on the main system p. 543 clock. The subsystem clock oscillation cannot be stopped. The HALT mode can be used when the CPU is operating on either the main system clock or the subsystem clock. When shifting to the STOP mode, be sure to stop the peripheral hardware operation p. 543 operating with main system clock before executing STOP instruction. The following sequence is recommended for operating current reduction of the A/D converter when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 to stop the A/D conversion operation, and then execute the STOP instruction. OSTC: Oscillation stabilization time counter status register After the above time has elapsed, the bits are set to 1 in order from MOST11 and remain 1 p. 543 p. 544 The oscillation stabilization time counter counts up to the oscillation stabilization time p. 544 set by OSTS. If the STOP mode is entered and then released while the internal high-speed oscillation clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts ("a" below). p. 544 p. 545 p. 545 Soft Hard OSTS: Oscillation stabilization time select register To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS before executing the STOP instruction. Do not change the value of the OSTS register during the X1 clock oscillation stabilization time. The oscillation stabilization time counter counts up to the oscillation stabilization time p. 545 set by OSTS. If the STOP mode is entered and then released while the internal high-speed oscillation clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. Soft Hard The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts ("a" below). STOP mode p. 545 Because the interrupt request signal is used to clear the standby mode, if there is an p. 550 interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. Thus, the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction and the system returns to the operating mode as soon as the wait time set using the oscillation stabilization time select register (OSTS) has elapsed. To use the peripheral hardware that stops operation in the STOP mode, and the p. 553 peripheral hardware for which the clock that stops oscillating in the STOP mode after the STOP mode is released, restart the peripheral hardware. Even if "internal low-speed oscillator can be stopped by software" is selected by the p. 553 option byte, the internal low-speed oscillation clock continues in the STOP mode in the status before the STOP mode is set. To stop the internal low-speed oscillator's oscillation in the STOP mode, stop it by software and then execute the STOP instruction To shorten oscillation stabilization time after the STOP mode is released when the CPU operates with the high-speed system clock (X1 oscillation), temporarily switch the CPU clock to the internal high-speed oscillation clock before the next execution of the STOP instruction. Before changing the CPU clock from the internal highspeed oscillation clock to the high-speed system clock (X1 oscillation) after the STOP mode is released, check the oscillation stabilization time with the oscillation stabilization time counter status register (OSTC). p. 553 User's Manual U17397EJ4V0UD 727 APPENDIX D LIST OF CAUTIONS www..com (23/27) Chapter Soft Classification Function Details of Function Cautions Page Chapter 22 Standby function STOP mode p. 553 If the STOP instruction is executed when AMPH = 1, supply of the CPU clock is stopped for 4.06 to 16.12 s after the STOP mode is released when the internal high-speed oscillation clock is selected as the CPU clock, or for the duration of 160 external clocks when the high-speed system clock (external clock input) is selected as the CPU clock. For an external reset, input a low level for 10 s or more to the RESET pin. During reset input, the X1 clock, XT1 clock, internal high-speed oscillation clock, and internal low-speed oscillation clock stop oscillating. External main system clock input and external subsystem clock input become invalid. When the STOP mode is released by a reset, the STOP mode contents are held during reset input. However, the port pins become high-impedance, except for P130, which is set to low-level output. p. 557 p. 557 Chapter 23 Hard Reset function - p. 557 Block diagram of An LVI circuit internal reset does not reset the LVI circuit. reset function Watchdog timer overflow Soft RESF: Reset control flag register Poweron-clear circuit - A watchdog timer internal reset resets the watchdog timer. Do not read data by a 1-bit memory manipulation instruction. p. 558 p. 559 p. 565 Chapter 24 Soft If an internal reset signal is generated in the POC circuit, the reset control flag register (RESF) is cleared to 00H. Set the low-voltage detector by software after the reset status is released (see CHAPTER 25 LOW-VOLTAGE DETECTOR). p. 566 pp. 568, 569 In 2.7 V/1.59 V POC mode A voltage oscillation stabilization time of 1.93 to 5.39 ms is required after the supply p. 569 voltage reaches 1.59 V (TYP.). If the supply voltage rises from 1.59 V (TYP.) to 2.7 V (TYP.) within 1.93 ms, the power supply oscillation stabilization time of 0 to 5.39 ms is automatically generated before reset processing. In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection voltage (VPOC), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action. p. 570 Cautions for power-on-clear circuit Chapter 25 Soft Lowvoltage detector LVIM: LowTo stop LVI, follow either of the procedures below. voltage detection * When using 8-bit memory manipulation instruction: Write 00H to LVIM. register * When using 1-bit memory manipulation instruction: Clear LVION to 0. Input voltage from external input pin (EXLVI) must be EXLVI < VDD. p. 574 Soft Hard p. 574 LVIS: LowBe sure to clear bits 4 to 7 to "0". p. 575 voltage detection Do not change the value of LVIS during LVI operation. p. 575 level selection When an input voltage from the external input pin (EXLVI) is detected, the p. 575 register detection voltage (VEXLVI = 1.21 V (TYP.)) is fixed. Therefore, setting of LVIS is not necessary. When detecting level of supply voltage (VDD) When detecting level of input voltage from external input pin (EXLVI) <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately after the processing in <4>. p. 577 If supply voltage (VDD) detection voltage (VLVI) when LVIMD is set to 1, an internal p. 577 reset signal is not generated. <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately after the processing in <3>. If input voltage from external input pin (EXLVI) detection voltage (VEXLVI = 1.21 V (TYP.)) when LVIMD is set to 1, an internal reset signal is not generated. Input voltage from external input pin (EXLVI) must be EXLVI < VDD. p. 580 p. 580 p. 580 728 Hard User's Manual U17397EJ4V0UD APPENDIX D LIST OF CAUTIONS www..com (24/27) Hard Classification Function Chapter Details of Function Cautions Page Chapter 25 LowWhen detecting Input voltage from external input pin (EXLVI) must be EXLVI < VDD. voltage level of input detector voltage from external input pin (EXLVI) Cautions for low- In a system where the supply voltage (VDD) fluctuates for a certain period in the voltage detector vicinity of the LVI detection voltage (VLVI), the operation is as follows depending on how the low-voltage detector is used. (1) When used as reset The system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action (1) below. (2) When used as interrupt Interrupt requests may be frequently generated. Take (b) of action (2) below. Option byte 0082H, 0083H/ 1082H, 1083H 0080H/1080H 0081H/1081H Be sure to set 00H to 0082H and 0083H (0082H/1082H and 0083H/1083H when the boot swap function is used). p. 585 Soft p. 587 Chapter 26 Soft p. 590 Set a value that is the same as that of 0080H to 1080H because 0080H and 1080H p. 590 are switched during the boot swap operation. POCMODE can only be written by using a dedicated flash memory programmer. It p. 590 cannot be set during self-programming or boot swap operation during selfprogramming (at this time, 1.59 V POC mode (default) is set). However, because the value of 1081H is copied to 0081H during the boot swap operation, it is recommended to set a value that is the same as that of 0081H to 1081H when the boot swap function is used. Be sure to set 00H (disabling on-chip debug operation) to 0084H for products not equipped with the on-chip debug function (PD78F0544, 78F0545, 78F0546, and 78F0547). Also set 00H to 1084H because 0084H and 1084H are switched during the boot swap operation. p. 591 0084H/1084H To use the on-chip debug function with a product equipped with the on-chip debug p. 591 function (PD78F0547D), set 02H or 03H to 0084H. Set a value that is the same as that of 0084H to 1084H because 0084H and 1084H are switched during the boot swap operation. 0080H/1080H The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 p. 592 = 0 is prohibited. The watchdog timer continues its operation during self-programming and EEPROM p. 592 emulation of the flash memory. During processing, the interrupt acknowledge time is delayed. Set the overflow time and window size taking this delay into consideration. If LSROSC = 0 (oscillation can be stopped by software), the count clock is not p. 592 supplied to the watchdog timer in the HALT and STOP modes, regardless of the setting of bit 0 (LSRSTOP) of the internal oscillation mode register (RCM). When 8-bit timer H1 operates with the internal low-speed oscillation clock, the count clock is supplied to 8-bit timer H1 even in the HALT/STOP mode Be sure to clear bit 7 to 0. 0081H/1081H Chapter 27 Soft Flash IMS: Internal memory memory size switching register, IXS: internal expansion RAM size switching register Operation clock Be sure to clear bits 7 to 1 to "0". p. 592 p. 593 Be sure to set each product to the values shown in Table 27-1 after a reset release. p. 595 Be sure to set each product to the values shown in Table 27-2 after a reset release. p. 596 To set the memory size, set IMS and then IXS. Set the memory size so that the internal ROM and internal expansion RAM areas do not overlap. pp. 595, 596 Only the internal high-speed oscillation clock (fRH) can be used when CSI10 is used. p. 605 Only the X1 clock (fX) or external main system clock (fEXCLK) can be used when UART6 is used. p. 605 User's Manual U17397EJ4V0UD 729 APPENDIX D LIST OF CAUTIONS www..com (25/27) Soft Classification Function Chapter Details of Function Cautions Page Flash memory Processing of X1, P31 pins For products without an on-chip debug function (other than the PD78F0547D) and p. 605 having a product rank of "I", "K", or "E", and for the product with an on-chip debug function (PD78F0547D), connect P31/INTP2/OCD1A and P121/X1/OCD0A as follows when writing the flash memory with a flash memory programmer. * P31/INTP2/OCD1A: Connect to EVSS via a resistor (10 k: recommended). * P121/X1/OCD0A: When using this pin as a port, connect it to VSS via a resistor (10 k: recommended) (in the input mode) or leave it open (in the output mode). The above connection is not necessary when writing the flash memory by means of self programming. Chapter 27 Selecting When UART6 is selected, the receive clock is calculated based on the reset p. 607 communication command sent from the dedicated flash memory programmer after the FLMD0 pulse mode has been received. Hard Security Settings After the security setting for the batch erase is set, erasure cannot be performed for p. 609 the device. In addition, even if a write command is executed, data different from that which has already been written to the flash memory cannot be written, because the erase command is disabled. If a security setting that rewrites boot cluster 0 has been applied, boot cluster 0 of that p. 609 device will not be rewritten. Flash memory programming by selfprogramming The self-programming function cannot be used when the CPU operates with the subsystem clock. Input a high level to the FLMD0 pin during self-programming. Be sure to execute the DI instruction before starting self-programming. The self-programming function checks the interrupt request flags (IF0L, IF0H, IF1L, and IF1H). If an interrupt request is generated, self-programming is stopped. Self-programming is also stopped by an interrupt request that is not masked even in the DI status. To prevent this, mask the interrupt by using the interrupt mask flag registers (MK0L, MK0H, MK1L, and MK1H). Allocate the entry program for self-programming in the common area of 0000H to 7FFFH. Chapter 28 Hard p. 612 p. 612 p. 612 Soft p. 612 p. 612 On-chip PD78F0547D The PD78F0547D has an on-chip debug function. Do not use this product for mass p. 620 debug production because its reliability cannot be guaranteed after the on-chip debug function function has been used, given the issue of the number of times the flash memory can (PD78F be rewritten. NEC Electronics does not accept complaints concerning this product. 0547D When Input the clock from the OCD0A/X1 pin during on-chip debugging. p. 620 only) OCD0A/X1 and Control the OCD0A/X1 and OCD0B/X2 pins by externally pulling down the p. 620 OCD0B/X2 are OCD1A/P31 pin or by using an external circuit using the P130 pin (that outputs a low used level when the device is reset). Electrical PD78F0547D The PD78F0547D has an on-chip debug function. Do not use this product for mass p. 636 specificat production because its reliability cannot be guaranteed after the on-chip debug ions function has been used, given the issue of the number of times the flash memory can (standard be rewritten. NEC Electronics does not accept complaints concerning this product. products) Absolute pp. 636, Product quality may suffer if the absolute maximum rating is exceeded even 637 maximum momentarily for any parameter. That is, the absolute maximum ratings are rated ratings values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. X1 oscillator When using the X1 oscillator, wire as follows in the area enclosed by the broken lines p. 638 characteristics in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. Chapter 30 730 Hard User's Manual U17397EJ4V0UD APPENDIX D LIST OF CAUTIONS www..com (26/27) Hard Classification Function Chapter Details of Function Cautions Page Chapter 30 Electrical specifications (standard products) X1 oscillator Since the CPU is started by the internal high-speed oscillation clock after a reset p. 638 characteristics release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. p. 639 XT1 Oscillator When using the XT1 oscillator, wire as follows in the area enclosed by the Characteristics broken lines in the above figure to avoid an adverse effect from wiring capacitance * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. The XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the X1 oscillator. Particular care is therefore required with the wiring method when the XT1 clock is used. Oscillator constants p. 639 The oscillator constants shown above are reference values based on evaluation pp. 640, in a specific environment by the resonator manufacturer. If it is necessary to 641 optimize the oscillator characteristics in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the 78K0/KF2 so that the internal operation conditions are within the specifications of the DC and AC characteristics. pp. 658, Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated 659 values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Chapter 32 Hard Electrical specifications ((A) grade products, target ) Absolute maximum ratings X1 oscillator When using the X1 oscillator, wire as follows in the area enclosed by the broken p. 660 characteristics lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. Since the CPU is started by the internal high-speed oscillation clock after a reset p. 660 release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. User's Manual U17397EJ4V0UD 731 APPENDIX D LIST OF CAUTIONS www..com (27/27) Hard Classification Function Chapter Details of Function Cautions Page Chapter 32 Electrical specifications ((A) grade products, target ) p. 661 XT1 Oscillator When using the XT1 oscillator, wire as follows in the area enclosed by the Characteristics broken lines in the above figure to avoid an adverse effect from wiring capacitance * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. p. 661 The XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the X1 oscillator. Particular care is therefore required with the wiring method when the XT1 clock is used. Chapter 33 Hard Recommended soldering conditions - Do not use different soldering methods together (except for partial heating). p. 683 Chapter 34 Soft Wait - When the CPU is operating on the subsystem clock and the peripheral hardware p. 685 clock is stopped, do not access the registers listed above using an access method in which a wait request is issued. 732 User's Manual U17397EJ4V0UD www..com APPENDIX E REVISION HISTORY E.1 Major Revisions in This Edition (1/2) Page Throughout Addition of (A) standard products Description Classification (d) PD78F0544GC(A)-GAD-AX, 78F0544GK(A)-GAK-AX, 78F0545GC(A)-GAD-AX, 78F0545GK(A)-GAK-AX, 78F0546GC(A)-GAD-AX, 78F0546GK(A)-GAK-AX, 78F0547GC(A)-GAD-AX, 78F0547GK(A)-GAK-AX CHAPTER 3 CPU ARCHITECTURE p. 46 Addition of Note 1 to Table 3-1 Set Values of Internal Memory Size Switching Register (IMS) and Internal Expansion RAM Size Switching Register (IXS) Addition of Note 3 to Table 3-7 Special Function Register List (4/4) (c) p. 70 (c) CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F0546, 78F0547, AND 78F0547D ONLY) p. 84 Addition of 4.2 Difference in Representation of Memory Space (c) CHAPTER 5 PORT FUNCTIONS p. 126 Addition of Note Figure 5-29 Format of Port Register (c) CHAPTER 6 CLOCK GENERATOR p. 137 p. 153, p. 166 Change of Cautions 2 and 3 (description concerning stopping time of supplying CPU clock) in Figure 6-2 Format of Clock Operation Mode Select Register (OSCCTL) Partial change (CPU clock supply stop time when AMPH = 1) of Note in 6.6.1 (1) <1> Setting frequency (OSCCTL register) Change of CPU clock supply stop time when AMPH = 1 in Table 6-6 Changing CPU Clock (b) (b) (b) CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 p. 196 p. 214 Change of (c) 16-bit timer output control register 0n (TOC0n) of Figure 7-25 Example of Register Settings in External Event Counter Mode Change of Figure 7-40 Timing Example of Free-Running Timer Mode (CR00n: Compare Register, CR01n: Capture Register) (change of figure to that where CR00n = 0000H) (a) (c) CHAPTER 11 WATCHDOG TIMER p. 295 pp. 295, 296 Change of Caution 5 in 11.4.1 Controlling operation of watchdog timer Change of Caution 2 in Table 11-3 Setting of Overflow Time of Watchdog Timer and Table 11-4 Setting Window Open Period of Watchdog Timer (c) (c) CHAPTER 20 INTERRUPT FUNCTIONS p. 522 p. 527 Addition of Note 4 to Table 20-1 Interrupt Source List (1/2) Addition of Note 1 to 5 to Table 20-2 Flags Corresponding to Interrupt Request Sources (2/2) (c) (c) CHAPTER 22 STANDBY FUNCTION p. 552 p. 553 p. 553 pp. 554, 555 Addition of Note to and change of description of Serial interface CSIA0 and IIC0 in Table 22-3 Operating Statuses in STOP Mode Change of Caution 4 in 22.2.2 (1) STOP mode setting and operating statuses Change of Figure 22-5 Operation Timing When STOP Mode Is Released Change of Figure 22-6 STOP Mode Release by Interrupt Request Generation (c) (b), (c) (a), (c) (a), (c) Remark "Classification" in the above table classifies revisions as follows. (a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note, (d): Addition/change of package, part number, or management division, (e): Addition/change of related documents User's Manual U17397EJ4V0UD 733 APPENDIX E REVISION HISTORY www..com (2/2) Page CHAPTER 23 RESET FUNCTION p. 562 Addition of Note 4 to Table 23-2. Hardware Statuses After Reset Acknowledgment (1/3) (c) Description Classification CHAPTER 26 OPTION BYTE p. 592 Change of Caution 2 in Figure 26-1 Format of Option Byte (1/2) (c) CHAPTER 27 FLASH MEMORY p. 595 p. 596 p. 609 Addition of Note 1 to Table 27-1 Internal Memory Size Switching Register Settings Addition of Note to Table 27-2 Internal Expansion RAM Size Switching Register Settings Partial addition of description to 27.8 Security Settings (c) (c) (c) CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) p. 637 p. 638 p. 639 pp. 643 to 646 Change of storage temperature of Absolute Maximum Ratings Addition of Note 2 to X1 Oscillator Characteristics Change of MIN. value in condition where 1.8 V VDD < 2.7 V of internal low-speed oscillation clock frequency (fRL) in Internal Oscillator Characteristics DC Characteristics * Addition of EXCLK and EXCLKS in the condition of Input voltage, high (VIH1) and Input voltage, low(VIlL1) * Change of MAX. value of Input voltage, high (VIH4) * Addition of FLMD0 and RESET in the condition of Input leakage current, high (ILH1) and Input leakage current, low (ILIL1) * Change of the condition of Pull-up resistor * Change of Notes 1, 2 , 4, and 5 of Supply current * Change of Note 8 of Watchdog timer operating current * Change of MAX. value of LVI operating current pp. 647, 648 (1) Bacic operation in AC Characteristics * * * * p. 658 Change of External main system clock input high-level width, low-level width (tEXCLKH, tEXCLKL) Change of External subsystem clock input high-level width, low-level width (tEXCLKSH, tEXCLKSL) Addition of Note 2 Change of the figure of AC Timing Test Points (c) (b, c) (b) (c) (b) (b, c) CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS, TARGET) Addition of chapter CHAPTER 32 PACKAGE DRAWINGS pp. 680, 682 Addition of the package drawings of (A) grade products (c) CHAPTER 33 RECOMMENDED SOLDERING CONDITIONS p. 683 Addition of Remark (c) APPENDIX A DEVELOPMENT TOOLS pp 688 to 690 p. 681 pp. 693, 695 Addition of Note 1 and (3) When using the on-chip debug emulator with programming function QB-MINI2 to Figure A-1 Development Tool Configuration Addition of description to Note 1 in A.2 Language Processing Software Addition of A.4.2 When using on-chip debug emulator with programming function QB-MINI2 and A.5.3 When using on-chip debug emulator with programming function QB-MINI2 (c, d) (c) (d) Remark "Classification" in the above table classifies revisions as follows. (a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note, (d): Addition/change of package, part number, or management division, (e): Addition/change of related documents 734 User's Manual U17397EJ4V0UD APPENDIX E REVISION HISTORY www..com E.2 Revision History of Preceding Editions Here is the revision history of the preceding editions. Chapter indicates the chapter of each edition. (1/13) Edition 2nd Description Addition of Note on a product with on-chip debug function to and modification of operating ambient temperature in 1.1 Features Addition of special grade products supporting automotive equipment to 1.2 Applications Modification of 1.3 Ordering Information Addition of Note to and modification of Caution 1 in 1.4 Pin Configuration (Top View) Modification of the following items on the function list in 1.5 78K0/Kx2 Series Lineup * Supply voltage range of internal low-speed oscillation clock * Detection voltage of POC * Operating ambient temperature Addition of pin to "On-chip debug" in 1.6 Block Diagram Modification of the following items in 1.7 Outline of Functions * Oscillation frequency range of high-speed system clock * Supply voltage range of internal low-speed oscillation clock * Operating ambient temperature Modification of outline of timer in 1.7 Outline of Functions Modification of Table 2-1 Pin I/O Buffer Power Supplies Addition of Note to 2.1 Pin Function List Modification of descriptions in 2.2.16 VDD and EVDD, and 2.2.17 VSS and EVSS Modification of recommended connection of unused pins of P121/X1, P122/X2/EXCLK, P123/XT1, and P124/XT2/EXCLKS in Table 2-2 Pin I/O Circuit Types Addition of Caution 2 to 3.1 Memory Space Modification of Table 3-1 Set Values of Internal Memory Size Switching Register (IMS) and Internal Expansion RAM Size Switching Register (IXS) Modification of Figure 3-1 Memory Map (PD78F0544) to Figure 3-5 Memory Map (PD78F0547D) Modification of description in (3) Option byte area and (5) On-chip debug security ID setting area (PD78F0547D only) in 3.1.1 Modification of description in 3.1.2 Memory bank (PD78F0546, 78F0547, and 78F0547D only) Addition of Note to Figure 3-8 Correspondence Between Data Memory and Addressing (PD78F0546) and Figure 3-9 Correspondence Between Data Memory and Addressing (PD78F0547, 78F0547D) Addition to description in 3.3 Instruction Address Addressing Addition to description in 3.3.2 Immediate addressing Addition to description in 3.3.3 Table indirect addressing Addition to description in 3.4.3 Direct addressing Modification of [Description example] in 3.4.4 Short direct addressing Addition to description in 3.4.6 Register indirect addressing Addition to description in 3.4.7 Based addressing Addition to description in 3.4.8 Based indexed addressing Addition of chapter CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F0546, 78F0547, AND 78F0547D ONLY) CHAPTER 3 CPU ARCHITECTURE CHAPTER 2 PIN FUNCTIONS Chapter CHAPTER 1 OUTLINE User's Manual U17397EJ4V0UD 735 APPENDIX E REVISION HISTORY www..com (2/13) Edition 2nd Description Modification of Table 5-1 Pin I/O Buffer Power Supplies Addition of Caution to 5.2.1 Port 0 Addition of Caution to 5.2.2 Port 1 Addition of description to 5.2.3 Port 2 and addition of Table 5-4 Setting Functions of P20/ANI0 to P27/ANI7 Pins Addition of Figure 5-19 Block Diagram of P64 to P67 Addition of Remark to and modification of Caution in 5.2.9 Port 12 Modification of Figure 5-21 Block Diagram of P120 Modification of Figure 5-22 Block Diagram of P121 to P124 Addition of a figure to Remark in 5.2.10 Port 13 Addition of (4) A/D port configuration register (ADPC) to 5.3 Registers Controlling Port Function Addition of Remark 2 and Notes 1 and 2 to Table 5-5 Settings of Port Mode Register and Output Latch When Using Alternate Function (2/2) Modification of oscillation frequency range X1 oscillator and external main system clock in 6.1 (1) Main system clock Addition to description in 6.1 (3) Internal low-speed oscillation clock Modification of Figure 6-1 Block Diagram of Clock Generator Modification of Figure 6-3 Format of Processor Clock Control Register (PCC) Addition of 6.3 (3) Setting of operation mode for subsystem clock pin Modification of description in 6.3 (8) Oscillation stabilization time select register (OSTS) Modification of oscillation frequency range in 6.4.1 X1 oscillator Modification of description in 6.4.3 When subsystem clock is not used Addition of Figure 6-12 Clock Generator Operation When Power Supply Voltage Is Turned On (When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0)) Addition of Figure 6-13 Clock Generator Operation When Power Supply Voltage Is Turned On (When 2.7 V/1.59 V POC Mode Is Set (Option Byte: POCMODE = 1)) Modification of 6.6.1 Controlling high-speed system clock Modification of 6.6.2 Example of controlling internal high-speed oscillation clock Modification of 6.6.3 Example of controlling subsystem clock Modification of description in Table 6-4 Clocks Supplied to CPU and Peripheral Hardware, and Register Setting Addition of Remark to Figure 6-14 CPU Clock Status Transition Diagram (When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0)) Modification of the following items in Table 6-5 CPU Clock Transition and SFR Register Setting Examples (3) CPU operating with subsystem clock (D) after reset release (A) (4) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C) (5) CPU clock changing from internal high-speed oscillation clock (B) to subsystem clock (D) (7) CPU clock changing from high-speed system clock (C) to subsystem clock (D) (9) CPU clock changing from subsystem clock (D) to high-speed system clock (C) Modification of Table 6-6 Changing CPU Clock Addition of 6.6.8 Time required for switchover of CPU clock and main system clock Addition of 6.6.9 Conditions before clock oscillation is stopped Addition of 6.6.10 Peripheral Hardware and Source Clocks CHAPTER 6 CLOCK GENERATOR Chapter CHAPTER 5 PORT FUNCTIONS 736 User's Manual U17397EJ4V0UD APPENDIX E REVISION HISTORY www..com (3/13) Edition 2nd Revision of chapter Description Chapter CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 CHAPTER 9 8-BIT TIMERS H0 AND H1 Modification of description in 8.2 (2) 8-bit timer compare register 5n (CR5n) Modification of Figure 9-2 Block Diagram of 8-Bit Timer H1 Modification of description in (1) 8-bit timer H compare register 0n (CMP0n) and (2) 8-bit time r H compare register 1n (CMP1n) in 9.2 Modification of Figure 9-6 Format of 8-Bit Timer H Mode Register 1 (TMHMD1) Modification of Figure 9-12 (e) Operation by changing CMP1n (CMP1n = 02H 03H, CMP0n = A5H) Modification of description in 9.4.3 Carrier generator operation (8-bit timer H1 only) Addition of <3> to Figure 9-13 Transfer Timing Addition of <8> to Setting in 9.4.3 Modification of (a) Operation when CMP01 = N, CMP11 = N and (b) Operation when CMP01 = N, CMP11 = M in Figure 9-15 Modification of description in Figure 9-15 (c) Operation when CMP11 is changed Modification of description in 11.1 Functions of Watchdog Timer Addition to description in and addition of Caution 4 to 11.4.1 Controlling operation of watchdog timer Addition of Note 1 and Cautions 1 and 2 to Figure 12-2 Format of Clock Output Selection Register (CKS) CHAPTER 11 WATCHDOG TIMER CHAPTER 12 CLOCK OUTPUT/ BUZZER OUTPUT CONTROLLER CHAPTER 13 A/D CONVERTER Modification of the following items in 13.2 Configuration of A/D Converter (2) Sample & hold circuit (3) Series resistor string (5) Successive approximation register (SAR) (9) AVREF pin Addition to Caution 1 in and addition of Caution 4 to Table 13-2 A/D Conversion Time Selection Modification of Cautions 2 and 3 in Figure 13-8 Format of Analog Input Channel Specification Register (ADS) Modification of description in 13.3 (5) A/D port configuration register (ADPC) Modification of Cautions 1 and 2 in Figure 13-9 Format of A/D Port Configuration Register (ADPC) Modification of Table 13-3 Setting Functions of ANI0/P20 to ANI7/P27 Pins Modification of 13.4.1 Basic operations of A/D converter Modification of description in Figure 13-11 Basic Operation of A/D Converter Modification of expression in 13.4.2 Input voltage and conversion results Modification of description in 13.4.3 A/D converter operation mode Modification of the description of the following items in 13.6 Cautions for A/D Converter (1) Operating current in STOP mode (4) Noise countermeasures (6) Input impedance of ANI0 to ANI7 pins (11) Internal equivalent circuit User's Manual U17397EJ4V0UD 737 APPENDIX E REVISION HISTORY www..com (4/13) Edition 2nd Description Addition of maximum transfer rate and Caution 4 to 14.1 (2) Asynchronous serial interface (UART) mode Addition of Caution 1 to 14.2 (3) Transmit shift register 0 (TXS0) Addition of Caution 5 to Figure 14-2 Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) Modification of description in 14.3 (2) Asynchronous serial interface reception error status register 0 (ASIS0) Modification of Caution 1 in Figure 14-9 Reception Completion Interrupt Request Timing Addition of Table 14-4 Set Value of TPS01 and TPS00 Addition of maximum transfer rate and Cautions 4 and 5 to 15.1 (2) Asynchronous serial interface (UART) mode Modification of Figure 15-1 LIN Transmission Operation Modification of Figure 15-2 LIN Reception Operation Addition of Caution 3 to 15.2 (3) Transmit buffer register 6 (TXB6) Addition of Cautions 4 and 5 to Figure 15-5 Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) Modification of description in 15.3 (2) Asynchronous serial interface reception error status register 6 (ASIS6) Addition of Caution 6 to Figure 15-10 Format of Asynchronous Serial Interface Control Register 6 (ASICL6) Modification of description in 15.3 (7) Input switch control register (ISC) Modification of Caution 1 in 15.4.2 (2) (e) Normal reception Modification of Figure 16-1 Block Diagram of Serial Interface CSI10 Modification of Figure 16-2 Block Diagram of Serial Interface CSI11 Modification of Caution 2 in 16.2 (1) Transmit buffer register 1n (SOTB1n) Modification of Caution 2 in 16.2 (2) Serial I/O shift register 1n (SIO1n) Modification of Note 2 in Figure 16-3 Format of Serial Operation Mode Register 10 (CSIM10) Modification of Note 2 in Figure 16-4 Format of Serial Operation Mode Register 11 (CSIM11) Modification of Caution 2 in Figure 16-5 Format of Serial Clock Selection Register 10 (CSIC10) Modification of Caution 2 in Figure 16-6 Format of Serial Clock Selection Register 11 (CSIC11) Modification of Note 1 of CSIM10 and CSIM11 in 16.4.1 (1) Register used Addition of (b) Type 3: CKP1n = 1, DAP1n = 0 and (d) Type 4: CKP1n = 1, DAP1n = 1 to Figure 16-11 Output Operation of First Bit Addition of (b) Type 3: CKP1n = 1, DAP1n = 0 and (d) Type 4: CKP1n = 1, DAP1n = 1 in Figure 16-12 Output Value of SO1n Pin (Last Bit) Modification of 17.4.3 (2) Automatic transmit/receive data setting Modification of Figure 17-14 Automatic Transmission/Reception Mode Flowchart Modification of description of internal buffer RAM in 17.4.3 (3) (a) Automatic transmission/reception mode ((i) Starting automatic transmission/reception, (ii) Completion of transmission/reception) Modification of Figure 17-18 Automatic Transmission Mode Flowchart CHAPTER 17 SERIAL INTERFACE CSIA0 CHAPTER 16 SERIAL INTERFACE CSI10, CSI11 CHAPTER 15 SERIAL INTERFACE UART6 Chapter CHAPTER 14 SERIAL INTERFACE UART0 738 User's Manual U17397EJ4V0UD APPENDIX E REVISION HISTORY www..com (5/13) Edition 2nd Description Modification of Figure 17-20 Repeat Transmission Mode Flowchart Modification of description in 17.4.3 (4) (a) Busy control option Modification of Figure 17-27 Example of Operation Timing of Bit Shift Detection Function by Busy Signal (When BUSYLV0 = 1) Modification of description in 17.4.3 (5) Automatic transmit/receive interval time Modification of Figure 17-28 Example of Interval Time for Automatic Transmission/Reception (When ADTI0 = 00H, STBE0 = 1, BUSYE0 = 0 (Two Clocks)) Modification of Figure 18-1 Block Diagram of Serial Interface IIC0 Addition of Caution 2 to 18.2 (1) IIC shift register 0 (IIC0) and addition to description in (2) Slave address register 0 (SVA0) Addition of 18.2 (13) Stop condition generator Addition of description to IICE0 and addition of Caution to Figure 18-5 Format of IIC Control Register 0 (IICC0) (1/4) Addition of Note 2 to Figure 18-5 Format of IIC Control Register 0 (IICC0) (2/4) Addition of description to STT0 in Figure 18-5 Format of IIC Control Register 0 (IICC0) (3/4) Addition of clearing condition to STCF and IICBSY in Figure 18-7 Format of IIC Flag Register 0 (IICF0) Modification of description in 18.3 (4) IIC clock selection register 0 (IICCL0) Modification of description in 18.3 (6) I C transfer clock setting method Modification of Table 18-2 Selection Clock Setting Addition of cause that ACK is not returned to 18.5.4 Acknowledge (ACK) Addition of 18.5.7 Canceling wait Modification of Table 18-6 Wait Periods and Figure 18-20 Communication Reservation Timing Modification of Table 18-7 Wait Periods Addition of (4) to (6) to 18.5.15 Cautions Modification of 18.5.16 (1) Master operation (single-master system) and (2) Master operation (multi-master system) Modification of Figure 18-25 Slave Operation Flowchart (1) and Figure 18-26 Slave Operation Flowchart (2) Addition of Note to (a) (i) When WTIM0 = 0 to and modification of (ii) When WTIM0 = 1 in 18.5.17 (1) Master device operation Addition of Notes 1 to 3 to (b) (i) When WTIM0 = 0 in 8.5.17 (1) Master device operation Addition of Note to (c) (i) When WTIM0 = 0 in 18.5.17 (1) Master device operation Modification of the value of the following items of IICS0 register in 18.5.17 (2) (d) (i) When WTIM0 = 0 (after restart, does not match with address (= not extension code)) (2) (d) (ii) When WTIM0 = 1 (after restart, does not match with address (= not extension code)) (3) (d) (i) When WTIM0 = 0 (after restart, does not match with address (= not extension code)) (3) (d) (ii) When WTIM0 = 1 (after restart, does not match with address (= not extension code)) (6) (d) (ii) Extension code (6) (e) When loss occurs due to stop condition during data transfer (6) (h) (ii) When WTIM0 = 1 Addition of description to 18.5.17 (5) Arbitration loss operation (operation as slave after arbitration loss) and (6) Operation when arbitration loss occurs (no communication after arbitration loss) 2 Chapter CHAPTER 17 SERIAL INTERFACE CSIA0 CHAPTER 18 SERIAL INTERFACE IIC0 User's Manual U17397EJ4V0UD 739 APPENDIX E REVISION HISTORY www..com (6/13) Edition 2nd Description Addition of description when (i) When WTIM0 = 0 to the following items in 18.5.17 (6) Operation when arbitration loss occurs (no communication after arbitration loss) (f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition (g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition (h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition Modification of Figure 18-27 Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) and Figure 18-28 Example of Slave to Master Communication (When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) Modification of Caution 3 in 22.1.1 Standby function Modification of description in 22.1.2 (2) Oscillation stabilization time select register (OSTS) Addition of clock output and buzzer output to items in and addition of Note to Table 22-1 Operating Statuses in HALT Mode Modification of Figure 22-4 HALT Mode Release by Reset Addition of clock output and buzzer output to items in Table 22-3 Operating Statuses in STOP Mode Modification of Figure 22-5 Operation Timing When STOP Mode Is Released Modification of Figure 22-7 STOP Mode Release by Reset Modification of Figure 23-2 Timing of Reset by RESET Input Modification of Figure 23-3 Timing of Reset Due to Watchdog Timer Overflow Modification of Figure 23-4 Timing of Reset in STOP Mode by RESET Input Addition of clock output and buzzer output to items in Table 23-1 Operation Statuses During Reset Period Modification of table in Note of Table 23-2 Hardware Statuses After Reset Acknowledgment (3/3) Addition of description of 2.7 V/1.59 V POC mode to 24.1 Functions of Power-on-Clear Circuit Modification of 24.3 Operation of Power-on-Clear Circuit Modification of Figure 24-3 Example of Software Processing After Reset Release (1/2) Modification of Figure 25-1 Block Diagram of Low-Voltage Detector Modification of Figure 25-3 Format of Low-Voltage Detection Level Selection Register (LVIS) Addition of (2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) to Figure 25-5 Timing of Low-Voltage Detector Internal Reset Signal Generation (Detects Level of Supply Voltage (VDD)) Modification of (1) In 1.59 V POC mode (option byte: POCMODE = 0) in and addition of (2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) to Figure 25-7 Timing of LowVoltage Detector Interrupt Signal Generation (Detects Level of Supply Voltage (VDD)) Modification of Figure 25-8 Timing of Low-Voltage Detector Interrupt Signal Generation (Detects Level of Input Voltage from External Input Pin (EXLVI)) Modification of Figure 25-9 Example of Software Processing After Reset Release (1/2) Modification of description in 26.1 Functions of Option Bytes Modification of Note in and addition of setting of area 0081H/1081H to 0084H/1084H to Figure 26-1 Format of Option Byte Modification of description example of software for setting the option bytes CHAPTER 26 OPTION BYTE CHAPTER 25 LOWVOLTAGE DETECTOR CHAPTER 24 POWER-ON-CLEAR CIRCUIT CHAPTER 23 RESET FUNCTION CHAPTER 22 STANDBY FUNCTION Chapter CHAPTER 18 SERIAL INTERFACE IIC0 740 User's Manual U17397EJ4V0UD APPENDIX E REVISION HISTORY www..com (7/13) Edition 2nd Description Addition of Caution to Figure 27-1 Format of Internal Memory Size Switching Register (IMS) Addition of Caution to Figure 27-2 Format of Internal Expansion RAM Size Switching Register (IXS) Modification of pin numbers in Table 27-3 Wiring Between 78K0/KF2 and Dedicated Flash Programmer Modification of wiring of pins 1, 2, and 11 in Figure 27-3 Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10) Mode Modification of wiring of pins 1, 2, and 11 in Figure 27-4 Example of Wiring Adapter for Flash Memory Writing in UART (UART6) Mode Modification of transfer rate in (1) CSI10 and (2) UART6 in 27.5 Modification of transfer rate in Speed column of Table 27-7 Communication Modes Addition of 27.8 Security Settings Modification of 27.9.1 Boot swap function Revision of chapter CHAPTER 28 ONCHIP DEBUG FUNCTION (PD78F0547D ONLY) CHAPTER 30 ELECTRICAL SPECIFICATIONS (TARGET) CHAPTER 31 PACKAGE DRAWINGS CHAPTER 32 CAUTIONS FOR WAIT Chapter CHAPTER 27 FLASH MEMORY Revision of chapter Addition of package drawing Modification of APPENDIX A DEVELOPMENT TOOLS APPENDIX B NOTES ON TARGET SYSTEM DESIGN APPENDIX D REVISION HISTORY CHAPTER 2 PIN FUNCTIONS CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F0546, 78F0547, AND 78F0547D ONLY) CHAPTER 6 CLOCK GENERATOR Addition of chapter 2nd edition Modification of Note in 2.2.12 AVREF and addition of wiring diagram and Caution to 2.2.15 (before REGC correction) Modification of software example (to store a value to be referenced in register A) in 4.3.1 Referencing values between memory banks Modification of software example in 4.3.2 Branching instruction between memory banks Modification of software example in 4.3.3 Subroutine call between memory banks Modification of software example in 4.3.4 Instruction branch to bank area by interrupt Change of Remark in 6.4.3 When subsystem clock is not used User's Manual U17397EJ4V0UD 741 APPENDIX E REVISION HISTORY www..com (8/13) Edition Description Chapter CHAPTER 6 CLOCK GENERATOR 2nd edition Correction of condition of clock oscillation frequency of following items in Table 6-5 CPU Clock Transition and SFR Register Setting Examples (less than 10 MHz 1 MHz fXH (before correction) more than 10 MHz 10 MHz < fXH 20 MHz) (2) CPU operating with high-speed system clock (C) after reset release (A) (4) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C) (9) CPU clock changing from subsystem clock (D) to high-speed system clock (C) Addition of Caution to Figure 9-3 Format of 8-Bit Timer H Compare Register 0n (CMP0n) Modification of Figure 13-22 Internal Equivalent Circuit of ANIn Pin and Table 13-4 Resistance and Capacitance Values of Equivalent Circuit (Reference Values) Deletion of Note in Table 22-3 Operating Statuses in STOP Mode CHAPTER 9 8-BIT TIMERS H0 AND H1 CHAPTER 13 A/D CONVERTER CHAPTER 22 STANDBY FUNCTION Modification in and addition of Note to Figure 24-2 Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector Modification of operation stabilization time when LVION = 1 (10 s (TYP.) 10 s (MAX.)) CHAPTER 24 POWER-ON-CLEAR CIRCUIT CHAPTER 25 LOWVOLTAGE DETECTOR Change of Figure 27-18 Example of Executing Boot Swapping Change of MAX. value of "8 MHz internal oscillator, 1.8 V VDD < 2.7 V" in Internal Oscillator Characteristics (10 MHz 10.4 MHz) Change of Note 2 in and addition of Notes 4 to 8 to DC Characteristics (4/4) Addition of Note 1 to (1) Basic operation of AC Characteristics Change of MIN. value of minimum pulse width of 1.59 V POC Circuit Characteristics (50 CHAPTER 27 FLASH MEMORY CHAPTER 30 ELECTRICAL SPECIFICATIONS (TARGET) s 200 s) Change of MIN. value of minimum pulse width of LVI Circuit Characteristics (50 s 200 s) Change of number of rewrites per chip in Flash Memory Programming Characteristics (MIN. value to MAX. value: 100 times MIN. value: 100 times) 3rd edition Extending value range of capacitor ("0.47 F: target" "0.47 to 1 F: recommended) Change of power supply voltage inclination tPTH from "0.5 V/ms (MAX.)" to "0.5 V/ms (MIN.)" Addition of following related documents of device * 78K0/Kx2 Flash Memory Programming (Programmer) Application Note * 78K0/Kx2 Flash Memory Self Programming User's Manual * PG-FPL3 Flash Memory Programmer User's Manual Deletion of description concerning production process division management from 1.1 Features Change of 1.3 Ordering Information Modification of Caution 1 and addition of Caution 2 to 1.4 Pin Configuration (Top View) Deletion of description concerning production process division management from 1.5 78K0/Kx2 Series Lineup Deletion of description concerning production process division management from 1.7 Outline of Functions INTRODUCTION Throughout CHAPTER 1 OUTLINE 742 User's Manual U17397EJ4V0UD APPENDIX E REVISION HISTORY www..com (9/13) Edition 3rd edition Description Addition of Caution 2, Note, and Remark 1 to 2.2.4 P30 to P33 (port 3) Addition of Caution, Note, and Remark 1 to 2.2.9 P120 to P124 (port 12) Addition of following contents to Table 2-2 Pin I/O Circuit Types * Addition of Notes 2 and 3 and Remark to P31/INTP2/OCD1A pin * Addition of Notes 2 and 5 and Remark to P121/X1/OCD0A pin * Addition of Note 4 to FLMD0 pin * Addition of connection of RESET pin when not used * Addition of Remark Change of numeric values in program area in Figures 3-1 Memory Map (PD78F0544) to 3-5 Memory Map (PD78F0547D) Addition of Remark and block number figure to Figures 3-1 Memory Map (PD78F0544) to 3-5 Memory Map (PD78F0547D) Addition of Table 3-2 Correspondence Between Address Values and Block Numbers of Flash Memory Change of software example in 4.3.1 Referencing values between memory banks. Deletion of Remark from old edition Change of software example 1 in and addition of example 2 to 4.3.2 Branching instruction between memory banks. Deletion of Remark from old edition Change of software example in 4.3.3 Subroutine call between memory banks. Change of Remark in old edition. Change of setting of digital input and output in Table 5-4 Setting Functions of P20/ANI0 to P27/ANI7 Pins Addition of Caution to 5.2.3 Port 2 Addition of Caution 3, Note, and Remark 1 to 5.2.4 Port 3 Addition of Caution 2, Note, and Remark 1 to 5.2.9 Port 12 Addition of Note to Figure 5-29 Format of Port Register Change of setting of digital input and output in Table 5-6 Setting Functions of ANI0/P20 to ANI7/P27 Pins Addition of 5.6 Cautions on 1-bit Manipulation Instruction for Port Register n (Pn) Addition of OR circuit to Figure 6-1 Block Diagram of Clock Generator Change of Cautions 2 and 3 (description concerning stopping time of supplying CPU clock) in Figure 6-2 Format of Clock Operation Mode Select Register (OSCCTL) Addition of description of external clock input to 6.4.1 X1 oscillator and 6.4.2 XT1 oscillator Change of voltage oscillation stabilization time and reset processing time in and addition of Note 1 concerning waiting for oscillation accuracy stabilization to Figure 6-12 Clock Generator Operation When Power Supply Voltage Is Turned On (When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0)) Addition of Caution 1 and waiting time for oscillation accuracy stabilization to and change of reset processing time in Figure 6-13 Clock Generator Operation When Power Supply Voltage Is Turned On (When 2.7 V/1.59 V POC Mode Is Set (Option Byte: POCMODE = 1)) Partial change (CPU clock supply stop time when AMPH = 1) of Note in 6.6.1 (1) <1> Setting frequency (OSCCTL register) and 6.6.1 (2) <1> Setting frequency (OSCCTL register) Change of Remark in Figure 6-14 CPU Clock Status Transition Diagram (When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0)) CHAPTER 6 CLOCK GENERATOR CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F0546, 78F0547, AND 78F0547D ONLY) CHAPTER 5 PORT FUNCTIONS CHAPTER 3 CPU ARCHITECTURE Chapter CHAPTER 2 PIN FUNCTIONS User's Manual U17397EJ4V0UD 743 APPENDIX E REVISION HISTORY www..com (10/13) Edition 3rd edition Description Change of CPU clock supply stop time when AMPH = 1 in Table 6-6 Changing CPU Clock Change of Remark 2 in Table 6-7 Time Required for Switchover of CPU Clock and Main System Clock Cycle Division Factor Addition of (iii) Setting range when CR00n or CR01n is used as a compare register Partial change of description of bits 3 and 2 (TMC0n3, TMC0n2: n = 0, 1) in Figure 7-6 Format of 16-Bit Timer Mode Control Register 00 (TMC00) and Figure 7-7 Format of 16-Bit Timer Mode Control Register 01 (TMC01) Change of (c) 16-bit timer output control register 0n (TOC0n) of Figure 7-22 Example of Register Settings for Square-Wave Output Operation Change of timing chart in Figure 7-23 Example of Software Processing for SquareWave Output Function Change of (c) 16-bit timer output control register 0n (TOC0n) of Figure 7-25 Example of Register Settings in External Event Counter Mode Change of Figure 7-26 Example of Software Processing in External Event Counter Mode Change of Figure 7-40 Timing Example of Free-Running Timer Mode (CR00n: Compare Register, CR01n: Capture Register) (change of figure to that where CR00n = 0000H) Change of Caution in Figure 7-46 Example of Register Settings for PPG Output Operation Change of Caution in Figure 7-49 Example of Register Settings for One-Shot Pulse Output Operation Change of restrictions on operations as external event counter, as PPG output, and as oneshot pulse output in Table 7-5 Restrictions for Each Channel of 16-Bit Timer/Event Counter 0n Change of Caution 3 in Figure 8-7 Format of 8-Bit Timer Mode Control Register 50 (TMC50) and Figure 8-8 Format of 8-Bit Timer Mode Control Register 51 (TMC51) Change of set value of TMC5n in Setting <1> in 8.4.2 Operation as external event counter Change of Caution in Figure 9-3 Format of 8-Bit Timer H Compare Register 0n (CMP0n) Partial addition of description to 9.2 (2) 8-bit timer H compare register 1n (CMP1n) Change of Caution 1 of Figure 9-5 Format of 8-Bit Timer H Mode Register 0 (TMHMD0) and Figure 9-6 Format of 8-Bit Timer H Mode Register 1 (TMHMD1) Partial change of description of RMC1 and NRZB1 bits in and addition of Caution to Figure 9-7 Format of 8-Bit Timer H Carrier Control Register 1 (TMCYC1) Change of (c) Operation when CMP0n = 00H in Figure 9-10 Timing of Interval Timer/Square-Wave Output Operation Partial change of description of RMC1 and NRZB1 bits in 9.4.3 (2) Carrier output control Change of setting of digital input and output in Table 13-3 Setting Functions of ANI0/P20 to ANI7/P27 Pins Change of maximum transfer rate in 14.1 Functions of Serial Interface UART0 Addition of setting data when target baud rate is 312500 bps and 625000 bps to Table 14-5 Set Data of Baud Rate Generator Change of maximum transfer rate in 15.1 Functions of Serial Interface UART6 Change of output clock selection range and Remark 2 in Figure 15-9 Format of Baud Rate Generator Control Register 6 (BRGC6) Partial change of description in 15.4.3 (2) Generation of serial clock CHAPTER 13 A/D CONVERTER CHAPTER 14 SERIAL INTERFACE UART0 CHAPTER 15 SERIAL INTERFACE UART6 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS H0 AND H1 Chapter CHAPTER 6 CLOCK GENERATOR CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 744 User's Manual U17397EJ4V0UD APPENDIX E REVISION HISTORY www..com (11/13) Edition 3rd edition Description Addition of data to be set where target baud rate is 625000 bps to and change of Remark 2 in Table 15-5 Set Data of Baud Rate Generator Addition of error if division ratio (k) is 4 to Table 15-6 Maximum/Minimum Permissible Baud Rate Error Partial change of condition in which STCEN bit is cleared in Figure 18-7 Format of IIC Flag Register 0 (IICF0) Addition of descriptions (1) Master operation in single master system, (2) Master operation in multimaster system, and (3) Slave operation to 18.5.16 Communication operations Partial change of Figure 18-23 Master Operation in Single-Master System Partial change of Figure 18-25 Slave Operation Flowchart (1) Addition of oscillation accuracy stabilization time to and change of reset processing time in Figure 22-4 HALT Mode Release by Reset Change of Caution 4 in 22.2.2 (1) STOP mode setting and operating statuses Addition of oscillation accuracy stabilization time to and change of CPU clock supply stop time after STOP mode is released when AMPH = 1 in Figure 22-5 Operation Timing When STOP Mode Is Released Addition of oscillation accuracy stabilization time to (2) When internal high-speed oscillation clock is used as CPU clock in Figure 22-6 STOP Mode Release by Interrupt Request Generation Addition of oscillation accuracy stabilization time to and change of reset processing time in Figure 22-7 STOP Mode Release by Reset Addition of oscillation accuracy stabilization time to Figures 23-2 Timing of Reset by RESET Input to 23-4 Timing of Reset in STOP Mode by RESET Input, change of reset processing time Partial change of description in 24.1 Functions of Power-on-Clear Circuit and 24.3 Operation of Power-on-Clear Circuit Change of voltage stabilization wait time and reset processing time in and addition of oscillation accuracy stabilization wait time and Note 3 to (1) In 1.59 V POC mode (option byte: POCMODE = 0) in Figure 24-2 Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector Change of reset processing time in and addition of oscillation accuracy stabilization wait time and Note 2 to (2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) in Figure 24-2 Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and LowVoltage Detector Change and addition of description in 25.1 Functions of Low-Voltage Detector Change of description of LVIMD bit in Figure 25-2 Format of Low-Voltage Detection Register (LVIM) Change and addition of description in 25.4 Operation of Low-Voltage Detector Change of Figure 25-7 Timing of Low-Voltage Detector Interrupt Signal Generation (Detects Level of Supply Voltage (VDD)) and Figure 25-8 Timing of Low-Voltage Detector Interrupt Signal Generation (Detects Level of Input Voltage from External Input Pin (EXLVI)) Addition of Caution to (1) 0080H/1080H and (2) 0081H/1081H in 26.1 Functions of Option Bytes Change of Note 2 in Table 27-3 Wiring Between 78K0/KF2 and Dedicated Flash Programmer CHAPTER 26 OPTION BYTE CHAPTER 27 FLASH MEMORY CHAPTER 25 LOWVOLTAGE DETECTOR CHAPTER 23 RESET FUNCTION CHAPTER 24 POWER-ON-CLEAR CIRCUIT CHAPTER 22 STANDBY FUNCTION Chapter CHAPTER 15 SERIAL INTERFACE UART6 CHAPTER 18 SERIAL INTERFACE IIC0 User's Manual U17397EJ4V0UD 745 APPENDIX E REVISION HISTORY www..com (12/13) Edition 3rd edition Description Addition of Note to Figure 27-4 Example of Wiring Adapter for Flash Memory Writing in UART (UART6) Mode Addition of Note to Figure 27-7 Communication with Dedicated Flash Programmer (UART6) Change of Note 1 in Table 27-4 Pin Connection Change of Figure 27-8 FLMD0 Pin Connection Example and change of description Addition of Caution 3, Note, and Remark to 27.6.6 Other signal pins Change of Table 27-7 Communication Modes Change of Table 27-8 Flash Memory Control Commands Partial change of description in 27.8 Security Settings Change of Table 27-10 Relationship Between Enabling Security Function and Command Change of Table 27-11 Setting Security in Each Programming Mode Addition of 27.9 Processing Time for Each Command When PG-FP4 Is Used (Reference) Deletion of Caution 5 from 27.10 Flash Memory Programming by Self-Programming Change of Figure 27-16 Flow of Self Programming (Rewriting Flash Memory) Addition of Table 27-13 Processing Time and Interrupt Response Time for Self Programming Sample Library Partial change of boot start position in Figure 27-17 Boot Swap Function Addition of recommended resistance to Note of Figure 28-1 Connection Example of QB78K0MINI and PD78F0547D (When OCD0A/X1 and OCD0B/X2 Are Used) and Figure 28-2 Connection Example of QB-78K0MINI and PD78F0547D (When OCD1A and OCD1B Are Used) Addition of Figure 28-3 Connection of FLMD0 Pin for Self Programming or On-Chip Debugging Change of following items of Absolute Maximum Ratings * Output current, high (addition of values of P20 to P27 and P121 to P124) * Output current, low (addition of values of P20 to P27 and P121 to P124) Addition of value when RSTS = 0 to 8 MHz internal oscillator in Internal Oscillator Characteristics Addition of recommended oscillator for X1 oscillation and XT1 oscillation and oscillator constants Change of following items of DC Characteristics * Input voltage, high (change of values of P60 to P63) * Input voltage, low (change of values of P60 to P62) * Output voltage, low (addition of values in this condition: P60 to P63, 2.7 V VDD < 4.0 V, IOL1 = 5.0 mA) * Supply current (change of values when square wave is input in operation mode and HALT mode, and addition of values for oscillator connection). Addition of values where TA = -40 to +70C in STOP mode. Addition of Note 2. Change of Notes 1 and 5 * A/D converter operating current (addition of values while converter is not operating (when comparator operates). Addition of Note 2) Change of following items of AC Characteristics * TI000, TI010, TI001, TI011 input high-level width, low-level width (addition of values in condition where 1.8 V VDD < 2.7 V) in (1) Basic operation * Transfer rate (change of values) in (2) Serial interface (a) UART6 and (b) UART0 Addition of MIN. and MAX. values as detection voltages of external input pin in LVI Circuit Characteristics CHAPTER 28 ONCHIP DEBUG FUNCTION (PD78F0547D ONLY) Chapter CHAPTER 15 SERIAL INTERFACE UART6 CHAPTER 30 ELECTRICAL SPECIFICATIONS 746 User's Manual U17397EJ4V0UD APPENDIX E REVISION HISTORY www..com (13/13) Edition 3rd edition Description Addition of Note 1 and value of write time to Basic Characteristics of Flash Memory Programming Characteristics. Deletion of "(2) Serial write operation characteristics" of old edition, and introduction of other manual Addition of chapter Chapter CHAPTER 30 ELECTRICAL SPECIFICATIONS CHAPTER 32 RECOMMENDED SOLDERING CONDITIONS APPENDIX A DEVELOPMENT TOOLS APPENDIX D LIST OF CAUTIONS APPENDIX E REVISION HISTORY Addition of FP-LITE3, FA-78F0547GC-UBT-MX and FA-78F0547GK-8EU-MX and Remark 2 to A.4 Flash Memory Programming Tools Addition of chapter Addition of E.2 Revision History of Preceding Editions User's Manual U17397EJ4V0UD 747 www..com For further information, please contact: NEC Electronics Corporation 1753, Shimonumabe, Nakahara-ku, Kawasaki, Kanagawa 211-8668, Japan Tel: 044-435-5111 http://www.necel.com/ [America] NEC Electronics America, Inc. 2880 Scott Blvd. Santa Clara, CA 95050-2554, U.S.A. Tel: 408-588-6000 800-366-9782 http://www.am.necel.com/ [Europe] NEC Electronics (Europe) GmbH Arcadiastrasse 10 40472 Dusseldorf, Germany Tel: 0211-65030 http://www.eu.necel.com/ Hanover Office Podbielski Strasse 166 B 30177 Hanover Tel: 0 511 33 40 2-0 Munich Office Werner-Eckert-Strasse 9 81829 Munchen Tel: 0 89 92 10 03-0 Stuttgart Office Industriestrasse 3 70565 Stuttgart Tel: 0 711 99 01 0-0 United Kingdom Branch Cygnus House, Sunrise Parkway Linford Wood, Milton Keynes MK14 6NP, U.K. Tel: 01908-691-133 Succursale Francaise 9, rue Paul Dautier, B.P. 52180 78142 Velizy-Villacoublay Cedex France Tel: 01-3067-5800 Sucursal en Espana Juan Esplandiu, 15 28007 Madrid, Spain Tel: 091-504-2787 Tyskland Filial Taby Centrum Entrance S (7th floor) 18322 Taby, Sweden Tel: 08 638 72 00 Filiale Italiana Via Fabio Filzi, 25/A 20124 Milano, Italy Tel: 02-667541 Branch The Netherlands Limburglaan 5 5616 HR Eindhoven The Netherlands Tel: 040 265 40 10 G05.12A [Asia & Oceania] NEC Electronics (China) Co., Ltd 7th Floor, Quantum Plaza, No. 27 ZhiChunLu Haidian District, Beijing 100083, P.R.China TEL: 010-8235-1155 http://www.cn.necel.com/ NEC Electronics Shanghai Ltd. Room 2509-2510, Bank of China Tower, 200 Yincheng Road Central, Pudong New Area, Shanghai P.R. China P.C:200120 Tel: 021-5888-5400 http://www.cn.necel.com/ NEC Electronics Hong Kong Ltd. 12/F., Cityplaza 4, 12 Taikoo Wan Road, Hong Kong Tel: 2886-9318 http://www.hk.necel.com/ Seoul Branch 11F., Samik Lavied'or Bldg., 720-2, Yeoksam-Dong, Kangnam-Ku, Seoul, 135-080, Korea Tel: 02-558-3737 NEC Electronics Taiwan Ltd. 7F, No. 363 Fu Shing North Road Taipei, Taiwan, R. O. C. Tel: 02-2719-2377 NEC Electronics Singapore Pte. Ltd. 238A Thomson Road, #12-08 Novena Square, Singapore 307684 Tel: 6253-8311 http://www.sg.necel.com/ |
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